Commit 93ce8d1f authored by Dimitris Lampridis's avatar Dimitris Lampridis

board: rename WB slave port, to be consistent across all boards

parent b60c3bb0
......@@ -124,8 +124,8 @@ package wr_board_pkg is
owr_pwren_o : out std_logic_vector(1 downto 0);
owr_en_o : out std_logic_vector(1 downto 0);
owr_i : in std_logic_vector(1 downto 0) := (others => '1');
slave_i : in t_wishbone_slave_in := cc_dummy_slave_in;
slave_o : out t_wishbone_slave_out;
wb_slave_i : in t_wishbone_slave_in := cc_dummy_slave_in;
wb_slave_o : out t_wishbone_slave_out;
aux_master_o : out t_wishbone_master_out;
aux_master_i : in t_wishbone_master_in := cc_dummy_master_in;
wrf_src_o : out t_wrf_source_out;
......
......@@ -7,7 +7,7 @@
-- Author(s) : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-02-22
-- Last update: 2017-02-22
-- Last update: 2017-03-07
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Wrapper for WR PTP core with common features shared between
......@@ -156,8 +156,8 @@ entity xwrc_board_common is
---------------------------------------------------------------------------
--External WB interface
---------------------------------------------------------------------------
slave_i : in t_wishbone_slave_in := cc_dummy_slave_in;
slave_o : out t_wishbone_slave_out;
wb_slave_i : in t_wishbone_slave_in := cc_dummy_slave_in;
wb_slave_o : out t_wishbone_slave_out;
aux_master_o : out t_wishbone_master_out;
aux_master_i : in t_wishbone_master_in := cc_dummy_master_in;
......
......@@ -7,7 +7,7 @@
-- Author(s) : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2016-02-17
-- Last update: 2017-02-22
-- Last update: 2017-03-07
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level wrapper for WR PTP core including all the modules
......
......@@ -7,7 +7,7 @@
-- Author(s) : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-02-17
-- Last update: 2017-02-22
-- Last update: 2017-03-07
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level wrapper for WR PTP core including all the modules
......@@ -436,8 +436,8 @@ begin -- architecture struct
owr_pwren_o => open,
owr_en_o => onewire_en,
owr_i => onewire_in,
slave_i => wb_slave_i,
slave_o => wb_slave_o,
wb_slave_i => wb_slave_i,
wb_slave_o => wb_slave_o,
wrf_src_o => wrf_src_o,
wrf_src_i => wrf_src_i,
wrf_snk_o => wrf_snk_o,
......
......@@ -7,7 +7,7 @@
-- Author(s) : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-02-16
-- Last update: 2017-02-20
-- Last update: 2017-03-07
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level wrapper for WR PTP core including all the modules
......@@ -451,8 +451,8 @@ begin -- architecture struct
owr_pwren_o => open,
owr_en_o => onewire_en,
owr_i => onewire_in,
slave_i => wb_slave_i,
slave_o => wb_slave_o,
wb_slave_i => wb_slave_i,
wb_slave_o => wb_slave_o,
wrf_src_o => wrf_src_o,
wrf_src_i => wrf_src_i,
wrf_snk_o => wrf_snk_o,
......
......@@ -7,7 +7,7 @@
-- Author(s) : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2016-07-26
-- Last update: 2017-03-06
-- Last update: 2017-03-07
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level wrapper for WR PTP core including all the modules
......@@ -431,8 +431,8 @@ begin -- architecture struct
owr_pwren_o => open,
owr_en_o => onewire_en,
owr_i => onewire_in,
slave_i => wb_slave_i,
slave_o => wb_slave_o,
wb_slave_i => wb_slave_i,
wb_slave_o => wb_slave_o,
wrf_src_o => wrf_src_o,
wrf_src_i => wrf_src_i,
wrf_snk_o => wrf_snk_o,
......
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