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White Rabbit core collection
Commit 97652bb9 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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gsi_scu/wr_core_demo: replaced MiniBone with real EtherBone

parent 9dfd9435
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Showing with 46 additions and 11 deletions
syn/gsi_scu/wr_core_demo/exploder_ng.qsf
View file @ 97652bb9
......@@ -56,6 +56,10 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to serial_to_cb_o
set_location_assignment PIN_U27 -to sfp_rxp_i
set_location_assignment PIN_AH17 -to sfp_tx_disable_o
set_location_assignment PIN_T25 -to sfp_txp_o
set_location_assignment PIN_H4 -to leds_o[0]
set_location_assignment PIN_J5 -to leds_o[1]
set_location_assignment PIN_H3 -to leds_o[2]
set_location_assignment PIN_J4 -to leds_o[3]
set_global_assignment -name VHDL_FILE ../../../modules/fabric/wr_fabric_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../top/gsi_scu/wr_core_demo/pow_reset.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd
......@@ -199,11 +203,22 @@ set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wi
set_global_assignment -name VHDL_FILE ../../../modules/wr_mini_nic/minic_wb_slave.vhd
set_global_assignment -name VHDL_FILE ../../../modules/mini_bone/mini_bone.vhd
set_global_assignment -name VHDL_FILE ../../../modules/mini_bone/xmini_bone.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/etherbone-core/hdl/EB_SPEC_Test/alt_FIFO_am_full_flag.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/etherbone-core/hdl/EB_SPEC_Test/EB_HDR_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/etherbone-core/hdl/EB_SPEC_Test/EB_checksum.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/etherbone-core/hdl/EB_SPEC_Test/wishbone_package32.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/etherbone-core/hdl/EB_SPEC_Test/wishbone_package16.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/etherbone-core/hdl/EB_SPEC_Test/EB_2_wb_converter.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/etherbone-core/hdl/EB_SPEC_Test/EB_RX_CTRL.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/etherbone-core/hdl/EB_SPEC_Test/EB_TX_CTRL.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/etherbone-core/hdl/EB_SPEC_Test/piso_flag.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/etherbone-core/hdl/EB_SPEC_Test/vhdl_2008_workaround_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/etherbone-core/hdl/EB_SPEC_Test/sipo_flag.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/etherbone-core/hdl/EB_SPEC_Test/WB_bus_adapter_streaming_sg.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/etherbone-core/hdl/EB_SPEC_Test/EB_CORE.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/etherbone-core/hdl/EB_SPEC_Test/eb_config_new.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/etherbone-core/hdl/EB_SPEC_Test/xetherbone_core.vhd
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_location_assignment PIN_H4 -to leds_o[0]
set_location_assignment PIN_J5 -to leds_o[1]
set_location_assignment PIN_H3 -to leds_o[2]
set_location_assignment PIN_J4 -to leds_o[3]
\ No newline at end of file
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
top/gsi_scu/wr_core_demo/Manifest.py
View file @ 97652bb9
modules = {"local" : "../../../modules/mini_bone"}
files = ["exploder_ng.vhd", "pow_reset.vhd"]
\ No newline at end of file
fetchto = "../../../ip_cores"
modules = {
"local" : "../../../modules/mini_bone",
"svn" : "http://svn.ohwr.org/etherbone-core/hdl/EB_SPEC_Test"
};
files = ["exploder_ng.vhd", "pow_reset.vhd"]
top/gsi_scu/wr_core_demo/exploder_ng.vhd
View file @ 97652bb9
......@@ -160,6 +160,19 @@ architecture rtl of EXPLODER_ng is
master_i : in t_wishbone_master_in);
end component;
component xetherbone_core
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
snk_i : in t_wrf_sink_in;
snk_o : out t_wrf_sink_out;
src_i : in t_wrf_source_in;
src_o : out t_wrf_source_out;
master_i : in t_wishbone_master_in;
master_o : out t_wishbone_master_out);
end component;
-- LCLK from GN4124 used as system clock
signal l_clk : std_logic;
......@@ -235,6 +248,8 @@ architecture rtl of EXPLODER_ng is
signal mb_master_in : t_wishbone_master_in;
signal dummy_gpio, gpio_out : std_logic_vector(31 downto 0);
begin
......@@ -331,11 +346,10 @@ begin
pad_txp_o => sfp_txp_o,
pad_rxp_i => sfp_rxp_i);
U_mbone : xmini_bone
generic map (
g_class_mask => x"f0",
g_our_ethertype => x"a0a0")
U_ebone : xetherbone_core
port map (
clk_sys_i => l_cLKp,
rst_n_i => nreset,
......
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