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White Rabbit core collection
Commit 9876e112 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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simulation models: bugfixes

parent 9d8b618f
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Showing with 33 additions and 12 deletions
sim/drivers/simdrv_minic.svh
View file @ 9876e112
...@@ -13,7 +13,7 @@ class CSimDrv_Minic; ...@@ -13,7 +13,7 @@ class CSimDrv_Minic;
`define RX_DESC_VALID(d) ((d) & (1<<31) ? 1 : 0) `define RX_DESC_VALID(d) ((d) & (1<<31) ? 1 : 0)
`define RX_DESC_ERROR(d) ((d) & (1<<30) ? 1 : 0) `define RX_DESC_ERROR(d) ((d) & (1<<30) ? 1 : 0)
`define RX_DESC_HAS_OOB(d) ((d) & (1<<29) ? 1 : 0) `define RX_DESC_HAS_OOB(d) ((d) & (1<<29) ? 1 : 0)
`define RX_DESC_SIZE(d) (((d) & (1<<0) ? -1 : 0) + (d & 'hfffe)) `define RX_DESC_SIZE(d) (((d) & (1<<0) ? -1 : 0) + (d & 'hffe))
protected CBusAccessor acc_regs, acc_pmem; protected CBusAccessor acc_regs, acc_pmem;
protected uint32_t base_regs, base_pmem; protected uint32_t base_regs, base_pmem;
...@@ -126,13 +126,15 @@ class CSimDrv_Minic; ...@@ -126,13 +126,15 @@ class CSimDrv_Minic;
minic_readl(`ADDR_MINIC_EIC_ISR, isr); minic_readl(`ADDR_MINIC_EIC_ISR, isr);
// $display("RXFrame");
if(! (isr & `MINIC_EIC_ISR_RX)) if(! (isr & `MINIC_EIC_ISR_RX))
return; return;
acc_pmem.read(rx_head, desc_hdr); acc_pmem.read(rx_head, desc_hdr);
if(!`RX_DESC_VALID(desc_hdr)) if(!`RX_DESC_VALID(desc_hdr))
begin begin
...@@ -140,11 +142,18 @@ class CSimDrv_Minic; ...@@ -140,11 +142,18 @@ class CSimDrv_Minic;
$stop; $stop;
end end
payload_size = `RX_DESC_SIZE(desc_hdr); payload_size = `RX_DESC_SIZE(desc_hdr);
num_words = (payload_size + 3) >> 2; num_words = (payload_size + 3) >> 2;
pbuff = new [num_words]; pbuff = new [num_words];
// $display("NWords %d hdr %x", num_words, desc_hdr);
if(`RX_DESC_HAS_OOB(desc_hdr))
payload_size = payload_size - 6;
if(!`RX_DESC_ERROR(desc_hdr)) if(!`RX_DESC_ERROR(desc_hdr))
begin begin
for(i=0; i<num_words;i++) for(i=0; i<num_words;i++)
......
sim/eth_packet.svh
View file @ 9876e112
...@@ -43,6 +43,7 @@ class EthPacket; ...@@ -43,6 +43,7 @@ class EthPacket;
bit error; bit error;
bit [15:0] ethertype; bit [15:0] ethertype;
bit [7:0] pclass;
vid_t vid; vid_t vid;
pcp_t pcp; pcp_t pcp;
......
sim/if_wb_master.svh
View file @ 9876e112
...@@ -18,8 +18,8 @@ interface IWishboneMaster ...@@ -18,8 +18,8 @@ interface IWishboneMaster
input rst_n_i input rst_n_i
); );
parameter g_data_width = 32;
parameter g_addr_width = 32; parameter g_addr_width = 32;
parameter g_data_width = 32;
logic [g_addr_width - 1 : 0] adr; logic [g_addr_width - 1 : 0] adr;
logic [g_data_width - 1 : 0] dat_o; logic [g_data_width - 1 : 0] dat_o;
...@@ -256,6 +256,7 @@ interface IWishboneMaster ...@@ -256,6 +256,7 @@ interface IWishboneMaster
begin begin
stb <= 1'b1; stb <= 1'b1;
we <= 1'b1; we <= 1'b1;
while(stall) while(stall)
begin begin
count_ack(ack_count); count_ack(ack_count);
......
sim/if_wb_slave.svh
View file @ 9876e112
...@@ -152,15 +152,21 @@ interface IWishboneSlave ...@@ -152,15 +152,21 @@ interface IWishboneSlave
task pipelined_fsm(); task pipelined_fsm();
if(settings.gen_random_stalls)
gen_random_stalls();
else
stall <= 0;
/* -----\/----- EXCLUDED -----\/-----
if(cyc) begin if(cyc) begin
if(settings.gen_random_stalls)
gen_random_stalls();
end else end else
stall <= 0; stall <= 0;
-----/\----- EXCLUDED -----/\----- */
if(cyc_start) begin if(cyc_start) begin
current_cycle.data = {}; current_cycle.data = {};
trans_index <= 0; trans_index <= 0;
first_transaction = 1; first_transaction = 1;
end end
......
sim/wb_packet_sink.svh
View file @ 9876e112
...@@ -35,6 +35,8 @@ class WBPacketSink extends EthPacketSink; ...@@ -35,6 +35,8 @@ class WBPacketSink extends EthPacketSink;
else begin else begin
pkt.has_smac = (stat & 'h4 ? 1'b1 : 1'b0); pkt.has_smac = (stat & 'h4 ? 1'b1 : 1'b0);
pkt.has_crc = (stat & 'h8 ? 1'b1 : 1'b0); pkt.has_crc = (stat & 'h8 ? 1'b1 : 1'b0);
pkt.pclass = (stat>>8) & 'hff;
end end
endtask // decode_status endtask // decode_status
......
sim/wb_packet_source.svh
View file @ 9876e112
...@@ -27,7 +27,9 @@ class WBPacketSource extends EthPacketSource; ...@@ -27,7 +27,9 @@ class WBPacketSource extends EthPacketSource;
st[1] = 1'b0; st[1] = 1'b0;
st[2] = (pkt.has_smac ? 1'b1: 1'b0); st[2] = (pkt.has_smac ? 1'b1: 1'b0);
st[3] = error; st[3] = error;
st[15:3] = 0; // FIXME: add packet classes st[15:8] = pkt.pclass; // FIXME: add packet classes
st[7:4]= 0;
return st; return st;
endfunction // pack_status endfunction // pack_status
......
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