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White Rabbit core collection
Commits
991af743
Commit
991af743
authored
Apr 21, 2017
by
Maciej Lipinski
Committed by
Grzegorz Daniluk
Jun 19, 2017
Browse files
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Plain Diff
[streamers/review] added streamers wrs_t/rx_cfg_i interface to all boards
parent
ef1fdd7a
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Showing
11 changed files
with
130 additions
and
8 deletions
+130
-8
wr_board_pkg.vhd
board/common/wr_board_pkg.vhd
+2
-0
xwrc_board_common.vhd
board/common/xwrc_board_common.vhd
+5
-2
wr_spec_pkg.vhd
board/spec/wr_spec_pkg.vhd
+11
-0
wrc_board_spec.vhd
board/spec/wrc_board_spec.vhd
+26
-1
xwrc_board_spec.vhd
board/spec/xwrc_board_spec.vhd
+4
-1
wr_svec_pkg.vhd
board/svec/wr_svec_pkg.vhd
+11
-0
wrc_board_svec.vhd
board/svec/wrc_board_svec.vhd
+26
-1
xwrc_board_svec.vhd
board/svec/xwrc_board_svec.vhd
+4
-1
wr_vfchd_pkg.vhd
board/vfchd/wr_vfchd_pkg.vhd
+11
-0
wrc_board_vfchd.vhd
board/vfchd/wrc_board_vfchd.vhd
+26
-1
xwrc_board_vfchd.vhd
board/vfchd/xwrc_board_vfchd.vhd
+4
-1
No files found.
board/common/wr_board_pkg.vhd
View file @
991af743
...
...
@@ -140,6 +140,8 @@ package wr_board_pkg is
wrs_rx_data_o
:
out
std_logic_vector
(
g_rx_streamer_params
.
data_width
-1
downto
0
);
wrs_rx_valid_o
:
out
std_logic
;
wrs_rx_dreq_i
:
in
std_logic
:
=
'0'
;
wrs_tx_cfg_i
:
in
t_tx_streamer_cfg
:
=
c_tx_streamer_cfg_default
;
wrs_rx_cfg_i
:
in
t_rx_streamer_cfg
:
=
c_rx_streamer_cfg_default
;
wb_eth_master_o
:
out
t_wishbone_master_out
;
wb_eth_master_i
:
in
t_wishbone_master_in
:
=
cc_dummy_master_in
;
aux_diag_i
:
in
t_generic_word_array
(
g_diag_ro_size
-1
downto
0
)
:
=
(
others
=>
(
others
=>
'0'
));
...
...
board/common/xwrc_board_common.vhd
View file @
991af743
...
...
@@ -188,7 +188,8 @@ entity xwrc_board_common is
wrs_rx_data_o
:
out
std_logic_vector
(
g_rx_streamer_params
.
data_width
-1
downto
0
);
wrs_rx_valid_o
:
out
std_logic
;
wrs_rx_dreq_i
:
in
std_logic
:
=
'0'
;
wrs_tx_cfg_i
:
in
t_tx_streamer_cfg
:
=
c_tx_streamer_cfg_default
;
wrs_rx_cfg_i
:
in
t_rx_streamer_cfg
:
=
c_rx_streamer_cfg_default
;
---------------------------------------------------------------------------
-- Etherbone WB master interface (when g_fabric_iface = ETHERBONE)
---------------------------------------------------------------------------
...
...
@@ -451,7 +452,9 @@ begin -- architecture struct
wb_slave_i
=>
aux_master_out
,
wb_slave_o
=>
aux_master_in
,
snmp_array_o
=>
aux_diag_in
(
c_WR_TRANS_ARR_SIZE_OUT
-1
downto
0
),
snmp_array_i
=>
aux_diag_out
(
c_WR_TRANS_ARR_SIZE_IN
-1
downto
0
));
snmp_array_i
=>
aux_diag_out
(
c_WR_TRANS_ARR_SIZE_IN
-1
downto
0
),
tx_streamer_cfg_i
=>
wrs_tx_cfg_i
,
rx_streamer_cfg_i
=>
wrs_rx_cfg_i
);
-- unused output ports
wrf_src_o
<=
c_dummy_snk_in
;
...
...
board/spec/wr_spec_pkg.vhd
View file @
991af743
...
...
@@ -79,11 +79,13 @@ package wr_spec_pkg is
wrs_tx_dreq_o
:
out
std_logic
;
wrs_tx_last_i
:
in
std_logic
:
=
'1'
;
wrs_tx_flush_i
:
in
std_logic
:
=
'0'
;
wrs_tx_cfg_i
:
in
t_tx_streamer_cfg
:
=
c_tx_streamer_cfg_default
;
wrs_rx_first_o
:
out
std_logic
;
wrs_rx_last_o
:
out
std_logic
;
wrs_rx_data_o
:
out
std_logic_vector
(
g_rx_streamer_params
.
data_width
-1
downto
0
);
wrs_rx_valid_o
:
out
std_logic
;
wrs_rx_dreq_i
:
in
std_logic
:
=
'0'
;
wrs_rx_cfg_i
:
in
t_rx_streamer_cfg
:
=
c_rx_streamer_cfg_default
;
wb_eth_master_o
:
out
t_wishbone_master_out
;
wb_eth_master_i
:
in
t_wishbone_master_in
:
=
cc_dummy_master_in
;
aux_diag_i
:
in
t_generic_word_array
(
g_diag_ro_size
-1
downto
0
)
:
=
(
others
=>
(
others
=>
'0'
));
...
...
@@ -204,11 +206,20 @@ package wr_spec_pkg is
wrs_tx_dreq_o
:
out
std_logic
;
wrs_tx_last_i
:
in
std_logic
:
=
'1'
;
wrs_tx_flush_i
:
in
std_logic
:
=
'0'
;
wrs_tx_cfg_mac_l_i
:
in
std_logic_vector
(
47
downto
0
)
:
=
x"000000000000"
;
wrs_tx_cfg_mac_t_i
:
in
std_logic_vector
(
47
downto
0
)
:
=
x"ffffffffffff"
;
wrs_tx_cfg_etype_i
:
in
std_logic_vector
(
15
downto
0
)
:
=
x"dbff"
;
wrs_rx_first_o
:
out
std_logic
;
wrs_rx_last_o
:
out
std_logic
;
wrs_rx_data_o
:
out
std_logic_vector
(
g_rx_streamer_params
.
data_width
-1
downto
0
);
wrs_rx_valid_o
:
out
std_logic
;
wrs_rx_dreq_i
:
in
std_logic
:
=
'0'
;
wrs_rx_cfg_mac_l_i
:
in
std_logic_vector
(
47
downto
0
)
:
=
x"000000000000"
;
wrs_rx_cfg_mac_r_i
:
in
std_logic_vector
(
47
downto
0
)
:
=
x"000000000000"
;
wrs_rx_cfg_etype_i
:
in
std_logic_vector
(
15
downto
0
)
:
=
x"dbff"
;
wrs_rx_cfg_acc_b_i
:
in
std_logic
:
=
'1'
;
wrs_rx_cfg_flt_r_i
:
in
std_logic
:
=
'0'
;
wrs_rx_cfg_fix_l_i
:
in
std_logic_vector
(
27
downto
0
)
:
=
x"0000000"
;
wb_eth_adr_o
:
out
std_logic_vector
(
c_wishbone_address_width
-1
downto
0
);
wb_eth_dat_o
:
out
std_logic_vector
(
c_wishbone_data_width
-1
downto
0
);
wb_eth_dat_i
:
in
std_logic_vector
(
c_wishbone_data_width
-1
downto
0
)
:
=
(
others
=>
'0'
);
...
...
board/spec/wrc_board_spec.vhd
View file @
991af743
...
...
@@ -203,12 +203,20 @@ entity wrc_board_spec is
wrs_tx_dreq_o
:
out
std_logic
;
wrs_tx_last_i
:
in
std_logic
:
=
'1'
;
wrs_tx_flush_i
:
in
std_logic
:
=
'0'
;
wrs_tx_cfg_mac_l_i
:
in
std_logic_vector
(
47
downto
0
)
:
=
x"000000000000"
;
wrs_tx_cfg_mac_t_i
:
in
std_logic_vector
(
47
downto
0
)
:
=
x"ffffffffffff"
;
wrs_tx_cfg_etype_i
:
in
std_logic_vector
(
15
downto
0
)
:
=
x"dbff"
;
wrs_rx_first_o
:
out
std_logic
;
wrs_rx_last_o
:
out
std_logic
;
wrs_rx_data_o
:
out
std_logic_vector
(
g_rx_streamer_params
.
data_width
-1
downto
0
);
wrs_rx_valid_o
:
out
std_logic
;
wrs_rx_dreq_i
:
in
std_logic
:
=
'0'
;
wrs_rx_cfg_mac_l_i
:
in
std_logic_vector
(
47
downto
0
)
:
=
x"000000000000"
;
wrs_rx_cfg_mac_r_i
:
in
std_logic_vector
(
47
downto
0
)
:
=
x"000000000000"
;
wrs_rx_cfg_etype_i
:
in
std_logic_vector
(
15
downto
0
)
:
=
x"dbff"
;
wrs_rx_cfg_acc_b_i
:
in
std_logic
:
=
'1'
;
wrs_rx_cfg_flt_r_i
:
in
std_logic
:
=
'0'
;
wrs_rx_cfg_fix_l_i
:
in
std_logic_vector
(
27
downto
0
)
:
=
x"0000000"
;
---------------------------------------------------------------------------
-- Etherbone WB master interface (when g_fabric_iface = "etherbone")
---------------------------------------------------------------------------
...
...
@@ -311,6 +319,10 @@ architecture std_wrapper of wrc_board_spec is
-- External Tx Timestamping I/F
signal
timestamps_out
:
t_txtsu_timestamp
;
-- streamers config
signal
wrs_tx_cfg_in
:
t_tx_streamer_cfg
;
signal
wrs_rx_cfg_in
:
t_rx_streamer_cfg
;
begin
-- architecture struct
-- Map top-level signals to internal records
...
...
@@ -373,6 +385,17 @@ begin -- architecture struct
tstamps_port_id_o
<=
timestamps_out
.
port_id
;
tstamps_frame_id_o
<=
timestamps_out
.
frame_id
;
wrs_tx_cfg_in
.
mac_local
<=
wrs_tx_cfg_mac_l_i
;
wrs_tx_cfg_in
.
mac_target
<=
wrs_tx_cfg_mac_t_i
;
wrs_tx_cfg_in
.
ethertype
<=
wrs_tx_cfg_etype_i
;
wrs_rx_cfg_in
.
mac_local
<=
wrs_rx_cfg_mac_l_i
;
wrs_rx_cfg_in
.
mac_remote
<=
wrs_rx_cfg_mac_r_i
;
wrs_rx_cfg_in
.
ethertype
<=
wrs_rx_cfg_etype_i
;
wrs_rx_cfg_in
.
accept_broadcasts
<=
wrs_rx_cfg_acc_b_i
;
wrs_rx_cfg_in
.
filter_remote
<=
wrs_rx_cfg_flt_r_i
;
wrs_rx_cfg_in
.
fixed_latency
<=
wrs_rx_cfg_fix_l_i
;
-- Instantiate the records-based module
cmp_xwrc_board_spec
:
xwrc_board_spec
generic
map
(
...
...
@@ -441,11 +464,13 @@ begin -- architecture struct
wrs_tx_dreq_o
=>
wrs_tx_dreq_o
,
wrs_tx_last_i
=>
wrs_tx_last_i
,
wrs_tx_flush_i
=>
wrs_tx_flush_i
,
wrs_tx_cfg_i
=>
wrs_tx_cfg_in
,
wrs_rx_first_o
=>
wrs_rx_first_o
,
wrs_rx_last_o
=>
wrs_rx_last_o
,
wrs_rx_data_o
=>
wrs_rx_data_o
,
wrs_rx_valid_o
=>
wrs_rx_valid_o
,
wrs_rx_dreq_i
=>
wrs_rx_dreq_i
,
wrs_rx_cfg_i
=>
wrs_rx_cfg_in
,
wb_eth_master_o
=>
wb_eth_master_out
,
wb_eth_master_i
=>
wb_eth_master_in
,
aux_diag_i
=>
aux_diag_in
,
...
...
board/spec/xwrc_board_spec.vhd
View file @
991af743
...
...
@@ -180,12 +180,13 @@ entity xwrc_board_spec is
wrs_tx_dreq_o
:
out
std_logic
;
wrs_tx_last_i
:
in
std_logic
:
=
'1'
;
wrs_tx_flush_i
:
in
std_logic
:
=
'0'
;
wrs_tx_cfg_i
:
in
t_tx_streamer_cfg
:
=
c_tx_streamer_cfg_default
;
wrs_rx_first_o
:
out
std_logic
;
wrs_rx_last_o
:
out
std_logic
;
wrs_rx_data_o
:
out
std_logic_vector
(
g_rx_streamer_params
.
data_width
-1
downto
0
);
wrs_rx_valid_o
:
out
std_logic
;
wrs_rx_dreq_i
:
in
std_logic
:
=
'0'
;
wrs_rx_cfg_i
:
in
t_rx_streamer_cfg
:
=
c_rx_streamer_cfg_default
;
---------------------------------------------------------------------------
-- Etherbone WB master interface (when g_fabric_iface = "etherbone")
---------------------------------------------------------------------------
...
...
@@ -462,11 +463,13 @@ begin -- architecture struct
wrs_tx_dreq_o
=>
wrs_tx_dreq_o
,
wrs_tx_last_i
=>
wrs_tx_last_i
,
wrs_tx_flush_i
=>
wrs_tx_flush_i
,
wrs_tx_cfg_i
=>
wrs_tx_cfg_i
,
wrs_rx_first_o
=>
wrs_rx_first_o
,
wrs_rx_last_o
=>
wrs_rx_last_o
,
wrs_rx_data_o
=>
wrs_rx_data_o
,
wrs_rx_valid_o
=>
wrs_rx_valid_o
,
wrs_rx_dreq_i
=>
wrs_rx_dreq_i
,
wrs_rx_cfg_i
=>
wrs_rx_cfg_i
,
wb_eth_master_o
=>
wb_eth_master_o
,
wb_eth_master_i
=>
wb_eth_master_i
,
aux_diag_i
=>
aux_diag_i
,
...
...
board/svec/wr_svec_pkg.vhd
View file @
991af743
...
...
@@ -81,11 +81,13 @@ package wr_svec_pkg is
wrs_tx_dreq_o
:
out
std_logic
;
wrs_tx_last_i
:
in
std_logic
:
=
'1'
;
wrs_tx_flush_i
:
in
std_logic
:
=
'0'
;
wrs_tx_cfg_i
:
in
t_tx_streamer_cfg
:
=
c_tx_streamer_cfg_default
;
wrs_rx_first_o
:
out
std_logic
;
wrs_rx_last_o
:
out
std_logic
;
wrs_rx_data_o
:
out
std_logic_vector
(
g_rx_streamer_params
.
data_width
-1
downto
0
);
wrs_rx_valid_o
:
out
std_logic
;
wrs_rx_dreq_i
:
in
std_logic
:
=
'0'
;
wrs_rx_cfg_i
:
in
t_rx_streamer_cfg
:
=
c_rx_streamer_cfg_default
;
wb_eth_master_o
:
out
t_wishbone_master_out
;
wb_eth_master_i
:
in
t_wishbone_master_in
:
=
cc_dummy_master_in
;
aux_diag_i
:
in
t_generic_word_array
(
g_diag_ro_size
-1
downto
0
)
:
=
(
others
=>
(
others
=>
'0'
));
...
...
@@ -207,11 +209,20 @@ package wr_svec_pkg is
wrs_tx_dreq_o
:
out
std_logic
;
wrs_tx_last_i
:
in
std_logic
:
=
'1'
;
wrs_tx_flush_i
:
in
std_logic
:
=
'0'
;
wrs_tx_cfg_mac_l_i
:
in
std_logic_vector
(
47
downto
0
)
:
=
x"000000000000"
;
wrs_tx_cfg_mac_t_i
:
in
std_logic_vector
(
47
downto
0
)
:
=
x"ffffffffffff"
;
wrs_tx_cfg_etype_i
:
in
std_logic_vector
(
15
downto
0
)
:
=
x"dbff"
;
wrs_rx_first_o
:
out
std_logic
;
wrs_rx_last_o
:
out
std_logic
;
wrs_rx_data_o
:
out
std_logic_vector
(
g_rx_streamer_params
.
data_width
-1
downto
0
);
wrs_rx_valid_o
:
out
std_logic
;
wrs_rx_dreq_i
:
in
std_logic
:
=
'0'
;
wrs_rx_cfg_mac_l_i
:
in
std_logic_vector
(
47
downto
0
)
:
=
x"000000000000"
;
wrs_rx_cfg_mac_r_i
:
in
std_logic_vector
(
47
downto
0
)
:
=
x"000000000000"
;
wrs_rx_cfg_etype_i
:
in
std_logic_vector
(
15
downto
0
)
:
=
x"dbff"
;
wrs_rx_cfg_acc_b_i
:
in
std_logic
:
=
'1'
;
wrs_rx_cfg_flt_r_i
:
in
std_logic
:
=
'0'
;
wrs_rx_cfg_fix_l_i
:
in
std_logic_vector
(
27
downto
0
)
:
=
x"0000000"
;
wb_eth_adr_o
:
out
std_logic_vector
(
c_wishbone_address_width
-1
downto
0
);
wb_eth_dat_o
:
out
std_logic_vector
(
c_wishbone_data_width
-1
downto
0
);
wb_eth_dat_i
:
in
std_logic_vector
(
c_wishbone_data_width
-1
downto
0
)
:
=
(
others
=>
'0'
);
...
...
board/svec/wrc_board_svec.vhd
View file @
991af743
...
...
@@ -205,12 +205,20 @@ entity wrc_board_svec is
wrs_tx_dreq_o
:
out
std_logic
;
wrs_tx_last_i
:
in
std_logic
:
=
'1'
;
wrs_tx_flush_i
:
in
std_logic
:
=
'0'
;
wrs_tx_cfg_mac_l_i
:
in
std_logic_vector
(
47
downto
0
)
:
=
x"000000000000"
;
wrs_tx_cfg_mac_t_i
:
in
std_logic_vector
(
47
downto
0
)
:
=
x"ffffffffffff"
;
wrs_tx_cfg_etype_i
:
in
std_logic_vector
(
15
downto
0
)
:
=
x"dbff"
;
wrs_rx_first_o
:
out
std_logic
;
wrs_rx_last_o
:
out
std_logic
;
wrs_rx_data_o
:
out
std_logic_vector
(
g_rx_streamer_params
.
data_width
-1
downto
0
);
wrs_rx_valid_o
:
out
std_logic
;
wrs_rx_dreq_i
:
in
std_logic
:
=
'0'
;
wrs_rx_cfg_mac_l_i
:
in
std_logic_vector
(
47
downto
0
)
:
=
x"000000000000"
;
wrs_rx_cfg_mac_r_i
:
in
std_logic_vector
(
47
downto
0
)
:
=
x"000000000000"
;
wrs_rx_cfg_etype_i
:
in
std_logic_vector
(
15
downto
0
)
:
=
x"dbff"
;
wrs_rx_cfg_acc_b_i
:
in
std_logic
:
=
'1'
;
wrs_rx_cfg_flt_r_i
:
in
std_logic
:
=
'0'
;
wrs_rx_cfg_fix_l_i
:
in
std_logic_vector
(
27
downto
0
)
:
=
x"0000000"
;
---------------------------------------------------------------------------
-- Etherbone WB master interface (when g_fabric_iface = "etherbone")
---------------------------------------------------------------------------
...
...
@@ -313,6 +321,10 @@ architecture std_wrapper of wrc_board_svec is
-- External Tx Timestamping I/F
signal
timestamps_out
:
t_txtsu_timestamp
;
-- streamers config
signal
wrs_tx_cfg_in
:
t_tx_streamer_cfg
;
signal
wrs_rx_cfg_in
:
t_rx_streamer_cfg
;
begin
-- architecture struct
-- Map top-level signals to internal records
...
...
@@ -375,6 +387,17 @@ begin -- architecture struct
tstamps_port_id_o
<=
timestamps_out
.
port_id
;
tstamps_frame_id_o
<=
timestamps_out
.
frame_id
;
wrs_tx_cfg_in
.
mac_local
<=
wrs_tx_cfg_mac_l_i
;
wrs_tx_cfg_in
.
mac_target
<=
wrs_tx_cfg_mac_t_i
;
wrs_tx_cfg_in
.
ethertype
<=
wrs_tx_cfg_etype_i
;
wrs_rx_cfg_in
.
mac_local
<=
wrs_rx_cfg_mac_l_i
;
wrs_rx_cfg_in
.
mac_remote
<=
wrs_rx_cfg_mac_r_i
;
wrs_rx_cfg_in
.
ethertype
<=
wrs_rx_cfg_etype_i
;
wrs_rx_cfg_in
.
accept_broadcasts
<=
wrs_rx_cfg_acc_b_i
;
wrs_rx_cfg_in
.
filter_remote
<=
wrs_rx_cfg_flt_r_i
;
wrs_rx_cfg_in
.
fixed_latency
<=
wrs_rx_cfg_fix_l_i
;
-- Instantiate the records-based module
cmp_xwrc_board_svec
:
xwrc_board_svec
generic
map
(
...
...
@@ -445,11 +468,13 @@ begin -- architecture struct
wrs_tx_dreq_o
=>
wrs_tx_dreq_o
,
wrs_tx_last_i
=>
wrs_tx_last_i
,
wrs_tx_flush_i
=>
wrs_tx_flush_i
,
wrs_tx_cfg_i
=>
wrs_tx_cfg_in
,
wrs_rx_first_o
=>
wrs_rx_first_o
,
wrs_rx_last_o
=>
wrs_rx_last_o
,
wrs_rx_data_o
=>
wrs_rx_data_o
,
wrs_rx_valid_o
=>
wrs_rx_valid_o
,
wrs_rx_dreq_i
=>
wrs_rx_dreq_i
,
wrs_rx_cfg_i
=>
wrs_rx_cfg_in
,
wb_eth_master_o
=>
wb_eth_master_out
,
wb_eth_master_i
=>
wb_eth_master_in
,
aux_diag_i
=>
aux_diag_in
,
...
...
board/svec/xwrc_board_svec.vhd
View file @
991af743
...
...
@@ -183,12 +183,13 @@ entity xwrc_board_svec is
wrs_tx_dreq_o
:
out
std_logic
;
wrs_tx_last_i
:
in
std_logic
:
=
'1'
;
wrs_tx_flush_i
:
in
std_logic
:
=
'0'
;
wrs_tx_cfg_i
:
in
t_tx_streamer_cfg
:
=
c_tx_streamer_cfg_default
;
wrs_rx_first_o
:
out
std_logic
;
wrs_rx_last_o
:
out
std_logic
;
wrs_rx_data_o
:
out
std_logic_vector
(
g_rx_streamer_params
.
data_width
-1
downto
0
);
wrs_rx_valid_o
:
out
std_logic
;
wrs_rx_dreq_i
:
in
std_logic
:
=
'0'
;
wrs_rx_cfg_i
:
in
t_rx_streamer_cfg
:
=
c_rx_streamer_cfg_default
;
---------------------------------------------------------------------------
-- Etherbone WB master interface (when g_fabric_iface = "etherbone")
---------------------------------------------------------------------------
...
...
@@ -474,11 +475,13 @@ begin -- architecture struct
wrs_tx_dreq_o
=>
wrs_tx_dreq_o
,
wrs_tx_last_i
=>
wrs_tx_last_i
,
wrs_tx_flush_i
=>
wrs_tx_flush_i
,
wrs_tx_cfg_i
=>
wrs_tx_cfg_i
,
wrs_rx_first_o
=>
wrs_rx_first_o
,
wrs_rx_last_o
=>
wrs_rx_last_o
,
wrs_rx_data_o
=>
wrs_rx_data_o
,
wrs_rx_valid_o
=>
wrs_rx_valid_o
,
wrs_rx_dreq_i
=>
wrs_rx_dreq_i
,
wrs_rx_cfg_i
=>
wrs_rx_cfg_i
,
wb_eth_master_o
=>
wb_eth_master_o
,
wb_eth_master_i
=>
wb_eth_master_i
,
aux_diag_i
=>
aux_diag_i
,
...
...
board/vfchd/wr_vfchd_pkg.vhd
View file @
991af743
...
...
@@ -64,11 +64,13 @@ package wr_vfchd_pkg is
wrs_tx_dreq_o
:
out
std_logic
;
wrs_tx_last_i
:
in
std_logic
:
=
'1'
;
wrs_tx_flush_i
:
in
std_logic
:
=
'0'
;
wrs_tx_cfg_i
:
in
t_tx_streamer_cfg
:
=
c_tx_streamer_cfg_default
;
wrs_rx_first_o
:
out
std_logic
;
wrs_rx_last_o
:
out
std_logic
;
wrs_rx_data_o
:
out
std_logic_vector
(
g_rx_streamer_params
.
data_width
-1
downto
0
);
wrs_rx_valid_o
:
out
std_logic
;
wrs_rx_dreq_i
:
in
std_logic
:
=
'0'
;
wrs_rx_cfg_i
:
in
t_rx_streamer_cfg
:
=
c_rx_streamer_cfg_default
;
wb_eth_master_o
:
out
t_wishbone_master_out
;
wb_eth_master_i
:
in
t_wishbone_master_in
:
=
cc_dummy_master_in
;
aux_diag_i
:
in
t_generic_word_array
(
g_diag_ro_size
-1
downto
0
)
:
=
(
others
=>
(
others
=>
'0'
));
...
...
@@ -175,11 +177,20 @@ package wr_vfchd_pkg is
wrs_tx_dreq_o
:
out
std_logic
;
wrs_tx_last_i
:
in
std_logic
:
=
'1'
;
wrs_tx_flush_i
:
in
std_logic
:
=
'0'
;
wrs_tx_cfg_mac_l_i
:
in
std_logic_vector
(
47
downto
0
)
:
=
x"000000000000"
;
wrs_tx_cfg_mac_t_i
:
in
std_logic_vector
(
47
downto
0
)
:
=
x"ffffffffffff"
;
wrs_tx_cfg_etype_i
:
in
std_logic_vector
(
15
downto
0
)
:
=
x"dbff"
;
wrs_rx_first_o
:
out
std_logic
;
wrs_rx_last_o
:
out
std_logic
;
wrs_rx_data_o
:
out
std_logic_vector
(
g_rx_streamer_params
.
data_width
-1
downto
0
);
wrs_rx_valid_o
:
out
std_logic
;
wrs_rx_dreq_i
:
in
std_logic
:
=
'0'
;
wrs_rx_cfg_mac_l_i
:
in
std_logic_vector
(
47
downto
0
)
:
=
x"000000000000"
;
wrs_rx_cfg_mac_r_i
:
in
std_logic_vector
(
47
downto
0
)
:
=
x"000000000000"
;
wrs_rx_cfg_etype_i
:
in
std_logic_vector
(
15
downto
0
)
:
=
x"dbff"
;
wrs_rx_cfg_acc_b_i
:
in
std_logic
:
=
'1'
;
wrs_rx_cfg_flt_r_i
:
in
std_logic
:
=
'0'
;
wrs_rx_cfg_fix_l_i
:
in
std_logic_vector
(
27
downto
0
)
:
=
x"0000000"
;
wb_eth_adr_o
:
out
std_logic_vector
(
c_wishbone_address_width
-1
downto
0
);
wb_eth_dat_o
:
out
std_logic_vector
(
c_wishbone_data_width
-1
downto
0
);
wb_eth_dat_i
:
in
std_logic_vector
(
c_wishbone_data_width
-1
downto
0
)
:
=
(
others
=>
'0'
);
...
...
board/vfchd/wrc_board_vfchd.vhd
View file @
991af743
...
...
@@ -189,12 +189,20 @@ entity wrc_board_vfchd is
wrs_tx_dreq_o
:
out
std_logic
;
wrs_tx_last_i
:
in
std_logic
:
=
'1'
;
wrs_tx_flush_i
:
in
std_logic
:
=
'0'
;
wrs_tx_cfg_mac_l_i
:
in
std_logic_vector
(
47
downto
0
)
:
=
x"000000000000"
;
wrs_tx_cfg_mac_t_i
:
in
std_logic_vector
(
47
downto
0
)
:
=
x"ffffffffffff"
;
wrs_tx_cfg_etype_i
:
in
std_logic_vector
(
15
downto
0
)
:
=
x"dbff"
;
wrs_rx_first_o
:
out
std_logic
;
wrs_rx_last_o
:
out
std_logic
;
wrs_rx_data_o
:
out
std_logic_vector
(
g_rx_streamer_params
.
data_width
-1
downto
0
);
wrs_rx_valid_o
:
out
std_logic
;
wrs_rx_dreq_i
:
in
std_logic
:
=
'0'
;
wrs_rx_cfg_mac_l_i
:
in
std_logic_vector
(
47
downto
0
)
:
=
x"000000000000"
;
wrs_rx_cfg_mac_r_i
:
in
std_logic_vector
(
47
downto
0
)
:
=
x"000000000000"
;
wrs_rx_cfg_etype_i
:
in
std_logic_vector
(
15
downto
0
)
:
=
x"dbff"
;
wrs_rx_cfg_acc_b_i
:
in
std_logic
:
=
'1'
;
wrs_rx_cfg_flt_r_i
:
in
std_logic
:
=
'0'
;
wrs_rx_cfg_fix_l_i
:
in
std_logic_vector
(
27
downto
0
)
:
=
x"0000000"
;
---------------------------------------------------------------------------
-- Etherbone WB master interface (when g_fabric_iface = "etherbone")
---------------------------------------------------------------------------
...
...
@@ -297,6 +305,10 @@ architecture std_wrapper of wrc_board_vfchd is
-- External Tx Timestamping I/F
signal
timestamps_out
:
t_txtsu_timestamp
;
-- streamers config
signal
wrs_tx_cfg_in
:
t_tx_streamer_cfg
;
signal
wrs_rx_cfg_in
:
t_rx_streamer_cfg
;
begin
-- architecture struct
-- Map top-level signals to internal records
...
...
@@ -359,6 +371,17 @@ begin -- architecture struct
tstamps_port_id_o
<=
timestamps_out
.
port_id
;
tstamps_frame_id_o
<=
timestamps_out
.
frame_id
;
wrs_tx_cfg_in
.
mac_local
<=
wrs_tx_cfg_mac_l_i
;
wrs_tx_cfg_in
.
mac_target
<=
wrs_tx_cfg_mac_t_i
;
wrs_tx_cfg_in
.
ethertype
<=
wrs_tx_cfg_etype_i
;
wrs_rx_cfg_in
.
mac_local
<=
wrs_rx_cfg_mac_l_i
;
wrs_rx_cfg_in
.
mac_remote
<=
wrs_rx_cfg_mac_r_i
;
wrs_rx_cfg_in
.
ethertype
<=
wrs_rx_cfg_etype_i
;
wrs_rx_cfg_in
.
accept_broadcasts
<=
wrs_rx_cfg_acc_b_i
;
wrs_rx_cfg_in
.
filter_remote
<=
wrs_rx_cfg_flt_r_i
;
wrs_rx_cfg_in
.
fixed_latency
<=
wrs_rx_cfg_fix_l_i
;
-- Instantiate the records-based module
cmp_xwrc_board_vfchd
:
xwrc_board_vfchd
generic
map
(
...
...
@@ -413,11 +436,13 @@ begin -- architecture struct
wrs_tx_dreq_o
=>
wrs_tx_dreq_o
,
wrs_tx_last_i
=>
wrs_tx_last_i
,
wrs_tx_flush_i
=>
wrs_tx_flush_i
,
wrs_tx_cfg_i
=>
wrs_tx_cfg_in
,
wrs_rx_first_o
=>
wrs_rx_first_o
,
wrs_rx_last_o
=>
wrs_rx_last_o
,
wrs_rx_data_o
=>
wrs_rx_data_o
,
wrs_rx_valid_o
=>
wrs_rx_valid_o
,
wrs_rx_dreq_i
=>
wrs_rx_dreq_i
,
wrs_rx_cfg_i
=>
wrs_rx_cfg_in
,
wb_eth_master_o
=>
wb_eth_master_out
,
wb_eth_master_i
=>
wb_eth_master_in
,
aux_diag_i
=>
aux_diag_in
,
...
...
board/vfchd/xwrc_board_vfchd.vhd
View file @
991af743
...
...
@@ -161,12 +161,13 @@ entity xwrc_board_vfchd is
wrs_tx_dreq_o
:
out
std_logic
;
wrs_tx_last_i
:
in
std_logic
:
=
'1'
;
wrs_tx_flush_i
:
in
std_logic
:
=
'0'
;
wrs_tx_cfg_i
:
in
t_tx_streamer_cfg
:
=
c_tx_streamer_cfg_default
;
wrs_rx_first_o
:
out
std_logic
;
wrs_rx_last_o
:
out
std_logic
;
wrs_rx_data_o
:
out
std_logic_vector
(
g_rx_streamer_params
.
data_width
-1
downto
0
);
wrs_rx_valid_o
:
out
std_logic
;
wrs_rx_dreq_i
:
in
std_logic
:
=
'0'
;
wrs_rx_cfg_i
:
in
t_rx_streamer_cfg
:
=
c_rx_streamer_cfg_default
;
---------------------------------------------------------------------------
-- Etherbone WB master interface (when g_fabric_iface = "etherbone")
---------------------------------------------------------------------------
...
...
@@ -462,11 +463,13 @@ begin -- architecture struct
wrs_tx_dreq_o
=>
wrs_tx_dreq_o
,
wrs_tx_last_i
=>
wrs_tx_last_i
,
wrs_tx_flush_i
=>
wrs_tx_flush_i
,
wrs_tx_cfg_i
=>
wrs_tx_cfg_i
,
wrs_rx_first_o
=>
wrs_rx_first_o
,
wrs_rx_last_o
=>
wrs_rx_last_o
,
wrs_rx_data_o
=>
wrs_rx_data_o
,
wrs_rx_valid_o
=>
wrs_rx_valid_o
,
wrs_rx_dreq_i
=>
wrs_rx_dreq_i
,
wrs_rx_cfg_i
=>
wrs_rx_cfg_i
,
wb_eth_master_o
=>
wb_eth_master_o
,
wb_eth_master_i
=>
wb_eth_master_i
,
aux_diag_i
=>
aux_diag_i
,
...
...
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