modules/wrc_core: remove dangling phy_rx_k16_i port

9b8256e1 · Dimitris Lampridis · 2deb7654 · 9b8256e1
Commit 9b8256e1 authored Mar 10, 2017 by Dimitris Lampridis
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wr_core.vhd modules/wrc_core/wr_core.vhd +1 -2

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--- a/modules/wrc_core/wr_core.vhd
+++ b/modules/wrc_core/wr_core.vhd
@@ -5,7 +5,7 @@
 -- Author     : Grzegorz Daniluk
 -- Company    : Elproma
 -- Created    : 2011-02-02
-- Last update: 2017-03-07
+-- Last update: 2017-03-10
 -- Platform   : FPGA-generics
 -- Standard   : VHDL
 -------------------------------------------------------------------------------
@@ -153,7 +153,6 @@ entity wr_core is
    phy_rx_data_i     : in std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
    phy_rx_rbclk_i    : in std_logic;
    phy_rx_k_i        : in std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
-    phy_rx_k16_i      : in std_logic := '0';
    phy_rx_enc_err_i  : in std_logic;
    phy_rx_bitslide_i : in std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0);