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White Rabbit core collection
Commits
9c2890c0
Commit
9c2890c0
authored
Aug 04, 2015
by
Grzegorz Daniluk
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Plain Diff
wr_endpoint: keep also 1-bit loopback signal for PHYs that don't accept detailed vector
parent
25b049e4
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Showing
11 changed files
with
72 additions
and
41 deletions
+72
-41
endpoint_pkg.vhd
modules/wr_endpoint/endpoint_pkg.vhd
+4
-2
endpoint_private_pkg.vhd
modules/wr_endpoint/endpoint_private_pkg.vhd
+4
-2
ep_1000basex_pcs.vhd
modules/wr_endpoint/ep_1000basex_pcs.vhd
+6
-2
ep_pcs_tbi_mdio_wb.vhd
modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd
+17
-10
pcs_regs.wb
modules/wr_endpoint/pcs_regs.wb
+16
-10
wr_endpoint.vhd
modules/wr_endpoint/wr_endpoint.vhd
+8
-6
xwr_endpoint.vhd
modules/wr_endpoint/xwr_endpoint.vhd
+3
-1
wr_core.vhd
modules/wrc_core/wr_core.vhd
+3
-1
wrcore_pkg.vhd
modules/wrc_core/wrcore_pkg.vhd
+4
-2
xwr_core.vhd
modules/wrc_core/xwr_core.vhd
+3
-1
endpoint_mdio.v
sim/endpoint_mdio.v
+4
-4
No files found.
modules/wr_endpoint/endpoint_pkg.vhd
View file @
9c2890c0
...
...
@@ -123,7 +123,8 @@ package endpoint_pkg is
pps_csync_p1_i
:
in
std_logic
:
=
'0'
;
pps_valid_i
:
in
std_logic
:
=
'1'
;
phy_rst_o
:
out
std_logic
;
phy_loopen_o
:
out
std_logic_vector
(
2
downto
0
);
phy_loopen_o
:
out
std_logic
;
phy_loopen_vec_o
:
out
std_logic_vector
(
2
downto
0
);
phy_tx_prbs_sel_o
:
out
std_logic_vector
(
2
downto
0
);
phy_sfp_tx_fault_i
:
in
std_logic
;
phy_sfp_los_i
:
in
std_logic
;
...
...
@@ -225,7 +226,8 @@ package endpoint_pkg is
pps_csync_p1_i
:
in
std_logic
;
pps_valid_i
:
in
std_logic
:
=
'1'
;
phy_rst_o
:
out
std_logic
;
phy_loopen_o
:
out
std_logic_vector
(
2
downto
0
);
phy_loopen_o
:
out
std_logic
;
phy_loopen_vec_o
:
out
std_logic_vector
(
2
downto
0
);
phy_tx_prbs_sel_o
:
out
std_logic_vector
(
2
downto
0
);
phy_sfp_tx_fault_i
:
in
std_logic
;
phy_sfp_los_i
:
in
std_logic
;
...
...
modules/wr_endpoint/endpoint_private_pkg.vhd
View file @
9c2890c0
...
...
@@ -136,7 +136,8 @@ package endpoint_private_pkg is
link_ctr_i
:
in
std_logic
:
=
'1'
;
serdes_rst_o
:
out
std_logic
;
serdes_syncen_o
:
out
std_logic
;
serdes_loopen_o
:
out
std_logic_vector
(
2
downto
0
);
serdes_loopen_o
:
out
std_logic
;
serdes_loopen_vec_o
:
out
std_logic_vector
(
2
downto
0
);
serdes_tx_prbs_sel_o
:
out
std_logic_vector
(
2
downto
0
);
serdes_sfp_tx_fault_i
:
in
std_logic
;
serdes_sfp_los_i
:
in
std_logic
;
...
...
@@ -322,7 +323,8 @@ package endpoint_private_pkg is
mdio_mcr_pdown_o
:
out
std_logic
;
mdio_mcr_anenable_o
:
out
std_logic
;
mdio_mcr_reset_o
:
out
std_logic
;
mdio_mcr_loopback_o
:
out
std_logic_vector
(
2
downto
0
);
mdio_mcr_loopback_o
:
out
std_logic
;
mdio_mcr_lpbck_vec_o
:
out
std_logic_vector
(
2
downto
0
);
mdio_mcr_sfp_tx_fault_i
:
in
std_logic
;
mdio_mcr_sfp_loss_i
:
in
std_logic
;
mdio_mcr_sfp_tx_disable_o
:
out
std_logic
;
...
...
modules/wr_endpoint/ep_1000basex_pcs.vhd
View file @
9c2890c0
...
...
@@ -125,8 +125,11 @@ entity ep_1000basex_pcs is
-- 1: serdes comma alignent is enabled.
serdes_syncen_o
:
out
std_logic
;
-- 000: loopback "normal operation" (see Serdes User Guide)
serdes_loopen_o
:
out
std_logic_vector
(
2
downto
0
);
-- 1: serdes near-end PMA loopback is enabled.
serdes_loopen_o
:
out
std_logic
;
-- 000: loopback vector "normal operation" (see Serdes User Guide)
serdes_loopen_vec_o
:
out
std_logic_vector
(
2
downto
0
);
-- 000: "normal operation" (see Serdes User Guide)
serdes_tx_prbs_sel_o
:
out
std_logic_vector
(
2
downto
0
);
...
...
@@ -436,6 +439,7 @@ begin -- rtl
mdio_mcr_anenable_o
=>
mdio_mcr_anenable
,
mdio_mcr_reset_o
=>
mdio_mcr_reset
,
mdio_mcr_loopback_o
=>
serdes_loopen_o
,
mdio_mcr_lpbck_vec_o
=>
serdes_loopen_vec_o
,
mdio_mcr_sfp_tx_fault_i
=>
serdes_sfp_tx_fault_i
,
mdio_mcr_sfp_loss_i
=>
serdes_sfp_los_i
,
mdio_mcr_sfp_tx_disable_o
=>
serdes_sfp_tx_disable_o
,
...
...
modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd
View file @
9c2890c0
...
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ep_pcs_tbi_mdio_wb.vhd
-- Author : auto-generated by wbgen2 from pcs_regs.wb
-- Created :
01/15/15 14:37:10
-- Created :
Tue Aug 4 10:01:08 2015
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pcs_regs.wb
...
...
@@ -37,10 +37,12 @@ entity ep_pcs_tbi_mdio_wb is
mdio_mcr_pdown_o
:
out
std_logic
;
-- Port for BIT field: 'Auto-Negotiation Enable' in reg: 'MDIO Control Register'
mdio_mcr_anenable_o
:
out
std_logic
;
-- Port for BIT field: 'Loopback' in reg: 'MDIO Control Register'
mdio_mcr_loopback_o
:
out
std_logic
;
-- Port for MONOSTABLE field: 'Reset' in reg: 'MDIO Control Register'
mdio_mcr_reset_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Loopback' in reg: 'MDIO Control Register'
mdio_mcr_l
oopback_o
:
out
std_logic_vector
(
2
downto
0
);
-- Port for std_logic_vector field: 'Loopback
- detailed
' in reg: 'MDIO Control Register'
mdio_mcr_l
pbck_vec_o
:
out
std_logic_vector
(
2
downto
0
);
-- Port for BIT field: 'SFP TX Fault Status' in reg: 'MDIO Control Register'
mdio_mcr_sfp_tx_fault_i
:
in
std_logic
;
-- Port for BIT field: 'SFP LOS' in reg: 'MDIO Control Register'
...
...
@@ -90,9 +92,10 @@ signal mdio_mcr_anrestart_dly0 : std_logic ;
signal
mdio_mcr_anrestart_int
:
std_logic
;
signal
mdio_mcr_pdown_int
:
std_logic
;
signal
mdio_mcr_anenable_int
:
std_logic
;
signal
mdio_mcr_loopback_int
:
std_logic
;
signal
mdio_mcr_reset_dly0
:
std_logic
;
signal
mdio_mcr_reset_int
:
std_logic
;
signal
mdio_mcr_l
oopback_int
:
std_logic_vector
(
2
downto
0
);
signal
mdio_mcr_l
pbck_vec_int
:
std_logic_vector
(
2
downto
0
);
signal
mdio_mcr_sfp_tx_disable_int
:
std_logic
;
signal
mdio_mcr_tx_prbs_sel_int
:
std_logic_vector
(
2
downto
0
);
signal
mdio_advertise_pause_int
:
std_logic_vector
(
1
downto
0
);
...
...
@@ -145,8 +148,9 @@ begin
mdio_mcr_anrestart_int
<=
'0'
;
mdio_mcr_pdown_int
<=
'0'
;
mdio_mcr_anenable_int
<=
'0'
;
mdio_mcr_loopback_int
<=
'0'
;
mdio_mcr_reset_int
<=
'0'
;
mdio_mcr_l
oopback
_int
<=
"000"
;
mdio_mcr_l
pbck_vec
_int
<=
"000"
;
mdio_mcr_sfp_tx_disable_int
<=
'0'
;
mdio_mcr_tx_prbs_sel_int
<=
"000"
;
lstat_read_notify_o
<=
'0'
;
...
...
@@ -187,8 +191,9 @@ begin
mdio_mcr_anrestart_int
<=
wrdata_reg
(
9
);
mdio_mcr_pdown_int
<=
wrdata_reg
(
11
);
mdio_mcr_anenable_int
<=
wrdata_reg
(
12
);
mdio_mcr_loopback_int
<=
wrdata_reg
(
14
);
mdio_mcr_reset_int
<=
wrdata_reg
(
15
);
mdio_mcr_l
oopback
_int
<=
wrdata_reg
(
18
downto
16
);
mdio_mcr_l
pbck_vec
_int
<=
wrdata_reg
(
18
downto
16
);
mdio_mcr_sfp_tx_disable_int
<=
wrdata_reg
(
21
);
mdio_mcr_tx_prbs_sel_int
<=
wrdata_reg
(
24
downto
22
);
end
if
;
...
...
@@ -202,9 +207,9 @@ begin
rddata_reg
(
11
)
<=
mdio_mcr_pdown_int
;
rddata_reg
(
12
)
<=
mdio_mcr_anenable_int
;
rddata_reg
(
13
)
<=
'0'
;
rddata_reg
(
14
)
<=
'0'
;
rddata_reg
(
14
)
<=
mdio_mcr_loopback_int
;
rddata_reg
(
15
)
<=
'0'
;
rddata_reg
(
18
downto
16
)
<=
mdio_mcr_l
oopback
_int
;
rddata_reg
(
18
downto
16
)
<=
mdio_mcr_l
pbck_vec
_int
;
rddata_reg
(
19
)
<=
mdio_mcr_sfp_tx_fault_i
;
rddata_reg
(
20
)
<=
mdio_mcr_sfp_loss_i
;
rddata_reg
(
21
)
<=
mdio_mcr_sfp_tx_disable_int
;
...
...
@@ -485,6 +490,8 @@ begin
mdio_mcr_pdown_o
<=
mdio_mcr_pdown_int
;
-- Auto-Negotiation Enable
mdio_mcr_anenable_o
<=
mdio_mcr_anenable_int
;
-- Loopback
mdio_mcr_loopback_o
<=
mdio_mcr_loopback_int
;
-- Reset
process
(
clk_sys_i
,
rst_n_i
)
begin
...
...
@@ -498,8 +505,8 @@ begin
end
process
;
-- Loopback
mdio_mcr_l
oopback_o
<=
mdio_mcr_loopback
_int
;
-- Loopback
- detailed
mdio_mcr_l
pbck_vec_o
<=
mdio_mcr_lpbck_vec
_int
;
-- SFP TX Fault Status
-- SFP LOS
-- SFP TX Disable
...
...
modules/wr_endpoint/pcs_regs.wb
View file @
9c2890c0
...
...
@@ -152,12 +152,16 @@ peripheral {
};
field {
name = "Reserved";
description = "Always return 0s, writes ignored.";
prefix = "RESV";
type = CONSTANT;
size = 1;
value = 0;
name = "Loopback";
description = "1 enable loopback mode \
0 = disable loopback mode \
With the TBI version, loopback bit is connected to PHY loopback enable pin. When set to 1, indicates to the external PHY to enter loopback mode";
prefix = "loopback";
align = 14;
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
...
...
@@ -172,12 +176,14 @@ peripheral {
};
field {
name = "Loopback";
description = "100 = far end loopback mode \
name = "Loopback - detailed";
description = "Loopback vector for Xilinx PHYs: \
100 = far end loopback mode \
000 = normal mode \
See also Transceiver documentation (for example Xilinx UG476 Table 2-37 and Figure 2-23";
See also Transceiver documentation (for example Xilinx UG476 Table 2-37 and Figure 2-23 \
LOOPBACK bit set to 1 may overwritte LPBCK_VEC depending on the PHY wrapper implementation";
prefix = "l
oopback
";
prefix = "l
pbck_vec
";
align = 16;
size = 3;
value = 0;
...
...
modules/wr_endpoint/wr_endpoint.vhd
View file @
9c2890c0
...
...
@@ -106,7 +106,8 @@ entity wr_endpoint is
-------------------------------------------------------------------------------
phy_rst_o
:
out
std_logic
;
phy_loopen_o
:
out
std_logic_vector
(
2
downto
0
);
phy_loopen_o
:
out
std_logic
;
phy_loopen_vec_o
:
out
std_logic_vector
(
2
downto
0
);
phy_tx_prbs_sel_o
:
out
std_logic_vector
(
2
downto
0
);
phy_sfp_tx_fault_i
:
in
std_logic
;
phy_sfp_los_i
:
in
std_logic
;
...
...
@@ -517,15 +518,16 @@ begin
link_ok_o
=>
link_ok
,
link_ctr_i
=>
ep_ctrl
,
serdes_rst_o
=>
phy_rst_o
,
serdes_loopen_o
=>
phy_loopen_o
,
serdes_rst_o
=>
phy_rst_o
,
serdes_loopen_o
=>
phy_loopen_o
,
serdes_loopen_vec_o
=>
phy_loopen_vec_o
,
serdes_tx_prbs_sel_o
=>
phy_tx_prbs_sel_o
,
serdes_sfp_tx_fault_i
=>
phy_sfp_tx_fault_i
,
serdes_sfp_los_i
=>
phy_sfp_los_i
,
serdes_sfp_tx_disable_o
=>
phy_sfp_tx_disable_o
,
serdes_enable_o
=>
phy_enable_o
,
serdes_syncen_o
=>
phy_syncen_o
,
serdes_rdy_i
=>
phy_rdy_i
,
serdes_enable_o
=>
phy_enable_o
,
serdes_syncen_o
=>
phy_syncen_o
,
serdes_rdy_i
=>
phy_rdy_i
,
serdes_tx_clk_i
=>
phy_ref_clk_i
,
serdes_tx_data_o
=>
phy_tx_data_o
,
...
...
modules/wr_endpoint/xwr_endpoint.vhd
View file @
9c2890c0
...
...
@@ -95,7 +95,8 @@ entity xwr_endpoint is
-------------------------------------------------------------------------------
phy_rst_o
:
out
std_logic
;
phy_loopen_o
:
out
std_logic_vector
(
2
downto
0
);
phy_loopen_o
:
out
std_logic
;
phy_loopen_vec_o
:
out
std_logic_vector
(
2
downto
0
);
phy_tx_prbs_sel_o
:
out
std_logic_vector
(
2
downto
0
);
phy_sfp_tx_fault_i
:
in
std_logic
;
phy_sfp_los_i
:
in
std_logic
;
...
...
@@ -295,6 +296,7 @@ begin
pps_valid_i
=>
pps_valid_i
,
phy_rst_o
=>
phy_rst_o
,
phy_loopen_o
=>
phy_loopen_o
,
phy_loopen_vec_o
=>
phy_loopen_vec_o
,
phy_tx_prbs_sel_o
=>
phy_tx_prbs_sel_o
,
phy_sfp_tx_fault_i
=>
phy_sfp_tx_fault_i
,
phy_sfp_los_i
=>
phy_sfp_los_i
,
...
...
modules/wrc_core/wr_core.vhd
View file @
9c2890c0
...
...
@@ -153,7 +153,8 @@ entity wr_core is
phy_rst_o
:
out
std_logic
;
phy_rdy_i
:
in
std_logic
:
=
'1'
;
phy_loopen_o
:
out
std_logic_vector
(
2
downto
0
);
phy_loopen_o
:
out
std_logic
;
phy_loopen_vec_o
:
out
std_logic_vector
(
2
downto
0
);
phy_tx_prbs_sel_o
:
out
std_logic_vector
(
2
downto
0
);
phy_sfp_tx_fault_i
:
in
std_logic
:
=
'0'
;
phy_sfp_los_i
:
in
std_logic
:
=
'0'
;
...
...
@@ -656,6 +657,7 @@ begin
phy_rst_o
=>
phy_rst_o
,
phy_rdy_i
=>
phy_rdy_i
,
phy_loopen_o
=>
phy_loopen_o
,
phy_loopen_vec_o
=>
phy_loopen_vec_o
,
phy_tx_prbs_sel_o
=>
phy_tx_prbs_sel_o
,
phy_sfp_tx_fault_i
=>
phy_sfp_tx_fault_i
,
phy_sfp_los_i
=>
phy_sfp_los_i
,
...
...
modules/wrc_core/wrcore_pkg.vhd
View file @
9c2890c0
...
...
@@ -342,7 +342,8 @@ package wrcore_pkg is
phy_rx_bitslide_i
:
in
std_logic_vector
(
f_pcs_bts_width
(
g_pcs_16bit
)
-1
downto
0
)
:
=
(
others
=>
'0'
);
phy_rst_o
:
out
std_logic
;
phy_rdy_i
:
in
std_logic
:
=
'1'
;
phy_loopen_o
:
out
std_logic_vector
(
2
downto
0
);
phy_loopen_o
:
out
std_logic
;
phy_loopen_vec_o
:
out
std_logic_vector
(
2
downto
0
);
phy_tx_prbs_sel_o
:
out
std_logic_vector
(
2
downto
0
);
phy_sfp_tx_fault_i
:
in
std_logic
:
=
'0'
;
phy_sfp_los_i
:
in
std_logic
:
=
'0'
;
...
...
@@ -480,7 +481,8 @@ package wrcore_pkg is
phy_rst_o
:
out
std_logic
;
phy_rdy_i
:
in
std_logic
:
=
'1'
;
phy_loopen_o
:
out
std_logic_vector
(
2
downto
0
);
phy_loopen_o
:
out
std_logic
;
phy_loopen_vec_o
:
out
std_logic_vector
(
2
downto
0
);
phy_tx_prbs_sel_o
:
out
std_logic_vector
(
2
downto
0
);
phy_sfp_tx_fault_i
:
in
std_logic
:
=
'0'
;
phy_sfp_los_i
:
in
std_logic
:
=
'0'
;
...
...
modules/wrc_core/xwr_core.vhd
View file @
9c2890c0
...
...
@@ -137,7 +137,8 @@ entity xwr_core is
phy_rst_o
:
out
std_logic
;
phy_rdy_i
:
in
std_logic
:
=
'1'
;
phy_loopen_o
:
out
std_logic_vector
(
2
downto
0
);
phy_loopen_o
:
out
std_logic
;
phy_loopen_vec_o
:
out
std_logic_vector
(
2
downto
0
);
phy_tx_prbs_sel_o
:
out
std_logic_vector
(
2
downto
0
);
phy_sfp_tx_fault_i
:
in
std_logic
:
=
'0'
;
phy_sfp_los_i
:
in
std_logic
:
=
'0'
;
...
...
@@ -278,6 +279,7 @@ begin
phy_rst_o
=>
phy_rst_o
,
phy_rdy_i
=>
phy_rdy_i
,
phy_loopen_o
=>
phy_loopen_o
,
phy_loopen_vec_o
=>
phy_loopen_vec_o
,
phy_tx_prbs_sel_o
=>
phy_tx_prbs_sel_o
,
phy_sfp_tx_fault_i
=>
phy_sfp_tx_fault_i
,
phy_sfp_los_i
=>
phy_sfp_los_i
,
...
...
sim/endpoint_mdio.v
View file @
9c2890c0
...
...
@@ -19,12 +19,12 @@
`define
MDIO_MCR_ANENABLE 32
'
h00001000
`define
MDIO_MCR_SPEED100_OFFSET 13
`define
MDIO_MCR_SPEED100 32
'
h00002000
`define
MDIO_MCR_
RESV
_OFFSET 14
`define
MDIO_MCR_
RESV
32
'
h00004000
`define
MDIO_MCR_
LOOPBACK
_OFFSET 14
`define
MDIO_MCR_
LOOPBACK
32
'
h00004000
`define
MDIO_MCR_RESET_OFFSET 15
`define
MDIO_MCR_RESET 32
'
h00008000
`define
MDIO_MCR_L
OOPBACK
_OFFSET 16
`define
MDIO_MCR_L
OOPBACK
32
'
h00070000
`define
MDIO_MCR_L
PBCK_VEC
_OFFSET 16
`define
MDIO_MCR_L
PBCK_VEC
32
'
h00070000
`define
MDIO_MCR_SFP_TX_FAULT_OFFSET 19
`define
MDIO_MCR_SFP_TX_FAULT 32
'
h00080000
`define
MDIO_MCR_SFP_LOSS_OFFSET 20
...
...
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