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White Rabbit core collection
Commit 9d8b618f authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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wr_core: updated wr_softpll and wr_pps_gen

parent f1530b6b
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Showing with 312 additions and 289 deletions
modules/wrc_core/Manifest.py
View file @ 9d8b618f
......@@ -2,7 +2,8 @@ files = [ "wr_core.vhd",
"wrc_dpram.vhd",
"wrcore_pkg.vhd",
"wrc_periph.vhd",
"wb_reset.vhd" ];
"wb_reset.vhd",
"wbp_mux.vhd" ];
modules = {"local" : "wb_conmax"};
modules/wrc_core/wr_core.vhd
View file @ 9d8b618f
......@@ -6,7 +6,7 @@
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-02-02
-- Last update: 2011-10-25
-- Last update: 2011-10-27
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -60,7 +60,7 @@ entity wr_core is
clk_ref_i : in std_logic;
-- Aux clock (i.e. the FMC clock)
clk_aux_i: in std_logic;
clk_aux_i : in std_logic;
rst_n_i : in std_logic;
......@@ -123,6 +123,51 @@ entity wr_core is
wb_stb_i : in std_logic;
wb_ack_o : out std_logic;
-------------------------------------------------------------------------------
-- External Fabric I/F
-------------------------------------------------------------------------------
ext_snk_adr_i : in std_logic_vector(1 downto 0) := "00";
ext_snk_dat_i : in std_logic_vector(15 downto 0) := x"0000";
ext_snk_sel_i : in std_logic_vector(1 downto 0) := "00";
ext_snk_cyc_i : in std_logic := '0';
ext_snk_we_i : in std_logic := '0';
ext_snk_stb_i : in std_logic := '0';
ext_snk_ack_o : out std_logic;
ext_snk_err_o : out std_logic;
ext_snk_stall_o : out std_logic;
ext_src_adr_o : out std_logic_vector(1 downto 0);
ext_src_dat_o : out std_logic_vector(15 downto 0);
ext_src_sel_o : out std_logic_vector(1 downto 0);
ext_src_cyc_o : out std_logic;
ext_src_stb_o : out std_logic;
ext_src_we_o : out std_logic;
ext_src_ack_i : in std_logic := '1';
ext_src_err_i : in std_logic := '0';
ext_src_stall_i : in std_logic := '0';
-------------------------------------------------------------------------------
-- Timecode/Servo Control
-------------------------------------------------------------------------------
-- DAC Control
tm_dac_value_o: out std_logic_vector(23 downto 0);
tm_dac_wr_o: out std_logic;
-- Aux clock lock enable
tm_clk_aux_lock_en_i: in std_logic;
-- Aux clock locked flag
tm_clk_aux_locked_o: out std_logic;
-- Timecode output
tm_time_valid_o: out std_logic;
tm_utc_o: out std_logic_vector(31 downto 0);
tm_cycles_o: out std_logic_vector(27 downto 0);
--DEBUG
genrest_n : out std_logic;
......@@ -155,23 +200,6 @@ architecture struct of wr_core is
-----------------------------------------------------------------------------
--Endpoint
-----------------------------------------------------------------------------
signal s_ep_rx_data_o : std_logic_vector(15 downto 0);
signal s_ep_rx_ctrl_o : std_logic_vector(4 - 1 downto 0);
signal s_ep_rx_bytesel_o : std_logic;
signal s_ep_rx_sof_p1_o : std_logic;
signal s_ep_rx_eof_p1_o : std_logic;
signal s_ep_rx_dreq_i : std_logic;
signal s_ep_rx_valid_o : std_logic;
signal s_ep_rx_rerror_p1_o : std_logic;
signal s_ep_tx_data_i : std_logic_vector(15 downto 0);
signal s_ep_tx_ctrl_i : std_logic_vector(4 - 1 downto 0);
signal s_ep_tx_bytesel_i : std_logic;
signal s_ep_tx_sof_p1_i : std_logic;
signal s_ep_tx_eof_p1_i : std_logic;
signal s_ep_tx_dreq_o : std_logic;
signal s_ep_tx_valid_i : std_logic;
signal s_ep_tx_terror_p1_o : std_logic;
signal txtsu_port_id_o : std_logic_vector(4 downto 0);
signal txtsu_frame_id_o : std_logic_vector(16 -1 downto 0);
......@@ -182,20 +210,6 @@ architecture struct of wr_core is
signal ep_wb_i : t_wb_i;
signal ep_wb_o : t_wb_o;
-----------------------------------------------------------------------------
--GTP
-----------------------------------------------------------------------------
signal s_gtp_tx_data_i : std_logic_vector(7 downto 0);
signal s_gtp_tx_k_i : std_logic;
signal s_gtp_tx_disparity_o : std_logic;
signal s_gtp_tx_enc_err_o : std_logic;
signal s_gtp_rx_data_o : std_logic_vector(7 downto 0);
signal s_gtp_rx_rbclk_o : std_logic;
signal s_gtp_rx_k_o : std_logic;
signal s_gtp_rx_enc_err_o : std_logic;
signal s_gtp_rx_bitslide_o : std_logic_vector(3 downto 0);
signal s_gtp_rst_i : std_logic;
signal s_gtp_loopen_i : std_logic;
constant c_mnic_memsize_log2 : integer := f_log2_size(g_dpram_size);
......@@ -273,14 +287,6 @@ architecture struct of wr_core is
-- For SPEC --
--===========================--
signal rst_wb_addr_o : std_logic_vector(17 downto 0);
signal rst_wb_data_i : std_logic_vector(31 downto 0);
signal rst_wb_data_o : std_logic_vector(31 downto 0);
signal rst_wb_sel_o : std_logic_vector(3 downto 0);
signal rst_wb_we_o : std_logic;
signal rst_wb_cyc_o : std_logic;
signal rst_wb_stb_o : std_logic;
signal rst_wb_ack_i : std_logic;
signal genrst_n : std_logic;
signal rst_wb_i : t_wb_i;
signal rst_wb_o : t_wb_o;
......@@ -312,8 +318,59 @@ architecture struct of wr_core is
signal ep_snk_out : t_wrf_sink_out;
signal ep_snk_in : t_wrf_sink_in;
signal minic_src_out : t_wrf_source_out;
signal minic_src_in : t_wrf_source_in;
signal minic_snk_out : t_wrf_sink_out;
signal minic_snk_in : t_wrf_sink_in;
signal ext_src_out : t_wrf_source_out;
signal ext_src_in : t_wrf_source_in;
signal ext_snk_out : t_wrf_sink_out;
signal ext_snk_in : t_wrf_sink_in;
signal dummy : std_logic_vector(31 downto 0);
component chipscope_ila
port (
CONTROL : inout std_logic_vector(35 downto 0);
CLK : in std_logic;
TRIG0 : in std_logic_vector(31 downto 0);
TRIG1 : in std_logic_vector(31 downto 0);
TRIG2 : in std_logic_vector(31 downto 0);
TRIG3 : in std_logic_vector(31 downto 0));
end component;
component chipscope_icon
port (
CONTROL0 : inout std_logic_vector (35 downto 0));
end component;
component xwbp_mux
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
ep_src_o : out t_wrf_source_out;
ep_src_i : in t_wrf_source_in;
ep_snk_o : out t_wrf_sink_out;
ep_snk_i : in t_wrf_sink_in;
ptp_src_o : out t_wrf_source_out;
ptp_src_i : in t_wrf_source_in;
ptp_snk_o : out t_wrf_sink_out;
ptp_snk_i : in t_wrf_sink_in;
ext_src_o : out t_wrf_source_out;
ext_src_i : in t_wrf_source_in;
ext_snk_o : out t_wrf_sink_out;
ext_snk_i : in t_wrf_sink_in;
class_core_i : in std_logic_vector(7 downto 0));
end component;
signal CONTROL : std_logic_vector(35 downto 0);
signal CLK : std_logic;
signal TRIG0 : std_logic_vector(31 downto 0);
signal TRIG1 : std_logic_vector(31 downto 0);
signal TRIG2 : std_logic_vector(31 downto 0);
signal TRIG3 : std_logic_vector(31 downto 0);
begin
s_rst_n <= genrst_n and rst_n_i;
......@@ -322,16 +379,16 @@ begin
--PPS generator
-----------------------------------------------------------------------------
PPS_GEN : wrsw_pps_gen
PPS_GEN : wr_pps_gen
port map(
clk_ref_i => clk_ref_i,
clk_sys_i => clk_sys_i,
rst_n_i => s_rst_n,
wb_addr_i => ppsg_wb_i.addr(3 downto 0),
wb_data_i => ppsg_wb_i.data,
wb_data_o => ppsg_wb_o.data,
wb_adr_i => ppsg_wb_i.addr(4 downto 0),
wb_dat_i => ppsg_wb_i.data,
wb_dat_o => ppsg_wb_o.data,
wb_cyc_i => ppsg_wb_i.cyc,
wb_sel_i => ppsg_wb_i.sel,
wb_stb_i => ppsg_wb_i.stb,
......@@ -359,12 +416,19 @@ begin
dac_hpll_data_o => dac_hpll_data_o,
dac_hpll_load_o => dac_hpll_load_p1_o,
dac_dmpll_data_o => dac_dpll_data_o,
dac_dmpll_load_o => dac_dpll_load_p1_o,
wb_addr_i => dpll_wb_i.addr(3 downto 0),
wb_data_i => dpll_wb_i.data,
wb_data_o => dpll_wb_o.data,
dac_aux_data_o => tm_dac_value_o,
dac_aux_load_o => tm_dac_wr_o,
clk_aux_lock_en_i => tm_clk_aux_lock_en_i,
clk_aux_locked_o => tm_clk_aux_locked_o,
wb_adr_i => dpll_wb_i.addr(6 downto 0),
wb_dat_i => dpll_wb_i.data,
wb_dat_o => dpll_wb_o.data,
wb_cyc_i => dpll_wb_i.cyc,
wb_sel_i => dpll_wb_i.sel,
wb_stb_i => dpll_wb_i.stb,
......@@ -402,7 +466,7 @@ begin
phy_tx_data_o(7 downto 0) => phy_tx_data_o,
phy_tx_data_o(15 downto 8) => dummy(7 downto 0),
phy_tx_k_o(0) => phy_tx_k_o,
phy_tx_k_o(1) =>dummy(8),
phy_tx_k_o(1) => dummy(8),
phy_tx_disparity_i => phy_tx_disparity_i,
phy_tx_enc_err_i => phy_tx_enc_err_i,
phy_rx_data_i(7 downto 0) => phy_rx_data_i,
......@@ -451,10 +515,10 @@ begin
mem_data_i => s_mnic_mem_data_i,
mem_wr_o => s_mnic_mem_wr_o,
src_o => ep_snk_in,
src_i => ep_snk_out,
snk_o => ep_src_in,
snk_i => ep_src_out,
src_o => minic_src_out,
src_i => minic_src_in,
snk_o => minic_snk_out,
snk_i => minic_snk_in,
txtsu_port_id_i => txtsu_port_id_o,
txtsu_frame_id_i => txtsu_frame_id_o,
......@@ -667,4 +731,89 @@ begin
lm32_jwb_i <= cnx_slave_o(7);
chipscope_ila_1 : chipscope_ila
port map (
CONTROL => CONTROL,
CLK => clk_sys_i,
TRIG0 => TRIG0,
TRIG1 => TRIG1,
TRIG2 => TRIG2,
TRIG3 => TRIG3);
chipscope_icon_1 : chipscope_icon
port map (
CONTROL0 => CONTROL);
TRIG0(15 downto 0) <= ep_src_out.dat;
trig0(17 downto 16) <= ep_src_out.adr;
trig0(19 downto 18) <= ep_src_out.sel;
trig0(20) <= ep_src_out.cyc;
trig0(21) <= ep_src_out.stb;
trig0(22) <= ep_src_out.we;
trig0(23) <= ep_src_in.ack;
trig0(24) <= ep_src_in.stall;
trig0(26) <= ep_src_in.err;
TRIG1(15 downto 0) <= minic_snk_in.dat;
trig1(17 downto 16) <= minic_snk_in.adr;
trig1(19 downto 18) <= minic_snk_in.sel;
trig1(20) <= minic_snk_in.cyc;
trig1(21) <= minic_snk_in.stb;
trig1(22) <= minic_snk_in.we;
trig1(23) <= minic_snk_out.ack;
trig1(24) <= minic_snk_out.stall;
trig1(26) <= minic_snk_out.err;
TRIG2(15 downto 0) <= ext_snk_in.dat;
trig2(17 downto 16) <= ext_snk_in.adr;
trig2(19 downto 18) <= ext_snk_in.sel;
trig2(20) <= ext_snk_in.cyc;
trig2(21) <= ext_snk_in.stb;
trig2(22) <= ext_snk_in.we;
trig2(23) <= ext_snk_out.ack;
trig2(24) <= ext_snk_out.stall;
trig2(26) <= ext_snk_out.err;
U_WBP_Mux : xwbp_mux
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
ep_src_o => ep_snk_in,
ep_src_i => ep_snk_out,
ep_snk_o => ep_src_in,
ep_snk_i => ep_src_out,
ptp_src_o => minic_snk_in,
ptp_src_i => minic_snk_out,
ptp_snk_o => minic_src_in,
ptp_snk_i => minic_src_out,
ext_src_o => ext_src_out,
ext_src_i => ext_src_in,
ext_snk_o => ext_snk_out,
ext_snk_i => ext_snk_in,
class_core_i => "00001111");
ext_src_adr_o <= ext_src_out.adr;
ext_src_dat_o <= ext_src_out.dat;
ext_src_stb_o <= ext_src_out.stb;
ext_src_cyc_o <= ext_src_out.cyc;
ext_src_sel_o <= ext_src_out.sel;
ext_src_we_o <= '1';
ext_src_in.ack <= ext_src_ack_i;
ext_src_in.stall <= ext_src_stall_i;
ext_src_in.err <= ext_src_err_i;
ext_snk_in.adr <= ext_snk_adr_i;
ext_snk_in.dat <= ext_snk_dat_i;
ext_snk_in.stb <= ext_snk_stb_i;
ext_snk_in.cyc <= ext_snk_cyc_i;
ext_snk_in.sel <= ext_snk_sel_i;
ext_snk_in.we <= ext_snk_we_i;
ext_snk_ack_o <= ext_snk_out.ack;
ext_snk_err_o <= ext_snk_out.err;
ext_snk_stall_o <= ext_snk_out.stall;
end struct;
modules/wrc_core/wrcore_pkg.vhd
View file @ 9d8b618f
......@@ -21,168 +21,7 @@ package wrcore_pkg is
wb_slaves_i : in t_conmax_slaves_i;
wb_slaves_o : out t_conmax_slaves_o);
end component;
-----------------------------------------------------------------------------
--PPS generator
-----------------------------------------------------------------------------
component wrsw_pps_gen
port (
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_addr_i : in std_logic_vector(3 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
pps_in_i : in std_logic;
pps_csync_o : out std_logic;
pps_out_o : out std_logic);
end component;
-----------------------------------------------------------------------------
--WR Endpoint
-----------------------------------------------------------------------------
component wrsw_endpoint is
generic (
g_simulation : integer;
g_phy_mode : string := "TBI";
g_rx_buffer_size_log2 : integer := 12);
port (
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
clk_dmtd_i : in std_logic;
rst_n_i : in std_logic;
pps_csync_p1_i : in std_logic;
--TBI
tbi_td_o : out std_logic_vector(9 downto 0);
tbi_enable_o : out std_logic;
tbi_syncen_o : out std_logic;
tbi_loopen_o : out std_logic;
tbi_prbsen_o : out std_logic;
tbi_rbclk_i : in std_logic;
tbi_rd_i : in std_logic_vector(9 downto 0);
tbi_sync_pass_i : in std_logic;
--GTP
gtp_tx_clk_i : in std_logic;
gtp_tx_data_o : out std_logic_vector(7 downto 0);
gtp_tx_k_o : out std_logic;
gtp_tx_disparity_i : in std_logic;
gtp_tx_enc_err_i : in std_logic;
gtp_rx_data_i : in std_logic_vector(7 downto 0);
gtp_rx_clk_i : in std_logic;
gtp_rx_k_i : in std_logic;
gtp_rx_enc_err_i : in std_logic;
gtp_rx_bitslide_i : in std_logic_vector(3 downto 0);
gtp_rst_o : out std_logic;
gtp_loopen_o : out std_logic;
--WRF Source
rx_data_o : out std_logic_vector(15 downto 0);
rx_ctrl_o : out std_logic_vector(4 - 1 downto 0);
rx_bytesel_o : out std_logic;
rx_sof_p1_o : out std_logic;
rx_eof_p1_o : out std_logic;
rx_dreq_i : in std_logic;
rx_valid_o : out std_logic;
rx_rabort_p1_i : in std_logic;
rx_idle_o : out std_logic;
rx_rerror_p1_o : out std_logic;
--WRF Sink
tx_data_i : in std_logic_vector(15 downto 0);
tx_ctrl_i : in std_logic_vector(4 -1 downto 0);
tx_bytesel_i : in std_logic;
tx_sof_p1_i : in std_logic;
tx_eof_p1_i : in std_logic;
tx_dreq_o : out std_logic;
tx_valid_i : in std_logic;
tx_rerror_p1_i : in std_logic;
tx_tabort_p1_i : in std_logic;
tx_terror_p1_o : out std_logic;
--TXTSU
txtsu_port_id_o : out std_logic_vector(4 downto 0);
txtsu_frame_id_o : out std_logic_vector(16 -1 downto 0);
txtsu_tsval_o : out std_logic_vector(28 + 4 - 1 downto 0);
txtsu_valid_o : out std_logic;
txtsu_ack_i : in std_logic;
--RTU
rtu_full_i : in std_logic;
rtu_almost_full_i : in std_logic;
rtu_rq_strobe_p1_o : out std_logic;
rtu_rq_smac_o : out std_logic_vector(48 - 1 downto 0);
rtu_rq_dmac_o : out std_logic_vector(48 - 1 downto 0);
rtu_rq_vid_o : out std_logic_vector(12 - 1 downto 0);
rtu_rq_has_vid_o : out std_logic;
rtu_rq_prio_o : out std_logic_vector(3-1 downto 0);
rtu_rq_has_prio_o : out std_logic;
--WB
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_addr_i : in std_logic_vector(5 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_ack_o : out std_logic
);
end component;
-----------------------------------------------------------------------------
--Mini NIC
-----------------------------------------------------------------------------
component wr_mini_nic is
generic (
g_memsize_log2 : integer := 14;
g_buffer_little_endian : boolean := true
);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
-- System memory i/f
mem_data_o : out std_logic_vector(31 downto 0);
mem_addr_o : out std_logic_vector(g_memsize_log2-1 downto 0);
mem_data_i : in std_logic_vector(31 downto 0);
mem_wr_o : out std_logic;
-- WRF source/sink
src_data_o : out std_logic_vector(15 downto 0);
src_ctrl_o : out std_logic_vector(4 - 1 downto 0);
src_bytesel_o : out std_logic;
src_sof_p1_o : out std_logic;
src_eof_p1_o : out std_logic;
src_dreq_i : in std_logic;
src_valid_o : out std_logic;
src_error_p1_o : out std_logic;
src_error_p1_i : in std_logic;
snk_data_i : in std_logic_vector(15 downto 0);
snk_ctrl_i : in std_logic_vector(4 -1 downto 0);
snk_bytesel_i : in std_logic;
snk_sof_p1_i : in std_logic;
snk_eof_p1_i : in std_logic;
snk_dreq_o : out std_logic;
snk_valid_i : in std_logic;
snk_error_p1_o : out std_logic;
snk_error_p1_i : in std_logic;
-- TXTSU i/f
txtsu_port_id_i : in std_logic_vector(4 downto 0);
txtsu_frame_id_i : in std_logic_vector(16 -1 downto 0);
txtsu_tsval_i : in std_logic_vector(28 + 4 - 1 downto 0);
txtsu_valid_i : in std_logic;
txtsu_ack_o : out std_logic;
--WB
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_addr_i : in std_logic_vector(3 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_ack_o : out std_logic;
wb_irq_o : out std_logic
);
end component;
-----------------------------------------------------------------------------
--Dual-port RAM
......@@ -291,32 +130,7 @@ package wrcore_pkg is
trace_eret_o : out std_logic);
end component;
component wr_softpll
generic (
g_deglitcher_threshold : integer;
g_tag_bits : integer);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
clk_ref_i : in std_logic;
clk_dmtd_i : in std_logic;
clk_rx_i : in std_logic;
clk_aux_i: in std_logic;
dac_hpll_data_o : out std_logic_vector(15 downto 0);
dac_hpll_load_o : out std_logic;
dac_dmpll_data_o : out std_logic_vector(15 downto 0);
dac_dmpll_load_o : out std_logic;
wb_addr_i : in std_logic_vector(3 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_irq_o : out std_logic;
debug_o: out std_logic_vector(3 downto 0));
end component;
component xwr_mini_nic
generic (
......@@ -344,4 +158,63 @@ package wrcore_pkg is
wb_o : out t_wishbone_slave_out);
end component;
component wr_softpll
generic (
g_deglitcher_threshold : integer;
g_tag_bits : integer;
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
clk_ref_i : in std_logic;
clk_dmtd_i : in std_logic;
clk_rx_i : in std_logic;
clk_aux_i : in std_logic := '0';
dac_hpll_data_o : out std_logic_vector(15 downto 0);
dac_hpll_load_o : out std_logic;
dac_dmpll_data_o : out std_logic_vector(15 downto 0);
dac_dmpll_load_o : out std_logic;
dac_aux_data_o : out std_logic_vector(23 downto 0);
dac_aux_load_o : out std_logic;
clk_aux_lock_en_i : in std_logic;
clk_aux_locked_o : out std_logic;
wb_adr_i : in std_logic_vector(6 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_irq_o : out std_logic;
debug_o : out std_logic_vector(3 downto 0));
end component;
component wr_pps_gen
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD);
port (
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
pps_in_i : in std_logic;
pps_csync_o : out std_logic;
pps_out_o : out std_logic;
tm_utc_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
tm_time_valid_o : out std_logic);
end component;
end wrcore_pkg;
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