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a1602aaf
Commit
a1602aaf
authored
Aug 23, 2018
by
Vraliens
Committed by
Grzegorz Daniluk
Jan 21, 2019
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spartan6: depending on generic value, ch0 or ch1 can be used
parent
9347bd38
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Showing
5 changed files
with
35 additions
and
12 deletions
+35
-12
whiterabbitgtp_wrapper_tile_spartan6.vhd
...gtp_phy/spartan6/whiterabbitgtp_wrapper_tile_spartan6.vhd
+4
-2
wr_gtp_phy_spartan6.vhd
platform/xilinx/wr_gtp_phy/spartan6/wr_gtp_phy_spartan6.vhd
+16
-6
wr_xilinx_pkg.vhd
platform/xilinx/wr_xilinx_pkg.vhd
+4
-1
xwrc_platform_xilinx.vhd
platform/xilinx/xwrc_platform_xilinx.vhd
+9
-2
spec_top.vhd
top/spec_1_1/wr_streamers_demo/spec_top.vhd
+2
-1
No files found.
platform/xilinx/wr_gtp_phy/spartan6/whiterabbitgtp_wrapper_tile_spartan6.vhd
View file @
a1602aaf
...
@@ -37,6 +37,8 @@ entity WHITERABBITGTP_WRAPPER_TILE_SPARTAN6 is
...
@@ -37,6 +37,8 @@ entity WHITERABBITGTP_WRAPPER_TILE_SPARTAN6 is
PLLLKDET1_OUT
:
out
std_logic
;
PLLLKDET1_OUT
:
out
std_logic
;
RESETDONE0_OUT
:
out
std_logic
;
RESETDONE0_OUT
:
out
std_logic
;
RESETDONE1_OUT
:
out
std_logic
;
RESETDONE1_OUT
:
out
std_logic
;
REFSELDYPLL0
:
in
std_logic_vector
(
2
downto
0
):
=
(
others
=>
'0'
);
REFSELDYPLL1
:
in
std_logic_vector
(
2
downto
0
):
=
(
others
=>
'0'
);
----------------------- Receive Ports - 8b10b Decoder ----------------------
----------------------- Receive Ports - 8b10b Decoder ----------------------
RXCHARISK0_OUT
:
out
std_logic
;
RXCHARISK0_OUT
:
out
std_logic
;
RXCHARISK1_OUT
:
out
std_logic
;
RXCHARISK1_OUT
:
out
std_logic
;
...
@@ -483,8 +485,8 @@ begin
...
@@ -483,8 +485,8 @@ begin
REFCLKPLL1
=>
open
,
REFCLKPLL1
=>
open
,
REFCLKPWRDNB0
=>
tied_to_vcc_i
,
REFCLKPWRDNB0
=>
tied_to_vcc_i
,
REFCLKPWRDNB1
=>
tied_to_vcc_i
,
REFCLKPWRDNB1
=>
tied_to_vcc_i
,
REFSELDYPLL0
=>
tied_to_ground_vec_i
(
2
downto
0
)
,
REFSELDYPLL0
=>
REFSELDYPLL0
,
REFSELDYPLL1
=>
tied_to_ground_vec_i
(
2
downto
0
)
,
REFSELDYPLL1
=>
REFSELDYPLL1
,
RESETDONE0
=>
RESETDONE0_OUT
,
RESETDONE0
=>
RESETDONE0_OUT
,
RESETDONE1
=>
RESETDONE1_OUT
,
RESETDONE1
=>
RESETDONE1_OUT
,
TSTCLK0
=>
tied_to_ground_i
,
TSTCLK0
=>
tied_to_ground_i
,
...
...
platform/xilinx/wr_gtp_phy/spartan6/wr_gtp_phy_spartan6.vhd
View file @
a1602aaf
...
@@ -66,7 +66,7 @@ entity wr_gtp_phy_spartan6 is
...
@@ -66,7 +66,7 @@ entity wr_gtp_phy_spartan6 is
-- Port 0
-- Port 0
-- dedicated GTP clock input
-- dedicated GTP clock input
gtp_clk_i
:
in
std_logic
;
gtp
0
_clk_i
:
in
std_logic
;
-- TX path, synchronous to ch0_ref_clk_i
-- TX path, synchronous to ch0_ref_clk_i
ch0_ref_clk_i
:
in
std_logic
;
ch0_ref_clk_i
:
in
std_logic
;
...
@@ -118,6 +118,9 @@ entity wr_gtp_phy_spartan6 is
...
@@ -118,6 +118,9 @@ entity wr_gtp_phy_spartan6 is
ch0_rdy_o
:
out
std_logic
;
ch0_rdy_o
:
out
std_logic
;
-- Port 1
-- Port 1
-- dedicated GTP clock input
gtp1_clk_i
:
in
std_logic
;
ch1_ref_clk_i
:
in
std_logic
;
ch1_ref_clk_i
:
in
std_logic
;
ch1_tx_data_i
:
in
std_logic_vector
(
7
downto
0
)
:
=
"00000000"
;
ch1_tx_data_i
:
in
std_logic_vector
(
7
downto
0
)
:
=
"00000000"
;
...
@@ -137,6 +140,10 @@ entity wr_gtp_phy_spartan6 is
...
@@ -137,6 +140,10 @@ entity wr_gtp_phy_spartan6 is
ch1_tx_prbs_sel_i
:
in
std_logic_vector
(
2
downto
0
)
:
=
(
others
=>
'0'
);
ch1_tx_prbs_sel_i
:
in
std_logic_vector
(
2
downto
0
)
:
=
(
others
=>
'0'
);
ch1_rdy_o
:
out
std_logic
;
ch1_rdy_o
:
out
std_logic
;
-- PLL source
ch0_ref_sel_pll
:
in
std_logic_vector
(
2
downto
0
);
ch1_ref_sel_pll
:
in
std_logic_vector
(
2
downto
0
);
-- Serial I/O
-- Serial I/O
pad_txn0_o
:
out
std_logic
;
pad_txn0_o
:
out
std_logic
;
...
@@ -183,6 +190,8 @@ architecture rtl of wr_gtp_phy_spartan6 is
...
@@ -183,6 +190,8 @@ architecture rtl of wr_gtp_phy_spartan6 is
PLLLKDET1_OUT
:
out
std_logic
;
PLLLKDET1_OUT
:
out
std_logic
;
RESETDONE0_OUT
:
out
std_logic
;
RESETDONE0_OUT
:
out
std_logic
;
RESETDONE1_OUT
:
out
std_logic
;
RESETDONE1_OUT
:
out
std_logic
;
REFSELDYPLL0
:
in
std_logic_vector
(
2
downto
0
):
=
(
others
=>
'0'
);
REFSELDYPLL1
:
in
std_logic_vector
(
2
downto
0
):
=
(
others
=>
'0'
);
RXCHARISK0_OUT
:
out
std_logic
;
RXCHARISK0_OUT
:
out
std_logic
;
RXCHARISK1_OUT
:
out
std_logic
;
RXCHARISK1_OUT
:
out
std_logic
;
RXDISPERR0_OUT
:
out
std_logic
;
RXDISPERR0_OUT
:
out
std_logic
;
...
@@ -387,8 +396,8 @@ begin -- rtl
...
@@ -387,8 +396,8 @@ begin -- rtl
ch0_gtp_reset
<=
ch0_rst_synced
or
std_logic
(
not
ch0_reset_counter
(
ch0_reset_counter
'left
));
ch0_gtp_reset
<=
ch0_rst_synced
or
std_logic
(
not
ch0_reset_counter
(
ch0_reset_counter
'left
));
ch0_rx_rec_clk_pad
<=
ch0_gtp_clkout_int
(
1
);
ch0_rx_rec_clk_pad
<=
ch0_gtp_clkout_int
(
1
);
ch0_ref_clk_in
(
0
)
<=
gtp_clk_i
;
ch0_ref_clk_in
(
0
)
<=
gtp
0
_clk_i
;
ch0_ref_clk_in
(
1
)
<=
'0'
;
ch0_ref_clk_in
(
1
)
<=
gtp1_clk_i
;
-- Near-end PMA loopback or loopback selected with ch1_loopen_vec_i
-- Near-end PMA loopback or loopback selected with ch1_loopen_vec_i
ch0_gtp_loopback
<=
"010"
when
(
ch0_loopen_i
=
'1'
)
else
ch0_gtp_loopback
<=
"010"
when
(
ch0_loopen_i
=
'1'
)
else
ch0_loopen_vec_i
;
ch0_loopen_vec_i
;
...
@@ -554,8 +563,8 @@ begin -- rtl
...
@@ -554,8 +563,8 @@ begin -- rtl
ch1_gtp_reset
<=
ch1_rst_synced
or
std_logic
(
not
ch1_reset_counter
(
ch1_reset_counter
'left
));
ch1_gtp_reset
<=
ch1_rst_synced
or
std_logic
(
not
ch1_reset_counter
(
ch1_reset_counter
'left
));
ch1_rx_rec_clk_pad
<=
ch1_gtp_clkout_int
(
1
);
ch1_rx_rec_clk_pad
<=
ch1_gtp_clkout_int
(
1
);
ch1_ref_clk_in
(
0
)
<=
gtp_clk_i
;
ch1_ref_clk_in
(
0
)
<=
gtp
0
_clk_i
;
ch1_ref_clk_in
(
1
)
<=
'0'
;
ch1_ref_clk_in
(
1
)
<=
gtp1_clk_i
;
-- Near-end PMA loopback or loopback selected with ch1_loopen_vec_i
-- Near-end PMA loopback or loopback selected with ch1_loopen_vec_i
ch1_gtp_loopback
<=
"010"
when
(
ch1_loopen_i
=
'1'
)
else
ch1_gtp_loopback
<=
"010"
when
(
ch1_loopen_i
=
'1'
)
else
ch1_loopen_vec_i
;
ch1_loopen_vec_i
;
...
@@ -740,7 +749,8 @@ begin -- rtl
...
@@ -740,7 +749,8 @@ begin -- rtl
PLLLKDET1_OUT
=>
ch1_gtp_pll_lockdet
,
PLLLKDET1_OUT
=>
ch1_gtp_pll_lockdet
,
RESETDONE0_OUT
=>
ch0_gtp_reset_done
,
RESETDONE0_OUT
=>
ch0_gtp_reset_done
,
RESETDONE1_OUT
=>
ch1_gtp_reset_done
,
RESETDONE1_OUT
=>
ch1_gtp_reset_done
,
REFSELDYPLL0
=>
ch0_ref_sel_pll
,
REFSELDYPLL1
=>
ch1_ref_sel_pll
,
----------------------- Receive Ports - 8b10b Decoder ----------------------
----------------------- Receive Ports - 8b10b Decoder ----------------------
RXCHARISK0_OUT
=>
ch0_rx_k_int
,
RXCHARISK0_OUT
=>
ch0_rx_k_int
,
RXCHARISK1_OUT
=>
ch1_rx_k_int
,
RXCHARISK1_OUT
=>
ch1_rx_k_int
,
...
...
platform/xilinx/wr_xilinx_pkg.vhd
View file @
a1602aaf
...
@@ -116,7 +116,7 @@ package wr_xilinx_pkg is
...
@@ -116,7 +116,7 @@ package wr_xilinx_pkg is
g_enable_ch1
:
integer
:
=
1
;
g_enable_ch1
:
integer
:
=
1
;
g_simulation
:
integer
:
=
0
);
g_simulation
:
integer
:
=
0
);
port
(
port
(
gtp
_clk_i
:
in
std_logic
;
gtp
0_clk_i
:
in
std_logic
;
ch0_ref_clk_i
:
in
std_logic
:
=
'0'
;
ch0_ref_clk_i
:
in
std_logic
:
=
'0'
;
ch0_tx_data_i
:
in
std_logic_vector
(
7
downto
0
)
:
=
"00000000"
;
ch0_tx_data_i
:
in
std_logic_vector
(
7
downto
0
)
:
=
"00000000"
;
ch0_tx_k_i
:
in
std_logic
:
=
'0'
;
ch0_tx_k_i
:
in
std_logic
:
=
'0'
;
...
@@ -132,6 +132,7 @@ package wr_xilinx_pkg is
...
@@ -132,6 +132,7 @@ package wr_xilinx_pkg is
ch0_loopen_vec_i
:
in
std_logic_vector
(
2
downto
0
)
:
=
(
others
=>
'0'
);
ch0_loopen_vec_i
:
in
std_logic_vector
(
2
downto
0
)
:
=
(
others
=>
'0'
);
ch0_tx_prbs_sel_i
:
in
std_logic_vector
(
2
downto
0
)
:
=
(
others
=>
'0'
);
ch0_tx_prbs_sel_i
:
in
std_logic_vector
(
2
downto
0
)
:
=
(
others
=>
'0'
);
ch0_rdy_o
:
out
std_logic
;
ch0_rdy_o
:
out
std_logic
;
gtp1_clk_i
:
in
std_logic
;
ch1_ref_clk_i
:
in
std_logic
;
ch1_ref_clk_i
:
in
std_logic
;
ch1_tx_data_i
:
in
std_logic_vector
(
7
downto
0
)
:
=
"00000000"
;
ch1_tx_data_i
:
in
std_logic_vector
(
7
downto
0
)
:
=
"00000000"
;
ch1_tx_k_i
:
in
std_logic
:
=
'0'
;
ch1_tx_k_i
:
in
std_logic
:
=
'0'
;
...
@@ -147,6 +148,8 @@ package wr_xilinx_pkg is
...
@@ -147,6 +148,8 @@ package wr_xilinx_pkg is
ch1_loopen_vec_i
:
in
std_logic_vector
(
2
downto
0
)
:
=
(
others
=>
'0'
);
ch1_loopen_vec_i
:
in
std_logic_vector
(
2
downto
0
)
:
=
(
others
=>
'0'
);
ch1_tx_prbs_sel_i
:
in
std_logic_vector
(
2
downto
0
)
:
=
(
others
=>
'0'
);
ch1_tx_prbs_sel_i
:
in
std_logic_vector
(
2
downto
0
)
:
=
(
others
=>
'0'
);
ch1_rdy_o
:
out
std_logic
;
ch1_rdy_o
:
out
std_logic
;
ch0_ref_sel_pll
:
in
std_logic_vector
(
2
downto
0
)
:
=
(
others
=>
'0'
);
ch1_ref_sel_pll
:
in
std_logic_vector
(
2
downto
0
)
:
=
(
others
=>
'0'
);
pad_txn0_o
:
out
std_logic
;
pad_txn0_o
:
out
std_logic
;
pad_txp0_o
:
out
std_logic
;
pad_txp0_o
:
out
std_logic
;
pad_rxn0_i
:
in
std_logic
:
=
'0'
;
pad_rxn0_i
:
in
std_logic
:
=
'0'
;
...
...
platform/xilinx/xwrc_platform_xilinx.vhd
View file @
a1602aaf
...
@@ -1031,7 +1031,9 @@ begin -- architecture rtl
...
@@ -1031,7 +1031,9 @@ begin -- architecture rtl
gen_phy_spartan6
:
if
(
g_fpga_family
=
"spartan6"
)
generate
gen_phy_spartan6
:
if
(
g_fpga_family
=
"spartan6"
)
generate
signal
clk_125m_gtp_buf
:
std_logic
;
signal
clk_125m_gtp_buf
:
std_logic
;
signal
clk_125m_gtp1_buf
:
std_logic
;
signal
clk_125m_gtp0_buf
:
std_logic
;
signal
ch0_phy8_out
,
ch1_phy8_out
:
t_phy_8bits_to_wrc
;
signal
ch0_phy8_out
,
ch1_phy8_out
:
t_phy_8bits_to_wrc
;
...
@@ -1059,7 +1061,7 @@ begin -- architecture rtl
...
@@ -1059,7 +1061,7 @@ begin -- architecture rtl
g_enable_ch0
=>
g_gtp_enable_ch0
,
g_enable_ch0
=>
g_gtp_enable_ch0
,
g_enable_ch1
=>
g_gtp_enable_ch1
)
g_enable_ch1
=>
g_gtp_enable_ch1
)
port
map
(
port
map
(
gtp
_clk_i
=>
clk_125m_gtp
_buf
,
gtp
0_clk_i
=>
clk_125m_gtp0
_buf
,
ch0_ref_clk_i
=>
clk_125m_pllref_buf
,
ch0_ref_clk_i
=>
clk_125m_pllref_buf
,
ch0_tx_data_i
=>
phy8_i
.
tx_data
,
ch0_tx_data_i
=>
phy8_i
.
tx_data
,
ch0_tx_k_i
=>
phy8_i
.
tx_k
(
0
),
ch0_tx_k_i
=>
phy8_i
.
tx_k
(
0
),
...
@@ -1075,6 +1077,7 @@ begin -- architecture rtl
...
@@ -1075,6 +1077,7 @@ begin -- architecture rtl
ch0_loopen_vec_i
=>
phy8_i
.
loopen_vec
,
ch0_loopen_vec_i
=>
phy8_i
.
loopen_vec
,
ch0_tx_prbs_sel_i
=>
phy8_i
.
tx_prbs_sel
,
ch0_tx_prbs_sel_i
=>
phy8_i
.
tx_prbs_sel
,
ch0_rdy_o
=>
ch0_phy8_out
.
rdy
,
ch0_rdy_o
=>
ch0_phy8_out
.
rdy
,
gtp1_clk_i
=>
clk_125m_gtp1_buf
,
ch1_ref_clk_i
=>
clk_125m_pllref_buf
,
ch1_ref_clk_i
=>
clk_125m_pllref_buf
,
ch1_tx_data_i
=>
phy8_i
.
tx_data
,
ch1_tx_data_i
=>
phy8_i
.
tx_data
,
ch1_tx_k_i
=>
phy8_i
.
tx_k
(
0
),
ch1_tx_k_i
=>
phy8_i
.
tx_k
(
0
),
...
@@ -1101,6 +1104,8 @@ begin -- architecture rtl
...
@@ -1101,6 +1104,8 @@ begin -- architecture rtl
);
);
gen_gtp_ch0
:
if
(
g_gtp_enable_ch0
=
1
and
g_gtp_enable_ch1
=
0
)
generate
gen_gtp_ch0
:
if
(
g_gtp_enable_ch0
=
1
and
g_gtp_enable_ch1
=
0
)
generate
clk_125m_gtp0_buf
<=
clk_125m_gtp_buf
;
clk_125m_gtp1_buf
<=
'0'
;
ch0_phy8_out
.
ref_clk
<=
clk_125m_pllref_buf
;
ch0_phy8_out
.
ref_clk
<=
clk_125m_pllref_buf
;
ch0_phy8_out
.
sfp_tx_fault
<=
sfp_tx_fault_i
;
ch0_phy8_out
.
sfp_tx_fault
<=
sfp_tx_fault_i
;
ch0_phy8_out
.
sfp_los
<=
sfp_los_i
;
ch0_phy8_out
.
sfp_los
<=
sfp_los_i
;
...
@@ -1112,6 +1117,8 @@ begin -- architecture rtl
...
@@ -1112,6 +1117,8 @@ begin -- architecture rtl
end
generate
gen_gtp_ch0
;
end
generate
gen_gtp_ch0
;
gen_gtp_ch1
:
if
(
g_gtp_enable_ch0
=
0
and
g_gtp_enable_ch1
=
1
)
generate
gen_gtp_ch1
:
if
(
g_gtp_enable_ch0
=
0
and
g_gtp_enable_ch1
=
1
)
generate
clk_125m_gtp0_buf
<=
'0'
;
clk_125m_gtp1_buf
<=
clk_125m_gtp_buf
;
ch1_phy8_out
.
ref_clk
<=
clk_125m_pllref_buf
;
ch1_phy8_out
.
ref_clk
<=
clk_125m_pllref_buf
;
ch1_phy8_out
.
sfp_tx_fault
<=
sfp_tx_fault_i
;
ch1_phy8_out
.
sfp_tx_fault
<=
sfp_tx_fault_i
;
ch1_phy8_out
.
sfp_los
<=
sfp_los_i
;
ch1_phy8_out
.
sfp_los
<=
sfp_los_i
;
...
...
top/spec_1_1/wr_streamers_demo/spec_top.vhd
View file @
a1602aaf
...
@@ -632,7 +632,8 @@ begin
...
@@ -632,7 +632,8 @@ begin
g_enable_ch1
=>
1
,
g_enable_ch1
=>
1
,
g_simulation
=>
g_simulation
)
g_simulation
=>
g_simulation
)
port
map
(
port
map
(
gtp_clk_i
=>
clk_gtp
,
gtp0_clk_i
=>
'0'
,
gtp1_clk_i
=>
clk_gtp
,
ch1_ref_clk_i
=>
clk_ref
,
ch1_ref_clk_i
=>
clk_ref
,
...
...
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