eca: initialize RAMs with 0 instead of undefined values

a3f85c63 · Wesley W. Terpstra · 361090f2 · a3f85c63 · a3f85c63
Commit a3f85c63 authored Mar 01, 2013 by Wesley W. Terpstra
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Showing with 2 additions and 2 deletions

eca_sdp.vhd modules/wr_eca/eca_sdp.vhd +1 -1

eca_tdp.vhd modules/wr_eca/eca_tdp.vhd +1 -1

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--- a/modules/wr_eca/eca_sdp.vhd
+++ b/modules/wr_eca/eca_sdp.vhd
@@ -51,7 +51,7 @@ architecture rtl of eca_sdp is
  type ram_t is array(2**g_addr_bits-1 downto 0) of 
    std_logic_vector(g_data_bits-1 downto 0);
    
-  signal ram : ram_t;
+  signal ram : ram_t := (others => (others => '0'));
 begin
  
  r : process(r_clk_i)

--- a/modules/wr_eca/eca_tdp.vhd
+++ b/modules/wr_eca/eca_tdp.vhd
@@ -58,7 +58,7 @@ architecture rtl of eca_tdp is
  type ram_t is array(2**g_addr_bits-1 downto 0) of 
    std_logic_vector(g_data_bits-1 downto 0);
    
-  signal ram : ram_t;
+  signal ram : ram_t := (others => (others => '0'));
 begin
  
  a : process(a_clk_i)