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White Rabbit core collection
Commit a88cad03 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski Committed by Maciej Lipinski
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wr_streamers: added fixed latency diagnostic counter registers (timely/late/timed-out frames)

parent f4574723
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Showing with 750 additions and 494 deletions
modules/wr_streamers/streamers_pkg.vhd
View file @ a88cad03
......@@ -139,6 +139,11 @@ package streamers_pkg is
filter_remote : std_logic;
-- value in cycles of fixed-latency enforced on data
fixed_latency : std_logic_vector(27 downto 0);
-- value in cycles of fixed-latency timeout (if it takes longer than this value
-- to output the packet, it's dropped)
fixed_latency_timeout : std_logic_vector(27 downto 0);
-- software controlled reset
sw_reset : std_logic;
end record;
......@@ -169,6 +174,7 @@ package streamers_pkg is
accept_broadcasts => '1',
filter_remote => '0',
fixed_latency => x"0000000",
fixed_latency_timeout => x"1000000",
sw_reset => '0');
constant c_tx_streamer_cfg_default: t_tx_streamer_cfg :=(
......
modules/wr_streamers/wr_streamers_wb.vhd
View file @ a88cad03
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : wr_streamers_wb.vhd
-- Author : auto-generated by wbgen2 from wr_streamers_wb.wb
-- Created : Fri Oct 19 19:28:20 2018
-- Created : Wed Nov 14 18:57:24 2018
-- Version : 0x00000001
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
......@@ -76,6 +76,7 @@ signal wr_streamers_dbg_ctrl_mux_int : std_logic ;
signal wr_streamers_dbg_ctrl_start_byte_int : std_logic_vector(7 downto 0);
signal wr_streamers_rstr_rst_sw_dly0 : std_logic ;
signal wr_streamers_rstr_rst_sw_int : std_logic ;
signal wr_streamers_rx_cfg6_rx_fixed_latency_timeout_int : std_logic_vector(27 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
......@@ -131,6 +132,7 @@ begin
wr_streamers_dbg_ctrl_mux_int <= '0';
wr_streamers_dbg_ctrl_start_byte_int <= "00000000";
wr_streamers_rstr_rst_sw_int <= '0';
wr_streamers_rx_cfg6_rx_fixed_latency_timeout_int <= "0000000000000000000000000000";
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
......@@ -630,6 +632,41 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(2) <= '1';
ack_in_progress <= '1';
when "100011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_stat14_rx_buf_overflow_cnt_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_stat15_rx_late_frames_cnt_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_stat16_rx_timeout_frames_cnt_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_stat17_rx_match_frames_cnt_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100111" =>
if (wb_we_i = '1') then
wr_streamers_rx_cfg6_rx_fixed_latency_timeout_int <= wrdata_reg(27 downto 0);
end if;
rddata_reg(27 downto 0) <= wr_streamers_rx_cfg6_rx_fixed_latency_timeout_int;
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
......@@ -762,6 +799,12 @@ begin
end process;
-- WR Streamer RX Buffer Overflow Count
-- WR Streamer RX Late Frames Count
-- WR Streamer RX Timed-out Frames Count
-- WR Streamer RX OK Frames Count
-- RX Fixed Latency Timeout
regs_o.rx_cfg6_rx_fixed_latency_timeout_o <= wr_streamers_rx_cfg6_rx_fixed_latency_timeout_int;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
wb_err_o <= '0';
......
modules/wr_streamers/wr_streamers_wb.wb
View file @ a88cad03
......@@ -290,6 +290,9 @@ peripheral {
};
};
reg {
name = "Tx Config Reg 0";
prefix = "TX_CFG0";
......@@ -641,4 +644,75 @@ peripheral {
type = MONOSTABLE;
};
};
reg {
name = "Rx statistics";
prefix = "RX_STAT14";
field {
name = "WR Streamer RX Buffer Overflow Count";
description = "Number of RX buffer overflow events";
prefix = "RX_BUF_OVERFLOW_CNT";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Rx statistics";
prefix = "RX_STAT15";
field {
name = "WR Streamer RX Late Frames Count";
description = "Number of RX frames that missed their fixed-latency deadline";
prefix = "RX_LATE_FRAMES_CNT";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Rx statistics";
prefix = "RX_STAT16";
field {
name = "WR Streamer RX Timed-out Frames Count";
description = "Number of RX frames that had their execution timestamp too far in the future (exceeding the RX_CFG6 value)";
prefix = "RX_TIMEOUT_FRAMES_CNT";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Rx statistics";
prefix = "RX_STAT17";
field {
name = "WR Streamer RX OK Frames Count";
description = "Number of RX executed on time in the fixed latency mode";
prefix = "RX_MATCH_FRAMES_CNT";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Rx Config Reg 6";
prefix = "RX_CFG6";
field {
name = "RX Fixed Latency Timeout";
prefix = "RX_FIXED_LATENCY_TIMEOUT";
type = SLV;
size = 28;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
};
modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd
View file @ a88cad03
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : wr_streamers_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from wr_streamers_wb.wb
-- Created : Fri Oct 19 19:28:20 2018
-- Created : Wed Nov 14 18:57:24 2018
-- Version : 0x00000001
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
......@@ -41,6 +41,10 @@ package wr_streamers_wbgen2_pkg is
rx_stat13_rx_latency_acc_cnt_msb_i : std_logic_vector(31 downto 0);
dbg_data_i : std_logic_vector(31 downto 0);
dummy_dummy_i : std_logic_vector(31 downto 0);
rx_stat14_rx_buf_overflow_cnt_i : std_logic_vector(31 downto 0);
rx_stat15_rx_late_frames_cnt_i : std_logic_vector(31 downto 0);
rx_stat16_rx_timeout_frames_cnt_i : std_logic_vector(31 downto 0);
rx_stat17_rx_match_frames_cnt_i : std_logic_vector(31 downto 0);
end record;
constant c_wr_streamers_in_registers_init_value: t_wr_streamers_in_registers := (
......@@ -63,7 +67,11 @@ package wr_streamers_wbgen2_pkg is
rx_stat12_rx_latency_acc_cnt_lsb_i => (others => '0'),
rx_stat13_rx_latency_acc_cnt_msb_i => (others => '0'),
dbg_data_i => (others => '0'),
dummy_dummy_i => (others => '0')
dummy_dummy_i => (others => '0'),
rx_stat14_rx_buf_overflow_cnt_i => (others => '0'),
rx_stat15_rx_late_frames_cnt_i => (others => '0'),
rx_stat16_rx_timeout_frames_cnt_i => (others => '0'),
rx_stat17_rx_match_frames_cnt_i => (others => '0')
);
-- Output registers (WB slave -> user design)
......@@ -102,6 +110,7 @@ package wr_streamers_wbgen2_pkg is
dbg_ctrl_mux_o : std_logic;
dbg_ctrl_start_byte_o : std_logic_vector(7 downto 0);
rstr_rst_sw_o : std_logic;
rx_cfg6_rx_fixed_latency_timeout_o : std_logic_vector(27 downto 0);
end record;
constant c_wr_streamers_out_registers_init_value: t_wr_streamers_out_registers := (
......@@ -137,7 +146,8 @@ package wr_streamers_wbgen2_pkg is
cfg_or_rx_fix_lat_o => '0',
dbg_ctrl_mux_o => '0',
dbg_ctrl_start_byte_o => (others => '0'),
rstr_rst_sw_o => '0'
rstr_rst_sw_o => '0',
rx_cfg6_rx_fixed_latency_timeout_o => (others => '0')
);
function "or" (left, right: t_wr_streamers_in_registers) return t_wr_streamers_in_registers;
......@@ -212,6 +222,10 @@ begin
tmp.rx_stat13_rx_latency_acc_cnt_msb_i := f_x_to_zero(left.rx_stat13_rx_latency_acc_cnt_msb_i) or f_x_to_zero(right.rx_stat13_rx_latency_acc_cnt_msb_i);
tmp.dbg_data_i := f_x_to_zero(left.dbg_data_i) or f_x_to_zero(right.dbg_data_i);
tmp.dummy_dummy_i := f_x_to_zero(left.dummy_dummy_i) or f_x_to_zero(right.dummy_dummy_i);
tmp.rx_stat14_rx_buf_overflow_cnt_i := f_x_to_zero(left.rx_stat14_rx_buf_overflow_cnt_i) or f_x_to_zero(right.rx_stat14_rx_buf_overflow_cnt_i);
tmp.rx_stat15_rx_late_frames_cnt_i := f_x_to_zero(left.rx_stat15_rx_late_frames_cnt_i) or f_x_to_zero(right.rx_stat15_rx_late_frames_cnt_i);
tmp.rx_stat16_rx_timeout_frames_cnt_i := f_x_to_zero(left.rx_stat16_rx_timeout_frames_cnt_i) or f_x_to_zero(right.rx_stat16_rx_timeout_frames_cnt_i);
tmp.rx_stat17_rx_match_frames_cnt_i := f_x_to_zero(left.rx_stat17_rx_match_frames_cnt_i) or f_x_to_zero(right.rx_stat17_rx_match_frames_cnt_i);
return tmp;
end function;
......
modules/wr_streamers/xrx_streamer.vhd
View file @ a88cad03
......@@ -122,6 +122,12 @@ entity xrx_streamer is
rx_data_o : out std_logic_vector(g_data_width-1 downto 0);
-- 1 indicted that rx_data_o is outputting a valid data word.
rx_valid_o : out std_logic;
-- 1 indicates the frame has been reproduced later than its desired fixed latency
rx_late_o : out std_logic;
-- 1 indicates the frame has been reproduced earlier than its desired fixed
-- latency due to the RX latency timeout
rx_timeout_o : out std_logic;
-- Synchronous data request input: when 1, the streamer may output another
-- data word in the subsequent clock cycle.
rx_dreq_i : in std_logic;
......@@ -140,7 +146,10 @@ entity xrx_streamer is
-- 1 when the latency on rx_latency_o is valid.
rx_latency_valid_o : out std_logic;
-- pulse when a frame was dropped due to buffer overflow
rx_overflow_p1_o : out std_logic;
rx_stat_overflow_p1_o : out std_logic;
rx_stat_match_p1_o : out std_logic;
rx_stat_late_p1_o : out std_logic;
rx_stat_timeout_p1_o : out std_logic;
-- received streamer frame (counts all frames, corrupted and not)
rx_frame_p1_o : out std_logic;
-- configuration
......@@ -345,6 +354,11 @@ begin -- rtl
rx_data_o => rx_data_o,
rx_valid_o => rx_valid_o,
rx_dreq_i => rx_dreq_i,
rx_late_o => rx_late_o,
rx_timeout_o => rx_timeout_o,
stat_match_p1_o => rx_stat_match_p1_o,
stat_late_p1_o => rx_stat_late_p1_o,
stat_timeout_p1_o => rx_stat_timeout_p1_o,
rx_streamer_cfg_i => rx_streamer_cfg_i);
......
modules/wr_streamers/xwr_streamers.vhd
View file @ a88cad03
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