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White Rabbit core collection
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White Rabbit core collection
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aaa69ce5
Commit
aaa69ce5
authored
Feb 09, 2012
by
Grzegorz Daniluk
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xwr_core, spec_top: ep rx buffer size generic is no longer log2
parent
01b80c76
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2 changed files
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4 additions
and
4 deletions
+4
-4
xwr_core.vhd
modules/wrc_core/xwr_core.vhd
+2
-2
spec_top.vhd
top/spec_1_1/wr_core_demo/spec_top.vhd
+2
-2
No files found.
modules/wrc_core/xwr_core.vhd
View file @
aaa69ce5
...
...
@@ -49,7 +49,7 @@ entity xwr_core is
g_simulation
:
integer
:
=
0
;
g_phys_uart
:
boolean
:
=
true
;
g_virtual_uart
:
boolean
:
=
false
;
g_ep_rxbuf_size
_log2
:
integer
:
=
12
;
g_ep_rxbuf_size
:
integer
:
=
1024
;
g_dpram_initf
:
string
:
=
""
;
g_dpram_size
:
integer
:
=
16384
;
--in 32-bit words
g_interface_mode
:
t_wishbone_interface_mode
:
=
CLASSIC
;
...
...
@@ -271,7 +271,7 @@ begin
g_simulation
=>
g_simulation
,
g_phys_uart
=>
g_phys_uart
,
g_virtual_uart
=>
g_virtual_uart
,
g_rx_buffer_size
=>
g_ep_rxbuf_size_log2
,
g_rx_buffer_size
=>
g_ep_rxbuf_size
,
g_dpram_initf
=>
g_dpram_initf
,
g_dpram_size
=>
g_dpram_size
,
g_interface_mode
=>
g_interface_mode
,
...
...
top/spec_1_1/wr_core_demo/spec_top.vhd
View file @
aaa69ce5
...
...
@@ -231,7 +231,7 @@ architecture rtl of spec_top is
g_simulation
:
integer
:
=
0
;
g_phys_uart
:
boolean
:
=
true
;
g_virtual_uart
:
boolean
:
=
false
;
g_ep_rxbuf_size
_log2
:
integer
:
=
12
;
g_ep_rxbuf_size
:
integer
:
=
1024
;
g_dpram_initf
:
string
:
=
""
;
g_dpram_size
:
integer
:
=
16384
;
--in 32-bit words
g_interface_mode
:
t_wishbone_interface_mode
:
=
CLASSIC
;
...
...
@@ -746,7 +746,7 @@ begin
g_simulation
=>
0
,
g_phys_uart
=>
true
,
g_virtual_uart
=>
false
,
g_ep_rxbuf_size
_log2
=>
12
,
g_ep_rxbuf_size
=>
1024
,
g_dpram_initf
=>
""
,
g_dpram_size
=>
16384
,
g_interface_mode
=>
PIPELINED
,
...
...
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