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W
White Rabbit core collection
Commit ad0b15e7 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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update submodules to include preamble shrinkage support

parent 4f4d6e79
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Showing with 4 additions and 3 deletions
modules/wrsw_txtsu/xwrsw_txtsu.vhd
View file @ ad0b15e7
......@@ -85,8 +85,9 @@ entity xwrsw_tx_tsu is
-- Wishbone bus
-------------------------------------------------------------------------------
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out;
int_o : out std_logic
);
......@@ -226,7 +227,7 @@ begin -- syn
wb_stb_i => wb_in.stb,
wb_we_i => wb_in.we,
wb_ack_o => wb_out.ack,
wb_int_o => wb_out.int,
wb_int_o => int_o,
txtsu_tsf_wr_req_i => txtsu_tsf_wr_req,
txtsu_tsf_wr_full_o => txtsu_tsf_wr_full,
txtsu_tsf_wr_empty_o => txtsu_tsf_wr_empty,
......
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