platform/altera: pass external reference clock through the platform module, in…

platform/altera: pass external reference clock through the platform module, in order to match the way this is done in the xilinx platform

platform/altera: pass external reference clock through the platform module, in…
platform/altera: pass external reference clock through the platform module, in order to match the way this is done in the xilinx platform
b01bf0e5 · Dimitris Lampridis · e766916d · b01bf0e5 · b01bf0e5 · b01bf0e5
Commit b01bf0e5 authored Feb 22, 2017 by Dimitris Lampridis
Showing with 10 additions and 3 deletions

xwrc_board_vfchd.vhd board/vfchd/xwrc_board_vfchd.vhd +4 -2

wr_altera_pkg.vhd platform/altera/wr_altera_pkg.vhd +1 -0

xwrc_platform_altera.vhd platform/altera/xwrc_platform_altera.vhd +5 -1

No files found.
--- a/board/vfchd/xwrc_board_vfchd.vhd
+++ b/board/vfchd/xwrc_board_vfchd.vhd
@@ -7,7 +7,7 @@
 -- Author(s)  : Dimitrios Lampridis  <dimitrios.lampridis@cern.ch>
 -- Company    : CERN (BE-CO-HT)
 -- Created    : 2016-07-26
-- Last update: 2017-02-20
+-- Last update: 2017-02-22
 -- Standard   : VHDL'93
 -------------------------------------------------------------------------------
 -- Description: Top-level wrapper for WR PTP core including all the modules
@@ -200,6 +200,7 @@ architecture struct of xwrc_board_vfchd is
  signal clk_pll_125m : std_logic;
  signal clk_pll_dmtd : std_logic;
  signal pll_locked   : std_logic;
+  signal clk_10m_ext  : std_logic;

  -- Reset logic
  signal rst_62m5_n       : std_logic;
@@ -294,6 +295,7 @@ begin  -- architecture struct
      clk_125m_ref_o       => clk_pll_125m,
      clk_62m5_dmtd_o      => clk_pll_dmtd,
      pll_locked_o         => pll_locked,
+      clk_10m_ext_o         => clk_10m_ext,
      phy8_o               => phy8_to_wrc,
      phy8_i               => phy8_from_wrc,
      phy16_o              => phy16_to_wrc,
@@ -410,7 +412,7 @@ begin  -- architecture struct
      clk_dmtd_i           => clk_pll_dmtd,
      clk_ref_i            => clk_pll_125m,
      clk_aux_i            => (others => '0'),
-      clk_ext_i            => clk_ext_10m_i,
+      clk_ext_i            => clk_10m_ext,
      clk_ext_mul_i        => ext_ref_mul,
      clk_ext_mul_locked_i => ext_ref_mul_locked,
      clk_ext_stopped_i    => '0',

--- a/platform/altera/wr_altera_pkg.vhd
+++ b/platform/altera/wr_altera_pkg.vhd
@@ -35,6 +35,7 @@ package wr_altera_pkg is
      clk_125m_ref_o        : out std_logic;
      clk_62m5_dmtd_o       : out std_logic;
      pll_locked_o          : out std_logic;
+      clk_10m_ext_o         : out std_logic;
      phy8_o                : out t_phy_8bits_to_wrc;
      phy8_i                : in  t_phy_8bits_from_wrc  := c_dummy_phy8_from_wrc;
      phy16_o               : out t_phy_16bits_to_wrc;

--- a/platform/altera/xwrc_platform_altera.vhd
+++ b/platform/altera/xwrc_platform_altera.vhd
@@ -7,7 +7,7 @@
 -- Author(s)  : Dimitrios Lampridis  <dimitrios.lampridis@cern.ch>
 -- Company    : CERN (BE-CO-HT)
 -- Created    : 2016-11-21
-- Last update: 2017-02-16
+-- Last update: 2017-02-22
 -- Standard   : VHDL'93
 -------------------------------------------------------------------------------
 -- Description: This module instantiates platform-specific modules that are
@@ -106,6 +106,7 @@ entity xwrc_platform_altera is
    clk_125m_ref_o        : out std_logic;
    clk_62m5_dmtd_o       : out std_logic;
    pll_locked_o          : out std_logic;
+    clk_10m_ext_o         : out std_logic;
    -- PHY
    phy8_o                : out t_phy_8bits_to_wrc;
    phy8_i                : in  t_phy_8bits_from_wrc  := c_dummy_phy8_from_wrc;
@@ -261,6 +262,9 @@ begin  -- architecture rtl
  -- always pass ext reference reset input to output, even when not used
  clk_ext_rst_o <= ext_ref_rst_i;

+  -- always pass ext reference clock input to output, even when not used
+  clk_10m_ext_o <= clk_10m_ext_i;
+
  -----------------------------------------------------------------------------
  -- Transceiver PHY
  -----------------------------------------------------------------------------