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White Rabbit core collection
Commit b51202e9 authored by Maciej Lipinski's avatar Maciej Lipinski Committed by Grzegorz Daniluk
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[streamers/review] added to boards the generic introduced in previous 

commit

this generics sets the operation mode of streamers (rx-only, tx-only
or rx_and_tx)
parent 4539e36f
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Showing with 35 additions and 14 deletions
board/common/wr_board_pkg.vhd
View file @ b51202e9
......@@ -80,6 +80,7 @@ package wr_board_pkg is
g_diag_ver : integer := 0;
g_diag_ro_size : integer := 0;
g_diag_rw_size : integer := 0;
g_streamers_op_mode : t_streamers_op_mode := TX_AND_RX;
g_tx_streamer_params : t_tx_streamer_params := c_tx_streamer_params_defaut;
g_rx_streamer_params : t_rx_streamer_params := c_rx_streamer_params_defaut;
g_fabric_iface : t_board_fabric_iface := PLAIN);
......
board/common/xwrc_board_common.vhd
View file @ b51202e9
......@@ -70,6 +70,7 @@ entity xwrc_board_common is
g_diag_ver : integer := 0;
g_diag_ro_size : integer := 0;
g_diag_rw_size : integer := 0;
g_streamers_op_mode : t_streamers_op_mode := TX_AND_RX;
g_tx_streamer_params : t_tx_streamer_params := c_tx_streamer_params_defaut;
g_rx_streamer_params : t_rx_streamer_params := c_rx_streamer_params_defaut;
g_fabric_iface : t_board_fabric_iface := PLAIN);
......@@ -423,6 +424,7 @@ begin -- architecture struct
cmp_xwr_transmission : xwr_transmission
generic map (
g_streamers_op_mode => g_streamers_op_mode,
g_tx_streamer_params => g_tx_streamer_params,
g_rx_streamer_params => g_rx_streamer_params)
port map (
......
board/spec/wr_spec_pkg.vhd
View file @ b51202e9
......@@ -17,6 +17,7 @@ package wr_spec_pkg is
g_with_external_clock_input : boolean := TRUE;
g_aux_clks : integer := 0;
g_fabric_iface : t_board_fabric_iface := plain;
g_streamers_op_mode : t_streamers_op_mode := TX_AND_RX;
g_tx_streamer_params : t_tx_streamer_params := c_tx_streamer_params_defaut;
g_rx_streamer_params : t_rx_streamer_params := c_rx_streamer_params_defaut;
g_dpram_initf : string := "default_xilinx";
......@@ -116,8 +117,9 @@ package wr_spec_pkg is
g_with_external_clock_input : integer := 1;
g_aux_clks : integer := 0;
g_fabric_iface : string := "plainfbrc";
g_tx_streamer_width : integer := 32;
g_rx_streamer_width : integer := 32;
g_streamers_op_mode : t_streamers_op_mode := TX_AND_RX;
g_tx_streamer_params : t_tx_streamer_params := c_tx_streamer_params_defaut;
g_rx_streamer_params : t_rx_streamer_params := c_rx_streamer_params_defaut;
g_dpram_initf : string := "default_xilinx";
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
......@@ -197,14 +199,14 @@ package wr_spec_pkg is
wrf_snk_stall_o : out std_logic;
wrf_snk_err_o : out std_logic;
wrf_snk_rty_o : out std_logic;
wrs_tx_data_i : in std_logic_vector(g_tx_streamer_width-1 downto 0) := (others => '0');
wrs_tx_data_i : in std_logic_vector(g_tx_streamer_params.data_width-1 downto 0) := (others => '0');
wrs_tx_valid_i : in std_logic := '0';
wrs_tx_dreq_o : out std_logic;
wrs_tx_last_i : in std_logic := '1';
wrs_tx_flush_i : in std_logic := '0';
wrs_rx_first_o : out std_logic;
wrs_rx_last_o : out std_logic;
wrs_rx_data_o : out std_logic_vector(g_rx_streamer_width-1 downto 0);
wrs_rx_data_o : out std_logic_vector(g_rx_streamer_params.data_width-1 downto 0);
wrs_rx_valid_o : out std_logic;
wrs_rx_dreq_i : in std_logic := '0';
wb_eth_adr_o : out std_logic_vector(c_wishbone_address_width-1 downto 0);
......
board/spec/wrc_board_spec.vhd
View file @ b51202e9
......@@ -66,6 +66,7 @@ entity wrc_board_spec is
-- "etherbone" = attach Etherbone slave to fabric interface
g_fabric_iface : string := "plainfbrc";
-- parameters configuration when g_fabric_iface = "streamers" (otherwise ignored)
g_streamers_op_mode : t_streamers_op_mode := TX_AND_RX;
g_tx_streamer_params : t_tx_streamer_params := c_tx_streamer_params_defaut;
g_rx_streamer_params : t_rx_streamer_params := c_rx_streamer_params_defaut;
-- memory initialisation file for embedded CPU
......@@ -379,6 +380,7 @@ begin -- architecture struct
g_with_external_clock_input => f_int2bool(g_with_external_clock_input),
g_aux_clks => g_aux_clks,
g_fabric_iface => f_str2iface_type(g_fabric_iface),
g_streamers_op_mode => g_streamers_op_mode,
g_tx_streamer_params => g_tx_streamer_params,
g_rx_streamer_params => g_rx_streamer_params,
g_dpram_initf => g_dpram_initf,
......
board/spec/xwrc_board_spec.vhd
View file @ b51202e9
......@@ -67,6 +67,7 @@ entity xwrc_board_spec is
-- etherbone = attach Etherbone slave to fabric interface
g_fabric_iface : t_board_fabric_iface := plain;
-- parameters configuration when g_fabric_iface = "streamers" (otherwise ignored)
g_streamers_op_mode : t_streamers_op_mode := TX_AND_RX;
g_tx_streamer_params : t_tx_streamer_params := c_tx_streamer_params_defaut;
g_rx_streamer_params : t_rx_streamer_params := c_rx_streamer_params_defaut;
-- memory initialisation file for embedded CPU
......@@ -409,6 +410,7 @@ begin -- architecture struct
g_diag_ver => g_diag_ver,
g_diag_ro_size => g_diag_ro_size,
g_diag_rw_size => g_diag_rw_size,
g_streamers_op_mode => g_streamers_op_mode,
g_tx_streamer_params => g_tx_streamer_params,
g_rx_streamer_params => g_rx_streamer_params,
g_fabric_iface => g_fabric_iface
......
board/svec/wr_svec_pkg.vhd
View file @ b51202e9
......@@ -17,6 +17,7 @@ package wr_svec_pkg is
g_with_external_clock_input : boolean := TRUE;
g_aux_clks : integer := 0;
g_fabric_iface : t_board_fabric_iface := plain;
g_streamers_op_mode : t_streamers_op_mode := TX_AND_RX;
g_tx_streamer_params : t_tx_streamer_params := c_tx_streamer_params_defaut;
g_rx_streamer_params : t_rx_streamer_params := c_rx_streamer_params_defaut;
g_dpram_initf : string := "default_xilinx";
......@@ -117,8 +118,9 @@ package wr_svec_pkg is
g_with_external_clock_input : integer := 1;
g_aux_clks : integer := 0;
g_fabric_iface : string := "plainfbrc";
g_tx_streamer_width : integer := 32;
g_rx_streamer_width : integer := 32;
g_streamers_op_mode : t_streamers_op_mode := TX_AND_RX;
g_tx_streamer_params : t_tx_streamer_params := c_tx_streamer_params_defaut;
g_rx_streamer_params : t_rx_streamer_params := c_rx_streamer_params_defaut;
g_dpram_initf : string := "default_xilinx";
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
......@@ -200,14 +202,14 @@ package wr_svec_pkg is
wrf_snk_stall_o : out std_logic;
wrf_snk_err_o : out std_logic;
wrf_snk_rty_o : out std_logic;
wrs_tx_data_i : in std_logic_vector(g_tx_streamer_width-1 downto 0) := (others => '0');
wrs_tx_data_i : in std_logic_vector(g_tx_streamer_params.data_width-1 downto 0) := (others => '0');
wrs_tx_valid_i : in std_logic := '0';
wrs_tx_dreq_o : out std_logic;
wrs_tx_last_i : in std_logic := '1';
wrs_tx_flush_i : in std_logic := '0';
wrs_rx_first_o : out std_logic;
wrs_rx_last_o : out std_logic;
wrs_rx_data_o : out std_logic_vector(g_rx_streamer_width-1 downto 0);
wrs_rx_data_o : out std_logic_vector(g_rx_streamer_params.data_width-1 downto 0);
wrs_rx_valid_o : out std_logic;
wrs_rx_dreq_i : in std_logic := '0';
wb_eth_adr_o : out std_logic_vector(c_wishbone_address_width-1 downto 0);
......
board/svec/wrc_board_svec.vhd
View file @ b51202e9
......@@ -66,6 +66,7 @@ entity wrc_board_svec is
-- "etherbone" = attach Etherbone slave to fabric interface
g_fabric_iface : string := "plainfbrc";
-- parameters configuration when g_fabric_iface = "streamers" (otherwise ignored)
g_streamers_op_mode : t_streamers_op_mode := TX_AND_RX;
g_tx_streamer_params : t_tx_streamer_params := c_tx_streamer_params_defaut;
g_rx_streamer_params : t_rx_streamer_params := c_rx_streamer_params_defaut;
-- memory initialisation file for embedded CPU
......@@ -381,6 +382,7 @@ begin -- architecture struct
g_with_external_clock_input => f_int2bool(g_with_external_clock_input),
g_aux_clks => g_aux_clks,
g_fabric_iface => f_str2iface_type(g_fabric_iface),
g_streamers_op_mode => g_streamers_op_mode,
g_tx_streamer_params => g_tx_streamer_params,
g_rx_streamer_params => g_rx_streamer_params,
g_dpram_initf => g_dpram_initf,
......
board/svec/xwrc_board_svec.vhd
View file @ b51202e9
......@@ -67,6 +67,7 @@ entity xwrc_board_svec is
-- etherbone = attach Etherbone slave to fabric interface
g_fabric_iface : t_board_fabric_iface := plain;
-- parameters configuration when g_fabric_iface = "streamers" (otherwise ignored)
g_streamers_op_mode : t_streamers_op_mode := TX_AND_RX;
g_tx_streamer_params : t_tx_streamer_params := c_tx_streamer_params_defaut;
g_rx_streamer_params : t_rx_streamer_params := c_rx_streamer_params_defaut;
-- memory initialisation file for embedded CPU
......@@ -421,6 +422,7 @@ begin -- architecture struct
g_diag_ver => g_diag_ver,
g_diag_ro_size => g_diag_ro_size,
g_diag_rw_size => g_diag_rw_size,
g_streamers_op_mode => g_streamers_op_mode,
g_tx_streamer_params => g_tx_streamer_params,
g_rx_streamer_params => g_rx_streamer_params,
g_fabric_iface => g_fabric_iface
......
board/vfchd/wr_vfchd_pkg.vhd
View file @ b51202e9
......@@ -17,6 +17,7 @@ package wr_vfchd_pkg is
g_aux_clks : integer := 0;
g_pcs_16bit : boolean := FALSE;
g_fabric_iface : t_board_fabric_iface := plain;
g_streamers_op_mode : t_streamers_op_mode := TX_AND_RX;
g_tx_streamer_params : t_tx_streamer_params := c_tx_streamer_params_defaut;
g_rx_streamer_params : t_rx_streamer_params := c_rx_streamer_params_defaut;
g_dpram_initf : string := "default_altera";
......@@ -101,8 +102,9 @@ package wr_vfchd_pkg is
g_pcs_16bit : integer := 0;
g_aux_clks : integer := 0;
g_fabric_iface : string := "plainfbrc";
g_tx_streamer_width : integer := 32;
g_rx_streamer_width : integer := 32;
g_streamers_op_mode : t_streamers_op_mode := TX_AND_RX;
g_tx_streamer_params : t_tx_streamer_params := c_tx_streamer_params_defaut;
g_rx_streamer_params : t_rx_streamer_params := c_rx_streamer_params_defaut;
g_dpram_initf : string := "default_altera";
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
......@@ -168,14 +170,14 @@ package wr_vfchd_pkg is
wrf_snk_stall_o : out std_logic;
wrf_snk_err_o : out std_logic;
wrf_snk_rty_o : out std_logic;
wrs_tx_data_i : in std_logic_vector(g_tx_streamer_width-1 downto 0) := (others => '0');
wrs_tx_data_i : in std_logic_vector(g_tx_streamer_params.data_width-1 downto 0) := (others => '0');
wrs_tx_valid_i : in std_logic := '0';
wrs_tx_dreq_o : out std_logic;
wrs_tx_last_i : in std_logic := '1';
wrs_tx_flush_i : in std_logic := '0';
wrs_rx_first_o : out std_logic;
wrs_rx_last_o : out std_logic;
wrs_rx_data_o : out std_logic_vector(g_rx_streamer_width-1 downto 0);
wrs_rx_data_o : out std_logic_vector(g_rx_streamer_params.data_width-1 downto 0);
wrs_rx_valid_o : out std_logic;
wrs_rx_dreq_i : in std_logic := '0';
wb_eth_adr_o : out std_logic_vector(c_wishbone_address_width-1 downto 0);
......
board/vfchd/wrc_board_vfchd.vhd
View file @ b51202e9
......@@ -68,6 +68,7 @@ entity wrc_board_vfchd is
-- "etherbone" = attach Etherbone slave to fabric interface
g_fabric_iface : string := "plainfbrc";
-- parameters configuration when g_fabric_iface = "streamers" (otherwise ignored)
g_streamers_op_mode : t_streamers_op_mode := TX_AND_RX;
g_tx_streamer_params : t_tx_streamer_params := c_tx_streamer_params_defaut;
g_rx_streamer_params : t_rx_streamer_params := c_rx_streamer_params_defaut;
-- memory initialisation file for embedded CPU
......@@ -366,6 +367,7 @@ begin -- architecture struct
g_aux_clks => g_aux_clks,
g_pcs_16bit => f_int2bool(g_pcs_16bit),
g_fabric_iface => f_str2iface_type(g_fabric_iface),
g_streamers_op_mode => g_streamers_op_mode,
g_tx_streamer_params => g_tx_streamer_params,
g_rx_streamer_params => g_rx_streamer_params,
g_dpram_initf => g_dpram_initf,
......
board/vfchd/xwrc_board_vfchd.vhd
View file @ b51202e9
......@@ -66,8 +66,9 @@ entity xwrc_board_vfchd is
-- etherbone = attach Etherbone slave to fabric interface
g_fabric_iface : t_board_fabric_iface := plain;
-- parameters configuration when g_fabric_iface = "streamers" (otherwise ignored)
g_tx_streamer_params : t_tx_streamer_params := c_tx_streamer_params_defaut;
g_rx_streamer_params : t_rx_streamer_params := c_rx_streamer_params_defaut;
g_streamers_op_mode : t_streamers_op_mode := TX_AND_RX;
g_tx_streamer_params : t_tx_streamer_params := c_tx_streamer_params_defaut;
g_rx_streamer_params : t_rx_streamer_params := c_rx_streamer_params_defaut;
-- memory initialisation file for embedded CPU
g_dpram_initf : string := "default_altera";
-- identification (id and ver) of the layout of words in the generic diag interface
......@@ -407,6 +408,7 @@ begin -- architecture struct
g_diag_ver => g_diag_ver,
g_diag_ro_size => g_diag_ro_size,
g_diag_rw_size => g_diag_rw_size,
g_streamers_op_mode => g_streamers_op_mode,
g_tx_streamer_params => g_tx_streamer_params,
g_rx_streamer_params => g_rx_streamer_params,
g_fabric_iface => g_fabric_iface
......
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