fix of stall/dreq in header processor + added debugging for chipscope

b633c853 · Maciej Lipinski · Grzegorz Daniluk · 5588e4c0 · b633c853 · b633c853
Commit b633c853 authored Nov 13, 2013 by Maciej Lipinski Committed by Grzegorz Daniluk Feb 04, 2014
5 changed files
--- a/modules/wr_endpoint/endpoint_private_pkg.vhd
+++ b/modules/wr_endpoint/endpoint_private_pkg.vhd
@@ -375,7 +375,8 @@ package endpoint_private_pkg is
      snk_fab_i  : in  t_ep_internal_fabric;
      snk_dreq_o : out std_logic;
      src_fab_o  : out t_ep_internal_fabric;
-      src_dreq_i : in  std_logic);
+      src_dreq_i : in  std_logic;
+      dbg_o      : out std_logic_vector(2 downto 0));
  end component;
  
  procedure f_pack_fifo_contents (

--- a/modules/wr_endpoint/ep_tx_crc_inserter.vhd
+++ b/modules/wr_endpoint/ep_tx_crc_inserter.vhd
@@ -53,7 +53,8 @@ entity ep_tx_crc_inserter is
    snk_dreq_o : out std_logic;

    src_fab_o  : out t_ep_internal_fabric;
-    src_dreq_i : in  std_logic
+    src_dreq_i : in  std_logic;
+    dbg_o      : out std_logic_vector(2 downto 0)
    );
 end ep_tx_crc_inserter;

@@ -79,6 +80,13 @@ architecture behavioral of ep_tx_crc_inserter is
  
 begin  -- behavioral

+  dbg_o          <= "111" when (state = IDLE) else
+                    "110" when (state = WAIT_CRC) else
+                    "101" when (state = EMBED_1) else
+                    "100" when (state = EMBED_2) else
+                    "011" when (state = EMBED_3) else
+                    "000";
+
  in_payload     <= '1' when (state = IDLE or state = WAIT_CRC) else '0';
 -- ML: potential optimization (if desperate)
 -- in_payload     <= '1' when (state = IDLE or state = WAIT_CRC) or (src_dreq_d0 = '1' and odd_length = '0' and state = EMBED_2)) else '0';

--- a/modules/wr_endpoint/ep_tx_header_processor.vhd
+++ b/modules/wr_endpoint/ep_tx_header_processor.vhd
@@ -565,7 +565,8 @@ begin  -- behavioral

  tx_en <= regs_i.ecr_tx_en_o and ep_ctrl and ep_ctrl_i; 

-  p_gen_stall : process(src_dreq_i, state, regs_i, wb_snk_i, snk_cyc_d0)
+  --p_gen_stall : process(src_dreq_i, state, regs_i, wb_snk_i, snk_cyc_d0, tx_en)
+  p_gen_stall : process(src_dreq_i, state, tx_en, wb_snk_i)
  begin
    --if(regs_i.ecr_tx_en_o = '0') then
    if(tx_en = '0') then --ML
@@ -575,9 +576,26 @@ begin  -- behavioral
 --      wb_out.stall <= '1';              -- /block for 1 cycle right upon
                                        -- detection of a packet, so the FSM
                                        -- has time to catch up
+    
+    -- once data is finished - cyc=LOW - but not neceserily TXF_DATA state, we make
+    -- sure that we stall the input to prevent new frame coming (it happened that 
+    -- frames were lost because of that - no SOF detected. SOF can happen in in IDLE only
+    -- so we need to keep stall HIGH till IDLE
+    elsif(state = TXF_DATA and wb_snk_i.cyc = '0') then -- accept OOB as is      
+      wb_out.stall <= '1';
+      
+    -- when data is flowing, we make stall HIGH only  if dreq_i is low
    elsif(src_dreq_i = '1' and state /= TXF_GAP and state /= TXF_ABORT and state /= TXF_DELAYED_SOF) then
      wb_out.stall <= '0';              -- during data/header phase - whenever
                                        -- the sink is ready to accept data
+    
+    -- when we receive OOB, there we have allwas resources/possibilties to accept it
+    -- since it is dumped in here, so we prevent dreq_i going LOW from stopping
+    -- to receive OOB
+    elsif(wb_snk_i.adr = c_WRF_OOB and wb_snk_i.stb = '1') then -- accept OOB as is
+      wb_out.stall <= '0';              
+
+    -- one other option renderds stall 
    else
      wb_out.stall <= '1';
    end if;

--- a/modules/wr_endpoint/ep_tx_path.vhd
+++ b/modules/wr_endpoint/ep_tx_path.vhd
@@ -132,7 +132,8 @@ entity ep_tx_path is
 -------------------------------------------------------------------------------
    ep_ctrl_i           : in std_logic :='1';
    regs_i : in t_ep_out_registers;
-    dbg_o          : out std_logic_vector(11 downto 0)
+--     dbg_o          : out std_logic_vector(11 downto 0)
+    dbg_o          : out std_logic_vector(33 downto 0)
    );


@@ -231,7 +232,8 @@ begin  -- rtl
      snk_fab_i  => fab_pipe(2),
      snk_dreq_o => dreq_pipe(2),
      src_fab_o  => fab_pipe(3),
-      src_dreq_i => dreq_pipe(3));
+      src_dreq_i => dreq_pipe(3),
+      dbg_o      => dbg_o(33 downto 31));

  pcs_fab_o    <= fab_pipe(3);
  dreq_pipe(3) <= pcs_dreq_i;
@@ -239,7 +241,12 @@ begin  -- rtl
  GEN_DBG: for i in 0 to 3 generate
    dbg_o(i)    <= fab_pipe(i).sof;
    dbg_o(i+4)  <= fab_pipe(i).eof;
-    dbg_o(i+8)  <= dreq_pipe(i);
  end generate GEN_DBG;
-
+    dbg_o(8)    <= dreq_pipe(0);
+    dbg_o(9)    <= dreq_pipe(1);
+    dbg_o(10)   <= dreq_pipe(2);
+    dbg_o(11) <= fab_pipe(0).dvalid;
+    dbg_o(12) <= fab_pipe(3).dvalid;
+    dbg_o(28 downto 13) <= fab_pipe(3).data;
+    dbg_o(30 downto 29) <= fab_pipe(3).addr;
 end rtl;
--- a/modules/wr_endpoint/wr_endpoint.vhd
+++ b/modules/wr_endpoint/wr_endpoint.vhd
@@ -358,7 +358,7 @@ architecture syn of wr_endpoint is
      inject_user_value_i    : in  std_logic_vector(15 downto 0) := x"0000";
      ep_ctrl_i              : in  std_logic                     := '1';
      regs_i                 : in  t_ep_out_registers;
-      dbg_o                  : out std_logic_vector(11 downto 0));
+      dbg_o                  : out std_logic_vector(33 downto 0));
  end component;

  component ep_rx_path
@@ -743,7 +743,8 @@ begin
      inject_user_value_i => inject_user_value_i,
      inject_packet_sel_i => inject_packet_sel_i,
      inject_ready_o      => inject_ready_o,
-      dbg_o               => dbg_o(43 downto 32)
+      dbg_o               => dbg_o(63 downto 30)
+--       dbg_o               => dbg_o(43 downto 32)
      );