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White Rabbit core collection
Commit ba95756c authored by Maciej Lipinski's avatar Maciej Lipinski Committed by Grzegorz Daniluk
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[wr_streamers] prevent sending streamer frames when link is down 

sending streamer frames when link is down causes weird behavior:
- the frames are counted as sent, while they are not
- some frames are dropped, depending on PHY implementation
- at startup, the link is reseted by software, so link is up for
  some time, then it goes down, than up again... mess

two additions:
- the dreq_o signal is gated with link_ok_i, so that frames cannot
  be sent when link is down
- startup counter which delays the start of sending frames
parent 58089e57
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Showing with 52 additions and 10 deletions
board/common/xwrc_board_common.vhd
View file @ ba95756c
......@@ -293,6 +293,9 @@ architecture struct of xwrc_board_common is
signal aux_diag_in : t_generic_word_array(c_diag_ro_size-1 downto 0);
signal aux_diag_out : t_generic_word_array(c_diag_rw_size-1 downto 0);
-- link state
signal link_ok : std_logic;
begin -- architecture struct
-- Check for unsupported fabric interface type
......@@ -415,8 +418,9 @@ begin -- architecture struct
rst_aux_n_o => aux_rst_n,
aux_diag_i => aux_diag_in,
aux_diag_o => aux_diag_out,
link_ok_o => link_ok_o);
link_ok_o => link_ok);
link_ok_o <= link_ok;
tm_time_valid_o <= tm_time_valid;
tm_tai_o <= tm_tai;
tm_cycles_o <= tm_cycles;
......@@ -427,7 +431,8 @@ begin -- architecture struct
generic map (
g_streamers_op_mode => g_streamers_op_mode,
g_tx_streamer_params => g_tx_streamer_params,
g_rx_streamer_params => g_rx_streamer_params)
g_rx_streamer_params => g_rx_streamer_params,
g_simulation => g_simulation)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
......@@ -449,6 +454,7 @@ begin -- architecture struct
tm_time_valid_i => tm_time_valid,
tm_tai_i => tm_tai,
tm_cycles_i => tm_cycles,
link_ok_i => link_ok,
wb_slave_i => aux_master_out,
wb_slave_o => aux_master_in,
snmp_array_o => aux_diag_in(c_WR_TRANS_ARR_SIZE_OUT-1 downto 0),
......
modules/wr_streamers/streamers_pkg.vhd
View file @ ba95756c
......@@ -172,7 +172,8 @@ package streamers_pkg is
g_tx_threshold : integer := 128;
g_tx_max_words_per_frame : integer := 256;
g_tx_timeout : integer := 1024;
g_escape_code_disable : boolean := FALSE);
g_escape_code_disable : boolean := FALSE;
g_simulation : integer := 0);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
......@@ -182,6 +183,7 @@ package streamers_pkg is
tm_time_valid_i : in std_logic := '0';
tm_tai_i : in std_logic_vector(39 downto 0) := x"0000000000";
tm_cycles_i : in std_logic_vector(27 downto 0) := x"0000000";
link_ok_i : in std_logic := '1';
tx_data_i : in std_logic_vector(g_data_width-1 downto 0);
tx_valid_i : in std_logic;
tx_dreq_o : out std_logic;
......@@ -277,7 +279,8 @@ package streamers_pkg is
g_stats_acc_width : integer := 64;
-- WB i/f
g_slave_mode : t_wishbone_interface_mode := CLASSIC;
g_slave_granularity : t_wishbone_address_granularity := BYTE
g_slave_granularity : t_wishbone_address_granularity := BYTE;
g_simulation : integer := 0
);
port (
......@@ -305,6 +308,7 @@ package streamers_pkg is
tm_time_valid_i : in std_logic := '0';
tm_tai_i : in std_logic_vector(39 downto 0) := x"0000000000";
tm_cycles_i : in std_logic_vector(27 downto 0) := x"0000000";
link_ok_i : in std_logic := '1';
wb_slave_i : in t_wishbone_slave_in := cc_dummy_slave_in;
wb_slave_o : out t_wishbone_slave_out;
snmp_array_o : out t_generic_word_array(c_WR_TRANS_ARR_SIZE_OUT-1 downto 0);
......
modules/wr_streamers/xtx_streamer.vhd
View file @ ba95756c
......@@ -72,7 +72,10 @@ entity xtx_streamer is
-- DO NOT USE unless you know what you are doing
-- legacy stuff: the streamers initially used in Btrain did not check/insert the escape
-- code. This is justified if only one block of a known number of words is sent/expected
g_escape_code_disable : boolean := FALSE
g_escape_code_disable : boolean := FALSE;
-- simulation mode (used for startaup-timer)
g_simulation : integer :=0
);
port (
......@@ -100,6 +103,8 @@ entity xtx_streamer is
-- Fractional part of the second (in clk_ref_i cycles)
tm_cycles_i : in std_logic_vector(27 downto 0) := x"0000000";
-- status of the link, in principle the tx can be done only if link is oK
link_ok_i : in std_logic := '1';
---------------------------------------------------------------------------
-- User interface
---------------------------------------------------------------------------
......@@ -169,7 +174,9 @@ architecture rtl of xtx_streamer is
signal tag_cycles : std_logic_vector(27 downto 0);
signal tag_valid, tag_valid_latched : std_logic;
signal reset_dly : std_logic;
signal link_ok_delay_cnt : unsigned(25 downto 0);
constant c_link_ok_rst_delay : unsigned(25 downto 0) := to_unsigned(62500000, 26);-- 1s
constant c_link_ok_rst_delay_sim : unsigned(25 downto 0) := to_unsigned(6250 , 26); -- 100us
begin -- rtl
......@@ -533,13 +540,33 @@ begin -- rtl
end if;
end process;
-- after reset, leave some time before accepting requests. This delay
-- is dependent on link_ok signal. This is because after startup (and
-- any reset possibly) the PHY first shows link_ok but it is latter
-- restarted by softare... it is a bit of a mess in which we better
-- not send anything. Once this startup is done, we only relay on
-- link_ok, i.e. we do not accept requests when link_ok is false.
-- During operation (i.e. after start-up/reset, the behaviour of link_ok
-- signal is satisfactory
p_delay_reset: process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
reset_dly <= rst_n_i;
if rst_n_i = '0' then
if(g_simulation = 1) then
link_ok_delay_cnt <= c_link_ok_rst_delay_sim;
else
link_ok_delay_cnt <= c_link_ok_rst_delay;
end if;
else
-- first initial moments of link_ok_i high are ignored
if(link_ok_i = '1' and link_ok_delay_cnt > 0) then
link_ok_delay_cnt <= link_ok_delay_cnt-1;
end if;
end if;
end if;
end process;
tx_dreq_o <= (not tx_almost_full) and reset_dly;
tx_dreq_o <= '0' when (link_ok_delay_cnt > 0) else
(not tx_almost_full) and link_ok_i;
end rtl;
modules/wr_streamers/xwr_streamers.vhd
View file @ ba95756c
......@@ -88,7 +88,8 @@ entity xwr_streamers is
-- WB I/F configuration
-----------------------------------------------------------------------------------------
g_slave_mode : t_wishbone_interface_mode := CLASSIC;
g_slave_granularity : t_wishbone_address_granularity := BYTE
g_slave_granularity : t_wishbone_address_granularity := BYTE;
g_simulation : integer := 0
);
port (
......@@ -150,6 +151,8 @@ entity xwr_streamers is
-- Fractional part of the second (in clk_ref_i cycles)
tm_cycles_i : in std_logic_vector(27 downto 0) := x"0000000";
-- status of the link, in principle the tx can be done only if link is oK
link_ok_i : in std_logic;
-- wishbone interface
wb_slave_i : in t_wishbone_slave_in := cc_dummy_slave_in;
wb_slave_o : out t_wishbone_slave_out;
......@@ -203,7 +206,8 @@ begin
g_tx_threshold => g_tx_streamer_params.threshold,
g_tx_max_words_per_frame => g_tx_streamer_params.max_words_per_frame,
g_tx_timeout => g_tx_streamer_params.timeout,
g_escape_code_disable => g_tx_streamer_params.escape_code_disable)
g_escape_code_disable => g_tx_streamer_params.escape_code_disable,
g_simulation => g_simulation)
port map(
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
......@@ -213,6 +217,7 @@ begin
tm_time_valid_i => tm_time_valid_i,
tm_tai_i => tm_tai_i,
tm_cycles_i => tm_cycles_i,
link_ok_i => link_ok_i,
tx_data_i => tx_data_i,
tx_valid_i => tx_valid_i,
tx_dreq_o => tx_dreq_o,
......
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