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White Rabbit core collection
Commit be137550 authored by Maciej Lipinski's avatar Maciej Lipinski
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[wr transsmision] cleaning, adding description and missing WB register

parent ef699437
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wr_transmission_pkg.vhd
View file @ be137550
......@@ -10,7 +10,10 @@
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- Description: package to be called where xwr_transmission is used. Important
-- part of the package are the two constants that provide information about the
-- generic array size - this array is used to provide information about statistics
-- to the WRPC
--
-------------------------------------------------------------------------------
--
......@@ -35,7 +38,7 @@
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-05-30 1.0 mlipinsk Created
-- 2016-05-30 1.0 mlipinsk Created
library ieee;
use ieee.std_logic_1164.all;
......
wr_transmission_wb.vhd
View file @ be137550
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : wr_transmission_wb.vhd
-- Author : auto-generated by wbgen2 from wr_transmission_wb.wb
-- Created : Fri Jun 10 18:36:57 2016
-- Created : Mon Jun 13 00:35:45 2016
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_transmission_wb.wb
......@@ -39,6 +39,8 @@ architecture syn of wr_transmission_wb is
signal wr_transmission_sscr1_rst_stats_dly0 : std_logic ;
signal wr_transmission_sscr1_rst_stats_int : std_logic ;
signal wr_transmission_sscr1_rst_seq_id_dly0 : std_logic ;
signal wr_transmission_sscr1_rst_seq_id_int : std_logic ;
signal wr_transmission_dbg_ctrl_mux_int : std_logic ;
signal wr_transmission_dbg_ctrl_start_byte_int : std_logic_vector(7 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
......@@ -69,6 +71,7 @@ begin
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
wr_transmission_sscr1_rst_stats_int <= '0';
wr_transmission_sscr1_rst_seq_id_int <= '0';
wr_transmission_dbg_ctrl_mux_int <= '0';
wr_transmission_dbg_ctrl_start_byte_int <= "00000000";
elsif rising_edge(clk_sys_i) then
......@@ -78,6 +81,7 @@ begin
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
wr_transmission_sscr1_rst_stats_int <= '0';
wr_transmission_sscr1_rst_seq_id_int <= '0';
ack_in_progress <= '0';
else
end if;
......@@ -87,11 +91,12 @@ begin
when "0000" =>
if (wb_we_i = '1') then
wr_transmission_sscr1_rst_stats_int <= wrdata_reg(0);
wr_transmission_sscr1_rst_seq_id_int <= wrdata_reg(1);
end if;
rddata_reg(0) <= '0';
rddata_reg(1) <= regs_i.sscr1_rx_latency_acc_overflow_i;
rddata_reg(1) <= '0';
rddata_reg(2) <= regs_i.sscr1_rx_latency_acc_overflow_i;
rddata_reg(31 downto 4) <= regs_i.sscr1_rst_ts_cyc_i;
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
ack_sreg(2) <= '1';
ack_in_progress <= '1';
......@@ -233,6 +238,19 @@ begin
end process;
-- Reset tx seq id
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
wr_transmission_sscr1_rst_seq_id_dly0 <= '0';
regs_o.sscr1_rst_seq_id_o <= '0';
elsif rising_edge(clk_sys_i) then
wr_transmission_sscr1_rst_seq_id_dly0 <= wr_transmission_sscr1_rst_seq_id_int;
regs_o.sscr1_rst_seq_id_o <= wr_transmission_sscr1_rst_seq_id_int and (not wr_transmission_sscr1_rst_seq_id_dly0);
end if;
end process;
-- Latency accumulator overflow
-- Reset timestamp cycles
-- Reset timestamp 32 LSB of TAI
......@@ -245,7 +263,7 @@ begin
-- WR Streamer frame latency
-- WR Streamer frame latency counter
-- WR Streamer block loss count
-- Debug Tx or Rx
-- Debug Tx (0) or Rx (1)
regs_o.dbg_ctrl_mux_o <= wr_transmission_dbg_ctrl_mux_int;
-- Debug Start byte
regs_o.dbg_ctrl_start_byte_o <= wr_transmission_dbg_ctrl_start_byte_int;
......
wr_transmission_wb.wb
View file @ be137550
......@@ -2,7 +2,7 @@
peripheral {
name = "WR Transmission control and debug";
description ="dd";
description ="This WB registers allow to diagnose transmission and reception of data using WR streamers";
prefix = "wr_transmission";
hdl_entity = "wr_transmission_wb";
......@@ -13,7 +13,13 @@ peripheral {
field {
name = "Reset statistics";
prefix = "RST_STATS";
description = "Reset";
description = "Writing 1 reset counters, latency acc/max/min. This reset is timestamped";
type = MONOSTABLE;
};
field {
name = "Reset tx seq id";
prefix = "RST_SEQ_ID";
description = "Writing 1 reset sequence ID of transmitted frames";
type = MONOSTABLE;
};
field {
......@@ -28,7 +34,7 @@ peripheral {
field {
name = "Reset timestamp cycles";
prefix = "RST_TS_CYC";
description = "Timestamp of the last reset of stats (RST_STAT) -- count of cycles";
description = "Timestamp of the last reset of stats (RST_STAT) -- count of clock cycles";
type = SLV;
size = 28;
align = 4;
......@@ -159,7 +165,7 @@ peripheral {
field {
name = "WR Streamer block loss count";
description = "Number of indications that one or more blocks in a frame were lost (probably CRC\
error, since reset";
error) since reset";
prefix = "RX_LOST_BLOCK_CNT";
type = SLV;
size = 32;
......@@ -170,8 +176,10 @@ peripheral {
reg {
name = "DBG Control register";
prefix = "DBG_CTRL";
description = "This register is meant to control simple debugging of transmitted or received data.\
It allows to sniff a 32-bit word at a configurable offset from received or transmitted data.";
field {
name = "Debug Tx or Rx";
name = "Debug Tx (0) or Rx (1)";
prefix = "MUX";
type = BIT;
access_bus = READ_WRITE;
......@@ -180,6 +188,7 @@ peripheral {
field {
name = "Debug Start byte";
prefix = "START_BYTE";
description ="The offset, in bytes, from which the 32-bit word is read.";
type = SLV;
align =8;
size = 8;
......
wr_transmission_wbgen2_pkg.vhd
View file @ be137550
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : wr_transmission_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from wr_transmission_wb.wb
-- Created : Fri Jun 10 18:36:57 2016
-- Created : Mon Jun 13 00:35:45 2016
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_transmission_wb.wb
......@@ -57,12 +57,14 @@ package wr_transmission_wbgen2_pkg is
type t_wr_transmission_out_registers is record
sscr1_rst_stats_o : std_logic;
sscr1_rst_seq_id_o : std_logic;
dbg_ctrl_mux_o : std_logic;
dbg_ctrl_start_byte_o : std_logic_vector(7 downto 0);
end record;
constant c_wr_transmission_out_registers_init_value: t_wr_transmission_out_registers := (
sscr1_rst_stats_o => '0',
sscr1_rst_seq_id_o => '0',
dbg_ctrl_mux_o => '0',
dbg_ctrl_start_byte_o => (others => '0')
);
......
xwr_transmission.vhd
View file @ be137550
......@@ -6,11 +6,14 @@
-- Author : Maciej Lipinski
-- Company : CERN
-- Created : 2016-05-30
-- Last update: 2016-05-31
-- Last update: 2016-06-12
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- Description: This module wraps WR_Streamers-related stuff (i.e. rx,tx and
-- statistics) and provides wishbone access to the statistics and streamer's
-- control/status registers.
--
--
-------------------------------------------------------------------------------
--
......@@ -106,7 +109,6 @@ entity xwr_transmission is
---------------------------------------------------------------------------
-- WRC Timing interface, used for latency measurement
-- Caution: uses clk_ref_i clock domain!
---------------------------------------------------------------------------
-- White Rabbit reference clock
......@@ -203,7 +205,7 @@ begin
tx_dreq_o => tx_dreq_o,
tx_last_i => tx_last_i,
tx_flush_i => tx_flush_i,
tx_reset_seq_i => '0',
tx_reset_seq_i => regs_from_wb.sscr1_rst_seq_id_o,
tx_frame_o => tx_frame,
cfg_mac_local_i => x"000000000000",
cfg_mac_target_i => x"ffffffffffff",
......
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