Commit bfb54e4d authored by Wesley W. Terpstra's avatar Wesley W. Terpstra

altera: these files might not be instantiated in the top of the design

parent 21c633e3
......@@ -124,10 +124,10 @@ architecture rtl of altera_phase is
-- We ensure timing between these nodes via the state machine
attribute altera_attribute : string;
attribute altera_attribute OF rtl : architecture is
("-name SDC_STATEMENT ""set_false_path -from {altera_phase:*|prime_trap} -to {altera_phase:*|raw_trap}"";" &
"-name SDC_STATEMENT ""set_false_path -from {altera_phase:*|raw_trap} -to {altera_phase:*|sync_trap*}"";" &
"-name SDC_STATEMENT ""set_false_path -to {altera_phase:*|aligned*}"";" &
"-name SDC_STATEMENT ""set_false_path -from {altera_phase:*|gen_rstn*} -to {altera_phase:*|sync_rstn*}""");
("-name SDC_STATEMENT ""set_false_path -from {*|altera_phase:*|prime_trap} -to {*|altera_phase:*|raw_trap}"";" &
"-name SDC_STATEMENT ""set_false_path -from {*|altera_phase:*|raw_trap} -to {*|altera_phase:*|sync_trap*}"";" &
"-name SDC_STATEMENT ""set_false_path -to {*|altera_phase:*|aligned*}"";" &
"-name SDC_STATEMENT ""set_false_path -from {*|altera_phase:*|gen_rstn*} -to {*|altera_phase:*|sync_rstn*}""");
begin
-- Pulse width of phasedone_i can be less than clock period... so make a trap
......
......@@ -91,8 +91,8 @@ architecture rtl of altera_reset is
-- We ensure timing between these nodes via the state machine
attribute altera_attribute : string;
attribute altera_attribute OF rtl : architecture is
("-name SDC_STATEMENT ""set_false_path -to {altera_reset:*|locked[2]}"";" &
"-name SDC_STATEMENT ""set_false_path -from {altera_reset:*|waiting} -to {altera_reset:*|nresets*}""");
("-name SDC_STATEMENT ""set_false_path -to {*|altera_reset:*|locked[2]}"";" &
"-name SDC_STATEMENT ""set_false_path -from {*|altera_reset:*|waiting} -to {*|altera_reset:*|nresets*}""");
begin
......
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