Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
W
White Rabbit core collection
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
30
Issues
30
List
Board
Labels
Milestones
Merge Requests
2
Merge Requests
2
CI / CD
CI / CD
Pipelines
Schedules
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
White Rabbit core collection
Commits
bfb54e4d
Commit
bfb54e4d
authored
Dec 18, 2013
by
Wesley W. Terpstra
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
altera: these files might not be instantiated in the top of the design
parent
21c633e3
Hide whitespace changes
Inline
Side-by-side
Showing
2 changed files
with
6 additions
and
6 deletions
+6
-6
altera_phase.vhd
platform/altera/altera_phase.vhd
+4
-4
altera_reset.vhd
platform/altera/altera_reset.vhd
+2
-2
No files found.
platform/altera/altera_phase.vhd
View file @
bfb54e4d
...
...
@@ -124,10 +124,10 @@ architecture rtl of altera_phase is
-- We ensure timing between these nodes via the state machine
attribute
altera_attribute
:
string
;
attribute
altera_attribute
OF
rtl
:
architecture
is
(
"-name SDC_STATEMENT ""set_false_path -from {
altera_phase:*|prime_trap} -to {
altera_phase:*|raw_trap}"";"
&
"-name SDC_STATEMENT ""set_false_path -from {
altera_phase:*|raw_trap} -to {
altera_phase:*|sync_trap*}"";"
&
"-name SDC_STATEMENT ""set_false_path
-to {
altera_phase:*|aligned*}"";"
&
"-name SDC_STATEMENT ""set_false_path -from {
altera_phase:*|gen_rstn*} -to {
altera_phase:*|sync_rstn*}"""
);
(
"-name SDC_STATEMENT ""set_false_path -from {
*|altera_phase:*|prime_trap} -to {*|
altera_phase:*|raw_trap}"";"
&
"-name SDC_STATEMENT ""set_false_path -from {
*|altera_phase:*|raw_trap} -to {*|
altera_phase:*|sync_trap*}"";"
&
"-name SDC_STATEMENT ""set_false_path
-to {*|
altera_phase:*|aligned*}"";"
&
"-name SDC_STATEMENT ""set_false_path -from {
*|altera_phase:*|gen_rstn*} -to {*|
altera_phase:*|sync_rstn*}"""
);
begin
-- Pulse width of phasedone_i can be less than clock period... so make a trap
...
...
platform/altera/altera_reset.vhd
View file @
bfb54e4d
...
...
@@ -91,8 +91,8 @@ architecture rtl of altera_reset is
-- We ensure timing between these nodes via the state machine
attribute
altera_attribute
:
string
;
attribute
altera_attribute
OF
rtl
:
architecture
is
(
"-name SDC_STATEMENT ""set_false_path
-to {
altera_reset:*|locked[2]}"";"
&
"-name SDC_STATEMENT ""set_false_path -from {
altera_reset:*|waiting} -to {
altera_reset:*|nresets*}"""
);
(
"-name SDC_STATEMENT ""set_false_path
-to {*|
altera_reset:*|locked[2]}"";"
&
"-name SDC_STATEMENT ""set_false_path -from {
*|altera_reset:*|waiting} -to {*|
altera_reset:*|nresets*}"""
);
begin
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment