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White Rabbit core collection
Commit c1b532b9 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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switch-optimization: use new combinational logic CRC32 calculations to save resources 

Conflicts:

	modules/wr_endpoint/endpoint_vectorized_top.vhd
	modules/wr_endpoint/ep_rx_path.vhd
	modules/wr_endpoint/ep_tx_path.vhd
parent fab49768
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Showing with 84 additions and 30 deletions
modules/wr_endpoint/endpoint_pkg.vhd
View file @ c1b532b9
......@@ -163,7 +163,9 @@ package endpoint_pkg is
g_with_rtu : boolean := true;
g_with_leds : boolean := true;
g_with_dmtd : boolean := false;
g_with_packet_injection : boolean := false);
g_with_packet_injection : boolean := false;
g_use_new_rxcrc : boolean := false;
g_use_new_txcrc : boolean := false);
port (
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
......
modules/wr_endpoint/endpoint_private_pkg.vhd
View file @ c1b532b9
......@@ -370,6 +370,8 @@ package endpoint_private_pkg is
end component;
component ep_tx_crc_inserter
generic(
g_use_new_crc : boolean := false);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
......
modules/wr_endpoint/ep_crc32_pkg.vhd
View file @ c1b532b9
......@@ -9,7 +9,7 @@ package ep_crc32_pkg is
constant c_CRC32_INIT_VALUE : std_logic_vector(31 downto 0) := x"00000000";
function f_update_crc32_d16(d : std_logic_vector; data_in : std_logic_vector) return std_logic_vector;
function f_update_crc32_d8(d : std_logic_vector; data_in : std_logic_vector) return std_logic_vector;
function f_update_crc32_d8(d : std_logic_vector(31 downto 0); data_in : std_logic_vector(7 downto 0)) return std_logic_vector;
end ep_crc32_pkg;
......@@ -56,8 +56,8 @@ package body ep_crc32_pkg is
end f_update_crc32_d16;
function f_update_crc32_d8(d : std_logic_vector; data_in : std_logic_vector) return std_logic_vector is
variable q : std_logic_vector(d'length-1 downto 0);
function f_update_crc32_d8(d : std_logic_vector(31 downto 0); data_in : std_logic_vector(7 downto 0)) return std_logic_vector is
variable q : std_logic_vector(31 downto 0);
begin
q(7) := not ((not d(31)) xor (not d(25)) xor data_in(7) xor data_in(1));
q(6) := not ((not d(31)) xor (not d(30)) xor (not d(25)) xor (not d(24)) xor data_in(7) xor data_in(6) xor data_in(1) xor data_in(0));
......
modules/wr_endpoint/ep_rx_path.vhd
View file @ c1b532b9
......@@ -65,7 +65,8 @@ entity ep_rx_path is
g_with_rtu : boolean := true;
g_with_rx_buffer : boolean := true;
g_with_early_match : boolean := false;
g_rx_buffer_size : integer := 1024);
g_rx_buffer_size : integer := 1024;
g_use_new_crc : boolean := false);
port (
clk_sys_i : in std_logic;
clk_rx_i : in std_logic;
......@@ -210,6 +211,8 @@ architecture behavioral of ep_rx_path is
end component;
component ep_rx_crc_size_check
generic (
g_use_new_crc : boolean := false);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
......@@ -433,6 +436,8 @@ begin -- behavioral
regs_i => regs_i);
U_crc_size_checker : ep_rx_crc_size_check
generic map (
g_use_new_crc => g_use_new_crc)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_sys_i,
......
modules/wr_endpoint/ep_tx_crc_inserter.vhd
View file @ c1b532b9
......@@ -43,8 +43,11 @@ use work.gencores_pkg.all;
use work.wr_fabric_pkg.all;
use work.endpoint_private_pkg.all;
use work.ep_wbgen2_pkg.all;
use work.ep_crc32_pkg.all;
entity ep_tx_crc_inserter is
generic(
g_use_new_crc : boolean := false);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
......@@ -77,6 +80,9 @@ architecture behavioral of ep_tx_crc_inserter is
signal stored_msb : std_logic_vector(7 downto 0);
signal in_payload : std_logic;
signal src_dreq_d0 : std_logic;
signal crc_p_value, crc_n_value : std_logic_vector(31 downto 0);
--signal crc_next, crc_new : std_logic_vector(31 downto 0);
begin -- behavioral
......@@ -93,25 +99,55 @@ begin -- behavioral
crc_gen_reset <= '1' when rst_n_i = '0' or snk_fab_i.sof = '1' else '0';
crc_gen_enable <= '1' when (snk_fab_i.dvalid = '1' and in_payload = '1') else '0';
U_tx_crc_generator : gc_crc_gen
generic map (
g_polynomial => x"04C11DB7",
g_init_value => x"ffffffff",
g_residue => x"38fb2284",
g_data_width => 16,
g_half_width => 8,
g_sync_reset => 1,
g_dual_width => 1,
g_registered_match_output => false,
g_registered_crc_output => true)
port map (
clk_i => clk_sys_i,
rst_i => crc_gen_reset,
en_i => crc_gen_enable,
half_i => snk_fab_i.bytesel,
data_i => snk_fab_i.data,
match_o => open,
crc_o => crc_value);
gen_old_crc: if(g_use_new_crc = false) generate
U_tx_crc_generator : gc_crc_gen
generic map (
g_polynomial => x"04C11DB7",
g_init_value => x"ffffffff",
g_residue => x"38fb2284",
g_data_width => 16,
g_half_width => 8,
g_sync_reset => 1,
g_dual_width => 1,
g_registered_match_output => false,
g_registered_crc_output => true)
port map (
clk_i => clk_sys_i,
rst_i => crc_gen_reset,
en_i => crc_gen_enable,
half_i => snk_fab_i.bytesel,
data_i => snk_fab_i.data,
match_o => open,
crc_o => crc_value);
end generate;
gen_new_crc: if(g_use_new_crc = true) generate
p_check_crc_p: process(clk_sys_i)
begin
if falling_edge(clk_sys_i) then
if(crc_gen_reset = '1')then
crc_n_value <= c_CRC32_INIT_VALUE;
elsif(crc_gen_enable = '1') then
crc_n_value <= f_update_crc32_d8(crc_p_value, snk_fab_i.data(15 downto 8));
end if;
end if;
end process;
p_check_crc_n: process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if(crc_gen_reset = '1') then
crc_p_value <= c_CRC32_INIT_VALUE;
elsif(crc_gen_enable = '1' and snk_fab_i.bytesel = '0') then
crc_p_value <= f_update_crc32_d8(crc_n_value, snk_fab_i.data(7 downto 0));
end if;
end if;
end process;
crc_value <= crc_p_value when odd_length = '0' else
crc_n_value;
end generate;
p_delay_dreq: process(clk_sys_i)
begin
......
modules/wr_endpoint/ep_tx_path.vhd
View file @ c1b532b9
......@@ -51,7 +51,8 @@ entity ep_tx_path is
g_with_timestamper : boolean;
g_with_packet_injection : boolean;
g_with_inj_ctrl : boolean := true;
g_force_gap_length : integer
g_force_gap_length : integer;
g_use_new_crc : boolean
);
port (
......@@ -294,6 +295,8 @@ begin -- rtl
end generate gen_without_injection;
U_Insert_CRC : ep_tx_crc_inserter
generic map(
g_use_new_crc => g_use_new_crc)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
......
modules/wr_endpoint/wr_endpoint.vhd
View file @ c1b532b9
......@@ -70,7 +70,9 @@ entity wr_endpoint is
g_with_rtu : boolean := true;
g_with_leds : boolean := true;
g_with_dmtd : boolean := false;
g_with_packet_injection : boolean := false
g_with_packet_injection : boolean := false;
g_use_new_rxcrc : boolean := false;
g_use_new_txcrc : boolean := false
);
port (
......@@ -330,7 +332,8 @@ architecture syn of wr_endpoint is
g_with_vlans : boolean;
g_with_timestamper : boolean;
g_with_packet_injection : boolean;
g_force_gap_length : integer);
g_force_gap_length : integer;
g_use_new_crc : boolean := false);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
......@@ -368,7 +371,8 @@ architecture syn of wr_endpoint is
g_with_dpi_classifier : boolean;
g_with_rtu : boolean;
g_with_rx_buffer : boolean;
g_rx_buffer_size : integer);
g_rx_buffer_size : integer;
g_use_new_crc : boolean);
port (
clk_sys_i : in std_logic;
clk_rx_i : in std_logic;
......@@ -713,7 +717,8 @@ begin
g_with_packet_injection => g_with_packet_injection,
g_with_vlans => g_with_vlans,
g_with_timestamper => g_with_timestamper,
g_force_gap_length => g_tx_force_gap_length)
g_force_gap_length => g_tx_force_gap_length,
g_use_new_crc => g_use_new_txcrc)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
......@@ -775,7 +780,8 @@ begin
g_with_dpi_classifier => g_with_dpi_classifier,
g_with_rtu => g_with_rtu,
g_with_rx_buffer => g_with_rx_buffer,
g_rx_buffer_size => g_rx_buffer_size)
g_rx_buffer_size => g_rx_buffer_size,
g_use_new_crc => g_use_new_rxcrc)
port map (
clk_sys_i => clk_sys_i,
clk_rx_i => phy_rx_clk_i,
......
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