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Commit c274e164 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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modules/wr_endpoint: added partial RTU header extraction

parent 8fb28aa5
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modules/wr_endpoint/Manifest.py
View file @ c274e164
......@@ -19,9 +19,10 @@ files = [ "endpoint_private_pkg.vhd",
"ep_ts_counter.vhd",
"ep_rx_status_reg_insert.vhd",
"ep_timestamping_unit.vhd",
"ep_leds_controller.vhd",
"ep_rtu_header_extract.vhd",
# "ep_flow_control.vhd",
# "ep_timestamping_unit.vhd",
# "ep_rmon_counters.vhd",
"ep_rx_buffer.vhd",
"ep_sync_detect.vhd",
......
modules/wr_endpoint/endpoint_private_pkg.vhd
View file @ c274e164
......@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-11-18
-- Last update: 2011-10-26
-- Last update: 2012-01-19
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -46,7 +46,7 @@ use work.ep_wbgen2_pkg.all;
use work.wr_fabric_pkg.all;
package endpoint_private_pkg is
-- special/control characters
constant c_k28_5 : std_logic_vector(7 downto 0) := "10111100"; -- bc
constant c_k23_7 : std_logic_vector(7 downto 0) := "11110111"; -- f7
......@@ -85,23 +85,23 @@ package endpoint_private_pkg is
prio : std_logic_vector(2 downto 0);
has_vid : std_logic;
has_prio : std_logic;
hash : std_logic_vector(15 downto 0);
end record;
type t_rmon_triggers is record
rx_sync_lost : std_logic;
rx_invalid_code : std_logic;
rx_overrun : std_logic;
rx_crc_err : std_logic;
rx_ok : std_logic;
rx_pfilter_drop : std_logic;
rx_runt : std_logic;
rx_giant : std_logic;
rx_pause : std_logic;
rx_pcs_err : std_logic;
rx_buffer_overrun : std_logic;
rx_rtu_overrun : std_logic;
rx_path_timing_failure: std_logic;
rx_sync_lost : std_logic;
rx_invalid_code : std_logic;
rx_overrun : std_logic;
rx_crc_err : std_logic;
rx_ok : std_logic;
rx_pfilter_drop : std_logic;
rx_runt : std_logic;
rx_giant : std_logic;
rx_pause : std_logic;
rx_pcs_err : std_logic;
rx_buffer_overrun : std_logic;
rx_rtu_overrun : std_logic;
rx_path_timing_failure : std_logic;
tx_pause : std_logic;
tx_underrun : std_logic;
......@@ -285,6 +285,19 @@ package endpoint_private_pkg is
purge_i : in std_logic);
end component;
component ep_leds_controller
generic (
g_blink_period_log2 : integer);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
dvalid_tx_i : in std_logic;
dvalid_rx_i : in std_logic;
link_ok_i : in std_logic;
led_link_o : out std_logic;
led_act_o : out std_logic);
end component;
--function f_pack_fifo_contents (
-- data : std_logic_vector;
-- sof : std_logic;
......@@ -361,7 +374,7 @@ package body endpoint_private_pkg is
else
if(fab.sof = '1' or fab.error = '1' or fab.eof = '1' or fab.has_rx_timestamp = '1') then
-- tag = 01
dout(17) <= 'X';
dout(17) <= 'X';
dout(16) <= '1';
dout(15) <= fab.sof;
dout(14) <= fab.eof;
......@@ -409,7 +422,7 @@ package body endpoint_private_pkg is
fab.bytesel <= (not din(16)) and din(17);
end if;
else
fab.bytesel <= 'X';
fab.bytesel <= 'X';
fab.dvalid <= '0';
fab.sof <= '0';
fab.eof <= '0';
......
modules/wr_endpoint/ep_rtu_header_extract.vhd 0 → 100644
View file @ c274e164
library ieee;
use ieee.std_logic_1164.all;
use work.endpoint_private_pkg.all;
entity ep_rtu_header_extract is
generic(
g_with_rtu : boolean);
port(
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
snk_fab_i : in t_ep_internal_fabric;
snk_dreq_o : out std_logic;
src_fab_o : out t_ep_internal_fabric;
src_dreq_i : in std_logic;
rtu_rq_o : out t_ep_internal_rtu_request;
rtu_full_i : in std_logic;
rtu_rq_valid_o : out std_logic
);
end ep_rtu_header_extract;
architecture rtl of ep_rtu_header_extract is
signal hdr_offset : std_logic_vector(11 downto 0);
signal in_packet : std_logic;
procedure f_extract_rtu(signal q : out std_logic_vector;
signal fab : t_ep_internal_fabric;
signal at_offset : std_logic) is
begin
if(at_offset = '1' and fab.dvalid = '1') then
q <= fab.data;
end if;
end f_extract_rtu;
begin -- rtl
gen_with_rtu : if(g_with_rtu) generate
p_hdr_offset_sreg : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if (rst_n_i = '0' or snk_fab_i.sof = '1') then
hdr_offset(hdr_offset'left downto 1) <= (others => '0');
hdr_offset(0) <= '1';
elsif(snk_fab_i.dvalid = '1') then
hdr_offset <= hdr_offset(hdr_offset'left-1 downto 0) & '0';
end if;
end if;
end process;
p_gen_rtu_request : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
rtu_rq_o.smac <= (others => '0');
rtu_rq_o.dmac <= (others => '0');
rtu_rq_o.vid <= (others => '0');
rtu_rq_o.has_vid <= '0';
rtu_rq_o.prio <= (others => '0');
rtu_rq_o.has_prio <= '0';
in_packet <= '0';
else
if(snk_fab_i.sof = '1' and rtu_full_i = '0') then
in_packet <= '1';
end if;
if(snk_fab_i.eof = '1' or snk_fab_i.error = '1') then
in_packet <= '0';
end if;
f_extract_rtu(rtu_rq_o.dmac(47 downto 32), snk_fab_i, hdr_offset(0));
f_extract_rtu(rtu_rq_o.dmac(31 downto 16), snk_fab_i, hdr_offset(1));
f_extract_rtu(rtu_rq_o.dmac(15 downto 0), snk_fab_i, hdr_offset(2));
f_extract_rtu(rtu_rq_o.smac(47 downto 32), snk_fab_i, hdr_offset(3));
f_extract_rtu(rtu_rq_o.smac(31 downto 16), snk_fab_i, hdr_offset(4));
f_extract_rtu(rtu_rq_o.smac(15 downto 0), snk_fab_i, hdr_offset(5));
if(hdr_offset(5) = '1' and in_packet = '1') then
rtu_rq_valid_o <= '1';
else
rtu_rq_valid_o <= '0';
end if;
end if;
end if;
end process;
src_fab_o.sof <= snk_fab_i.sof and not rtu_full_i;
end generate gen_with_rtu;
gen_without_rtu : if (not g_with_rtu) generate
src_fab_o.sof <= snk_fab_i.sof;
end generate gen_without_rtu;
snk_dreq_o <= src_dreq_i;
src_fab_o.eof <= snk_fab_i.eof;
src_fab_o.dvalid <= snk_fab_i.dvalid;
src_fab_o.error <= snk_fab_i.error;
src_fab_o.bytesel <= snk_fab_i.bytesel;
src_fab_o.data <= snk_fab_i.data;
src_fab_o.addr <= snk_fab_i.addr;
src_fab_o.has_rx_timestamp <= snk_fab_i.has_rx_timestamp;
end rtl;
modules/wr_endpoint/ep_rx_early_address_match.vhd
View file @ c274e164
......@@ -11,8 +11,6 @@ use work.ep_wbgen2_pkg.all;
-- to filter out pause and HP frames in advance.
entity ep_rx_early_address_match is
generic (
g_with_rtu : boolean);
port(
clk_sys_i : in std_logic;
clk_rx_i : in std_logic;
......@@ -28,8 +26,6 @@ entity ep_rx_early_address_match is
match_is_pause_o : out std_logic;
match_pause_quanta_o : out std_logic_vector(15 downto 0);
rtu_rq_o : out t_ep_internal_rtu_request;
regs_i : in t_ep_out_registers
);
......@@ -56,14 +52,7 @@ architecture behavioral of ep_rx_early_address_match is
end if;
end f_compare_slv;
procedure f_extract_rtu(signal q : out std_logic_vector;
signal fab : t_ep_internal_fabric;
signal at_offset : std_logic) is
begin
if(at_offset = '1' and fab.dvalid = '1') then
q <= fab.data;
end if;
end f_extract_rtu;
begin -- behavioral
......@@ -126,24 +115,7 @@ begin -- behavioral
end if;
end process;
gen_with_rtu : if(g_with_rtu) generate
p_gen_rtu_request : process(clk_rx_i)
begin
if rising_edge(clk_rx_i) then
if rst_n_rx_i = '0' then
rtu_rq_o.smac <= (others => '0');
rtu_rq_o.dmac <= (others => '0');
else
f_extract_rtu(rtu_rq_o.dmac(47 downto 32), snk_fab_i, hdr_offset(0));
f_extract_rtu(rtu_rq_o.dmac(31 downto 16), snk_fab_i, hdr_offset(1));
f_extract_rtu(rtu_rq_o.dmac(15 downto 0), snk_fab_i, hdr_offset(2));
f_extract_rtu(rtu_rq_o.smac(47 downto 32), snk_fab_i, hdr_offset(3));
f_extract_rtu(rtu_rq_o.smac(31 downto 16), snk_fab_i, hdr_offset(4));
f_extract_rtu(rtu_rq_o.smac(15 downto 0), snk_fab_i, hdr_offset(5));
end if;
end if;
end process;
end generate gen_with_rtu;
p_match_hp : process(clk_rx_i)
......
modules/wr_endpoint/ep_rx_path.vhd
View file @ c274e164
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2009-06-22
-- Last update: 2011-10-29
-- Last update: 2012-01-19
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -101,9 +101,22 @@ end ep_rx_path;
architecture behavioral of ep_rx_path is
component ep_rx_early_address_match
component ep_rtu_header_extract
generic (
g_with_rtu : boolean);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
snk_fab_i : in t_ep_internal_fabric;
snk_dreq_o : out std_logic;
src_fab_o : out t_ep_internal_fabric;
src_dreq_i : in std_logic;
rtu_rq_o : out t_ep_internal_rtu_request;
rtu_full_i : in std_logic;
rtu_rq_valid_o : out std_logic);
end component;
component ep_rx_early_address_match
port (
clk_sys_i : in std_logic;
clk_rx_i : in std_logic;
......@@ -115,7 +128,6 @@ architecture behavioral of ep_rx_path is
match_is_hp_o : out std_logic;
match_is_pause_o : out std_logic;
match_pause_quanta_o : out std_logic_vector(15 downto 0);
rtu_rq_o : out t_ep_internal_rtu_request;
regs_i : in t_ep_out_registers);
end component;
......@@ -261,8 +273,8 @@ architecture behavioral of ep_rx_path is
type t_fab_pipe is array(integer range <>) of t_ep_internal_fabric;
signal fab_pipe : t_fab_pipe(0 to 8);
signal dreq_pipe : std_logic_vector(8 downto 0);
signal fab_pipe : t_fab_pipe(0 to 9);
signal dreq_pipe : std_logic_vector(9 downto 0);
signal ematch_done : std_logic;
signal ematch_is_hp : std_logic;
......@@ -285,8 +297,6 @@ begin -- behavioral
fab_pipe(0) <= pcs_fab_i;
U_early_addr_match : ep_rx_early_address_match
generic map (
g_with_rtu => g_with_rtu)
port map (
clk_sys_i => clk_sys_i,
......@@ -380,19 +390,34 @@ begin -- behavioral
regs_i => regs_i);
end generate gen_with_vlan_unit;
gen_without_vlan_unit: if(not g_with_vlans) generate
fab_pipe(6) <= fab_pipe(5);
dreq_pipe(5) <= dreq_pipe(6);
end generate gen_without_vlan_unit;
U_RTU_Header_Extract: ep_rtu_header_extract
generic map (
g_with_rtu => g_with_rtu)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_sys_i,
snk_fab_i => fab_pipe(6),
snk_dreq_o => dreq_pipe(6),
src_fab_o => fab_pipe(7),
src_dreq_i => dreq_pipe(7),
rtu_rq_o => rtu_rq_o,
rtu_full_i => rtu_full_i,
rtu_rq_valid_o => rtu_rq_valid_o);
U_Gen_Status : ep_rx_status_reg_insert
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_sys_i,
snk_fab_i => fab_pipe(6),
snk_dreq_o => dreq_pipe(6),
src_fab_o => fab_pipe(7),
src_dreq_i => dreq_pipe(7),
snk_fab_i => fab_pipe(7),
snk_dreq_o => dreq_pipe(7),
src_fab_o => fab_pipe(8),
src_dreq_i => dreq_pipe(8),
pfilter_drop_i => pfilter_drop,
pfilter_pclass_i => pfilter_pclass,
pfilter_done_i => pfilter_done,
......@@ -408,26 +433,26 @@ begin -- behavioral
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_sys_i,
snk_fab_i => fab_pipe(7),
snk_dreq_o => dreq_pipe(7),
src_fab_o => fab_pipe(8),
src_dreq_i => dreq_pipe(8),
snk_fab_i => fab_pipe(8),
snk_dreq_o => dreq_pipe(8),
src_fab_o => fab_pipe(9),
src_dreq_i => dreq_pipe(9),
level_o => fc_buffer_occupation_o,
regs_i => regs_i,
rmon_o => open);
end generate gen_with_rx_buffer;
gen_without_rx_buffer: if (not g_with_rx_buffer) generate
fab_pipe(8) <= fab_pipe(7);
dreq_pipe(7) <= dreq_pipe(8);
fab_pipe(9) <= fab_pipe(8);
dreq_pipe(8) <= dreq_pipe(9);
end generate gen_without_rx_buffer;
U_RX_Wishbone_Master : ep_rx_wb_master
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_sys_i,
snk_fab_i => fab_pipe(8),
snk_dreq_o => dreq_pipe(8),
snk_fab_i => fab_pipe(9),
snk_dreq_o => dreq_pipe(9),
src_wb_i => src_wb_i,
src_wb_o => src_wb_o
);
......
modules/wr_endpoint/wr_endpoint.vhd
View file @ c274e164
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-04-26
-- Last update: 2012-01-13
-- Last update: 2012-01-19
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -66,10 +66,10 @@ entity wr_endpoint is
clk_ref_i : in std_logic;
-- reference clock / 2 (62.5 MHz, in-phase with refclk)
clk_sys_i : in std_logic;
clk_sys_i : in std_logic;
--
clk_dmtd_i:in std_logic;
clk_dmtd_i : in std_logic;
-- sync reset (clk_sys_i domain), active LO
rst_n_i : in std_logic;
......@@ -123,7 +123,7 @@ entity wr_endpoint is
src_we_o : out std_logic;
src_stall_i : in std_logic;
src_ack_i : in std_logic;
src_err_i : in std_logic;
src_err_i : in std_logic;
snk_dat_i : in std_logic_vector(15 downto 0);
snk_adr_i : in std_logic_vector(1 downto 0);
......@@ -189,15 +189,15 @@ entity wr_endpoint is
-- Wishbone bus
-------------------------------------------------------------------------------
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_adr_i : in std_logic_vector(7 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_ack_o : out std_logic;
wb_stall_o:out std_logic;
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_adr_i : in std_logic_vector(7 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-------------------------------------------------------------------------------
-- Misc stuff
......@@ -231,7 +231,7 @@ architecture syn of wr_endpoint is
phase_meas_o : out std_logic_vector(31 downto 0);
phase_meas_p_o : out std_logic);
end component;
component ep_tx_framer
generic (
g_with_vlans : boolean;
......@@ -466,6 +466,7 @@ architecture syn of wr_endpoint is
signal phase_meas_p : std_logic;
signal validity_cntr : unsigned(1 downto 0);
signal rtu_rq : t_ep_internal_rtu_request;
begin
......@@ -617,11 +618,21 @@ begin
rmon_o => rmon,
regs_i => regs_fromwb,
rtu_full_i => rtu_full_i,
src_wb_o => src_out,
src_wb_i => src_in
rtu_full_i => rtu_full_i,
rtu_rq_o => rtu_rq,
rtu_rq_valid_o => rtu_rq_strobe_p1_o,
src_wb_o => src_out,
src_wb_i => src_in
);
rtu_rq_smac_o <= rtu_rq.smac;
rtu_rq_dmac_o <= rtu_rq.dmac;
rtu_rq_vid_o <= rtu_rq.vid;
rtu_rq_prio_o <= rtu_rq.prio;
rtu_rq_has_vid_o <= rtu_rq.has_vid;
rtu_rq_has_prio_o <= rtu_rq.has_prio;
src_dat_o <= src_out.dat;
src_adr_o <= src_out.adr;
src_sel_o <= src_out.sel;
......@@ -630,7 +641,7 @@ begin
src_we_o <= src_out.we;
src_in.stall <= src_stall_i;
src_in.ack <= src_ack_i;
src_in.err <= src_err_i;
src_in.err <= src_err_i;
-------------------------------------------------------------------------------
-- Flow control unit
......@@ -723,8 +734,8 @@ begin
-------------------------------------------------------------------------------
extended_ADDR <= std_logic_vector(resize(unsigned(wb_adr_i), c_wishbone_address_width));
U_Slave_adapter: wb_slave_adapter
U_Slave_adapter : wb_slave_adapter
generic map (
g_master_use_struct => true,
g_master_mode => CLASSIC,
......@@ -746,7 +757,7 @@ begin
sl_stall_o => wb_stall_o,
master_i => wb_out,
master_o => wb_in);
U_WB_SLAVE : ep_wishbone_controller
port map (
rst_n_i => rst_n_sys,
......@@ -773,9 +784,9 @@ begin
);
wb_out.stall <= '0';
wb_out.rty <= '0';
wb_out.err <= '0';
wb_out.int <= '0';
wb_out.rty <= '0';
wb_out.err <= '0';
wb_out.int <= '0';
regs_towb <= regs_towb_ep or regs_towb_tsu;
......@@ -796,17 +807,17 @@ begin
end if;
end process;
-------------------------------------------------------------------------------
-- DMTD phase meter
------------------------------------------------------------------------------
U_DMTD : dmtd_phase_meas
generic map (
g_counter_bits => 14,
g_deglitcher_threshold => 1000 )
g_counter_bits => 14,
g_deglitcher_threshold => 1000)
port map (
clk_sys_i => clk_sys_i,
clk_sys_i => clk_sys_i,
clk_a_i => phy_ref_clk_i,
clk_b_i => phy_rx_clk_i,
......@@ -822,29 +833,42 @@ begin
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
validity_cntr <= (others => '0');
validity_cntr <= (others => '0');
regs_towb_ep.dmsr_ps_rdy_i <= '0';
else
if(regs_fromwb.dmcr_en_o = '0') then
validity_cntr <= (others => '0');
validity_cntr <= (others => '0');
regs_towb_ep.dmsr_ps_rdy_i <= '0';
elsif(regs_fromwb.dmsr_ps_rdy_o= '1' and regs_fromwb.dmsr_ps_rdy_load_o = '1') then
elsif(regs_fromwb.dmsr_ps_rdy_o = '1' and regs_fromwb.dmsr_ps_rdy_load_o = '1') then
regs_towb_ep.dmsr_ps_rdy_i <= '0';
elsif(phase_meas_p = '1') then
if(validity_cntr = "11") then
regs_towb_ep.dmsr_ps_rdy_i <= '1';
regs_towb_ep.dmsr_ps_val_i <= phase_meas(23 downto 0); -- discard few
regs_towb_ep.dmsr_ps_val_i <= phase_meas(23 downto 0); -- discard few
else
regs_towb_ep.dmsr_ps_rdy_i <= '0';
validity_cntr <= validity_cntr + 1;
validity_cntr <= validity_cntr + 1;
end if;
end if;
end if;
end if;
end process;
gen_leds : if g_with_leds generate
U_Led_Ctrl : ep_leds_controller
generic map (
g_blink_period_log2 => 20)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
dvalid_tx_i => txpcs_fab.dvalid,
dvalid_rx_i => rxpcs_fab.dvalid,
link_ok_i => link_ok,
led_link_o => led_link_o,
led_act_o => led_act_o);
end generate gen_leds;
end syn;
......
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