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White Rabbit core collection
Commit cbf6b50b authored by Dimitris Lampridis's avatar Dimitris Lampridis Committed by Maciej Lipinski
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cleanup: drive various signals when unused

parent 55cec38d
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Showing with 40 additions and 23 deletions
modules/wr_softpll_ng/spll_wb_slave.vhd
View file @ cbf6b50b
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : spll_wb_slave.vhd
-- Author : auto-generated by wbgen2 from spll_wb_slave.wb
-- Created : Thu Dec 3 18:39:19 2015
-- Created : Thu Apr 20 16:40:20 2017
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE spll_wb_slave.wb
......@@ -831,6 +831,11 @@ begin
);
end generate genblock_0;
genblock_1: if (g_with_debug_fifo = 0) generate
regs_o.dfr_host_wr_full_o <= '0';
regs_o.dfr_host_wr_empty_o <= '0';
regs_o.dfr_host_wr_usedw_o <= "0000000000000";
end generate genblock_1;
-- extra code for reg/fifo/mem: Tag Readout Register
spll_trr_in_int(23 downto 0) <= regs_i.trr_value_i;
spll_trr_in_int(30 downto 24) <= regs_i.trr_chan_id_i;
......
modules/wr_softpll_ng/spll_wbgen2_pkg.vhd
View file @ cbf6b50b
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : spll_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from spll_wb_slave.wb
-- Created : Thu Dec 3 18:39:19 2015
-- Created : Thu Apr 20 16:40:20 2017
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE spll_wb_slave.wb
......@@ -165,10 +165,10 @@ function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if x(i) = '1' then
tmp(i):= '1';
else
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
......
modules/wrc_core/xwr_syscon_wb.vhd
View file @ cbf6b50b
......@@ -6,7 +6,7 @@
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-11-07
-- Last update: 2012-08-02
-- Last update: 2017-04-20
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -110,7 +110,8 @@ begin
slave_o.err <= '0';
slave_o.rty <= '0';
slave_o.int <= '0';
end syn;
......
platform/altera/xwrc_platform_altera.vhd
View file @ cbf6b50b
......@@ -7,7 +7,7 @@
-- Author(s) : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2016-11-21
-- Last update: 2017-02-22
-- Last update: 2017-04-27
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: This module instantiates platform-specific modules that are
......@@ -18,22 +18,22 @@
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
--
-------------------------------------------------------------------------------
library ieee;
......@@ -234,9 +234,14 @@ begin -- architecture rtl
end generate gen_arria5_ext_ref_pll;
gen_arria5_no_ext_ref_pll : if (g_with_external_clock_input = FALSE) generate
ext_ref_mul_o <= '0';
ext_ref_mul_locked_o <= '1';
end generate gen_arria5_no_ext_ref_pll;
-- not provided by Altera PLL
ext_ref_mul_stopped_o <= '0';
end generate gen_arria5_default_plls;
end generate gen_default_plls;
......
platform/xilinx/xwrc_platform_xilinx.vhd
View file @ cbf6b50b
......@@ -334,6 +334,13 @@ begin -- architecture rtl
end generate gen_spartan6_ext_ref_pll;
gen_spartan6_no_ext_ref_pll : if (g_with_external_clock_input = FALSE) generate
clk_10m_ext_o <= '0';
ext_ref_mul_o <= '0';
ext_ref_mul_locked_o <= '1';
ext_ref_mul_stopped_o <= '1';
end generate gen_spartan6_no_ext_ref_pll;
end generate gen_spartan6_default_plls;
end generate gen_default_plls;
......@@ -344,7 +351,6 @@ begin -- architecture rtl
clk_62m5_sys_o <= clk_62m5_sys_i;
clk_62m5_dmtd_o <= clk_62m5_dmtd_i;
clk_125m_ref_o <= clk_125m_ref_i;
clk_10m_ext_o <= clk_10m_ext_i;
pll_locked_o <= clk_sys_locked_i and clk_dmtd_locked_i;
......
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