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White Rabbit core collection
Commit cdad3f33 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski Committed by Maciej Lipinski
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wr_streamers: added fixed latency diagnostic counter registers (timely/late/timed-out frames)

parent 8f88535b
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Showing with 273 additions and 14 deletions
modules/wr_streamers/streamers_pkg.vhd
View file @ cdad3f33
...@@ -139,6 +139,11 @@ package streamers_pkg is ...@@ -139,6 +139,11 @@ package streamers_pkg is
filter_remote : std_logic; filter_remote : std_logic;
-- value in cycles of fixed-latency enforced on data -- value in cycles of fixed-latency enforced on data
fixed_latency : std_logic_vector(27 downto 0); fixed_latency : std_logic_vector(27 downto 0);
-- value in cycles of fixed-latency timeout (if it takes longer than this value
-- to output the packet, it's dropped)
fixed_latency_timeout : std_logic_vector(27 downto 0);
-- software controlled reset -- software controlled reset
sw_reset : std_logic; sw_reset : std_logic;
end record; end record;
...@@ -169,6 +174,7 @@ package streamers_pkg is ...@@ -169,6 +174,7 @@ package streamers_pkg is
accept_broadcasts => '1', accept_broadcasts => '1',
filter_remote => '0', filter_remote => '0',
fixed_latency => x"0000000", fixed_latency => x"0000000",
fixed_latency_timeout => x"1000000",
sw_reset => '0'); sw_reset => '0');
constant c_tx_streamer_cfg_default: t_tx_streamer_cfg :=( constant c_tx_streamer_cfg_default: t_tx_streamer_cfg :=(
......
modules/wr_streamers/wr_streamers_wb.vhd
View file @ cdad3f33
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- File : wr_streamers_wb.vhd -- File : wr_streamers_wb.vhd
-- Author : auto-generated by wbgen2 from wr_streamers_wb.wb -- Author : auto-generated by wbgen2 from wr_streamers_wb.wb
-- Created : Fri Oct 19 19:28:20 2018 -- Created : Wed Nov 14 18:57:24 2018
-- Version : 0x00000001 -- Version : 0x00000001
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
...@@ -76,6 +76,7 @@ signal wr_streamers_dbg_ctrl_mux_int : std_logic ; ...@@ -76,6 +76,7 @@ signal wr_streamers_dbg_ctrl_mux_int : std_logic ;
signal wr_streamers_dbg_ctrl_start_byte_int : std_logic_vector(7 downto 0); signal wr_streamers_dbg_ctrl_start_byte_int : std_logic_vector(7 downto 0);
signal wr_streamers_rstr_rst_sw_dly0 : std_logic ; signal wr_streamers_rstr_rst_sw_dly0 : std_logic ;
signal wr_streamers_rstr_rst_sw_int : std_logic ; signal wr_streamers_rstr_rst_sw_int : std_logic ;
signal wr_streamers_rx_cfg6_rx_fixed_latency_timeout_int : std_logic_vector(27 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0); signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0); signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0); signal wrdata_reg : std_logic_vector(31 downto 0);
...@@ -131,6 +132,7 @@ begin ...@@ -131,6 +132,7 @@ begin
wr_streamers_dbg_ctrl_mux_int <= '0'; wr_streamers_dbg_ctrl_mux_int <= '0';
wr_streamers_dbg_ctrl_start_byte_int <= "00000000"; wr_streamers_dbg_ctrl_start_byte_int <= "00000000";
wr_streamers_rstr_rst_sw_int <= '0'; wr_streamers_rstr_rst_sw_int <= '0';
wr_streamers_rx_cfg6_rx_fixed_latency_timeout_int <= "0000000000000000000000000000";
elsif rising_edge(clk_sys_i) then elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register -- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1); ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
...@@ -630,6 +632,41 @@ begin ...@@ -630,6 +632,41 @@ begin
rddata_reg(31) <= 'X'; rddata_reg(31) <= 'X';
ack_sreg(2) <= '1'; ack_sreg(2) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "100011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_stat14_rx_buf_overflow_cnt_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_stat15_rx_late_frames_cnt_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_stat16_rx_timeout_frames_cnt_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_stat17_rx_match_frames_cnt_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100111" =>
if (wb_we_i = '1') then
wr_streamers_rx_cfg6_rx_fixed_latency_timeout_int <= wrdata_reg(27 downto 0);
end if;
rddata_reg(27 downto 0) <= wr_streamers_rx_cfg6_rx_fixed_latency_timeout_int;
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others => when others =>
-- prevent the slave from hanging the bus on invalid address -- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1'; ack_in_progress <= '1';
...@@ -762,6 +799,12 @@ begin ...@@ -762,6 +799,12 @@ begin
end process; end process;
-- WR Streamer RX Buffer Overflow Count
-- WR Streamer RX Late Frames Count
-- WR Streamer RX Timed-out Frames Count
-- WR Streamer RX OK Frames Count
-- RX Fixed Latency Timeout
regs_o.rx_cfg6_rx_fixed_latency_timeout_o <= wr_streamers_rx_cfg6_rx_fixed_latency_timeout_int;
rwaddr_reg <= wb_adr_i; rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i); wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
wb_err_o <= '0'; wb_err_o <= '0';
......
modules/wr_streamers/wr_streamers_wb.wb
View file @ cdad3f33
...@@ -290,6 +290,9 @@ peripheral { ...@@ -290,6 +290,9 @@ peripheral {
}; };
}; };
reg { reg {
name = "Tx Config Reg 0"; name = "Tx Config Reg 0";
prefix = "TX_CFG0"; prefix = "TX_CFG0";
...@@ -641,4 +644,75 @@ peripheral { ...@@ -641,4 +644,75 @@ peripheral {
type = MONOSTABLE; type = MONOSTABLE;
}; };
}; };
reg {
name = "Rx statistics";
prefix = "RX_STAT14";
field {
name = "WR Streamer RX Buffer Overflow Count";
description = "Number of RX buffer overflow events";
prefix = "RX_BUF_OVERFLOW_CNT";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Rx statistics";
prefix = "RX_STAT15";
field {
name = "WR Streamer RX Late Frames Count";
description = "Number of RX frames that missed their fixed-latency deadline";
prefix = "RX_LATE_FRAMES_CNT";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Rx statistics";
prefix = "RX_STAT16";
field {
name = "WR Streamer RX Timed-out Frames Count";
description = "Number of RX frames that had their execution timestamp too far in the future (exceeding the RX_CFG6 value)";
prefix = "RX_TIMEOUT_FRAMES_CNT";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Rx statistics";
prefix = "RX_STAT17";
field {
name = "WR Streamer RX OK Frames Count";
description = "Number of RX executed on time in the fixed latency mode";
prefix = "RX_MATCH_FRAMES_CNT";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Rx Config Reg 6";
prefix = "RX_CFG6";
field {
name = "RX Fixed Latency Timeout";
prefix = "RX_FIXED_LATENCY_TIMEOUT";
type = SLV;
size = 28;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
}; };
modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd
View file @ cdad3f33
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- File : wr_streamers_wbgen2_pkg.vhd -- File : wr_streamers_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from wr_streamers_wb.wb -- Author : auto-generated by wbgen2 from wr_streamers_wb.wb
-- Created : Fri Oct 19 19:28:20 2018 -- Created : Wed Nov 14 18:57:24 2018
-- Version : 0x00000001 -- Version : 0x00000001
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
...@@ -41,6 +41,10 @@ package wr_streamers_wbgen2_pkg is ...@@ -41,6 +41,10 @@ package wr_streamers_wbgen2_pkg is
rx_stat13_rx_latency_acc_cnt_msb_i : std_logic_vector(31 downto 0); rx_stat13_rx_latency_acc_cnt_msb_i : std_logic_vector(31 downto 0);
dbg_data_i : std_logic_vector(31 downto 0); dbg_data_i : std_logic_vector(31 downto 0);
dummy_dummy_i : std_logic_vector(31 downto 0); dummy_dummy_i : std_logic_vector(31 downto 0);
rx_stat14_rx_buf_overflow_cnt_i : std_logic_vector(31 downto 0);
rx_stat15_rx_late_frames_cnt_i : std_logic_vector(31 downto 0);
rx_stat16_rx_timeout_frames_cnt_i : std_logic_vector(31 downto 0);
rx_stat17_rx_match_frames_cnt_i : std_logic_vector(31 downto 0);
end record; end record;
constant c_wr_streamers_in_registers_init_value: t_wr_streamers_in_registers := ( constant c_wr_streamers_in_registers_init_value: t_wr_streamers_in_registers := (
...@@ -63,7 +67,11 @@ package wr_streamers_wbgen2_pkg is ...@@ -63,7 +67,11 @@ package wr_streamers_wbgen2_pkg is
rx_stat12_rx_latency_acc_cnt_lsb_i => (others => '0'), rx_stat12_rx_latency_acc_cnt_lsb_i => (others => '0'),
rx_stat13_rx_latency_acc_cnt_msb_i => (others => '0'), rx_stat13_rx_latency_acc_cnt_msb_i => (others => '0'),
dbg_data_i => (others => '0'), dbg_data_i => (others => '0'),
dummy_dummy_i => (others => '0') dummy_dummy_i => (others => '0'),
rx_stat14_rx_buf_overflow_cnt_i => (others => '0'),
rx_stat15_rx_late_frames_cnt_i => (others => '0'),
rx_stat16_rx_timeout_frames_cnt_i => (others => '0'),
rx_stat17_rx_match_frames_cnt_i => (others => '0')
); );
-- Output registers (WB slave -> user design) -- Output registers (WB slave -> user design)
...@@ -102,6 +110,7 @@ package wr_streamers_wbgen2_pkg is ...@@ -102,6 +110,7 @@ package wr_streamers_wbgen2_pkg is
dbg_ctrl_mux_o : std_logic; dbg_ctrl_mux_o : std_logic;
dbg_ctrl_start_byte_o : std_logic_vector(7 downto 0); dbg_ctrl_start_byte_o : std_logic_vector(7 downto 0);
rstr_rst_sw_o : std_logic; rstr_rst_sw_o : std_logic;
rx_cfg6_rx_fixed_latency_timeout_o : std_logic_vector(27 downto 0);
end record; end record;
constant c_wr_streamers_out_registers_init_value: t_wr_streamers_out_registers := ( constant c_wr_streamers_out_registers_init_value: t_wr_streamers_out_registers := (
...@@ -137,7 +146,8 @@ package wr_streamers_wbgen2_pkg is ...@@ -137,7 +146,8 @@ package wr_streamers_wbgen2_pkg is
cfg_or_rx_fix_lat_o => '0', cfg_or_rx_fix_lat_o => '0',
dbg_ctrl_mux_o => '0', dbg_ctrl_mux_o => '0',
dbg_ctrl_start_byte_o => (others => '0'), dbg_ctrl_start_byte_o => (others => '0'),
rstr_rst_sw_o => '0' rstr_rst_sw_o => '0',
rx_cfg6_rx_fixed_latency_timeout_o => (others => '0')
); );
function "or" (left, right: t_wr_streamers_in_registers) return t_wr_streamers_in_registers; function "or" (left, right: t_wr_streamers_in_registers) return t_wr_streamers_in_registers;
...@@ -212,6 +222,10 @@ begin ...@@ -212,6 +222,10 @@ begin
tmp.rx_stat13_rx_latency_acc_cnt_msb_i := f_x_to_zero(left.rx_stat13_rx_latency_acc_cnt_msb_i) or f_x_to_zero(right.rx_stat13_rx_latency_acc_cnt_msb_i); tmp.rx_stat13_rx_latency_acc_cnt_msb_i := f_x_to_zero(left.rx_stat13_rx_latency_acc_cnt_msb_i) or f_x_to_zero(right.rx_stat13_rx_latency_acc_cnt_msb_i);
tmp.dbg_data_i := f_x_to_zero(left.dbg_data_i) or f_x_to_zero(right.dbg_data_i); tmp.dbg_data_i := f_x_to_zero(left.dbg_data_i) or f_x_to_zero(right.dbg_data_i);
tmp.dummy_dummy_i := f_x_to_zero(left.dummy_dummy_i) or f_x_to_zero(right.dummy_dummy_i); tmp.dummy_dummy_i := f_x_to_zero(left.dummy_dummy_i) or f_x_to_zero(right.dummy_dummy_i);
tmp.rx_stat14_rx_buf_overflow_cnt_i := f_x_to_zero(left.rx_stat14_rx_buf_overflow_cnt_i) or f_x_to_zero(right.rx_stat14_rx_buf_overflow_cnt_i);
tmp.rx_stat15_rx_late_frames_cnt_i := f_x_to_zero(left.rx_stat15_rx_late_frames_cnt_i) or f_x_to_zero(right.rx_stat15_rx_late_frames_cnt_i);
tmp.rx_stat16_rx_timeout_frames_cnt_i := f_x_to_zero(left.rx_stat16_rx_timeout_frames_cnt_i) or f_x_to_zero(right.rx_stat16_rx_timeout_frames_cnt_i);
tmp.rx_stat17_rx_match_frames_cnt_i := f_x_to_zero(left.rx_stat17_rx_match_frames_cnt_i) or f_x_to_zero(right.rx_stat17_rx_match_frames_cnt_i);
return tmp; return tmp;
end function; end function;
......
modules/wr_streamers/xrtx_streamers_stats.vhd
View file @ cdad3f33
...@@ -78,6 +78,7 @@ entity xrtx_streamers_stats is ...@@ -78,6 +78,7 @@ entity xrtx_streamers_stats is
rst_n_i : in std_logic; rst_n_i : in std_logic;
-- input signals from streamers -- input signals from streamers
sent_frame_i : in std_logic; sent_frame_i : in std_logic;
rcvd_frame_i : in std_logic; rcvd_frame_i : in std_logic;
lost_block_i : in std_logic; lost_block_i : in std_logic;
...@@ -86,6 +87,10 @@ entity xrtx_streamers_stats is ...@@ -86,6 +87,10 @@ entity xrtx_streamers_stats is
rcvd_latency_i : in std_logic_vector(27 downto 0); rcvd_latency_i : in std_logic_vector(27 downto 0);
rcvd_latency_valid_i : in std_logic; rcvd_latency_valid_i : in std_logic;
rx_stat_match_p1_i : in std_logic;
rx_stat_late_p1_i : in std_logic;
rx_stat_timeout_p1_i : in std_logic;
clk_ref_i : in std_logic; clk_ref_i : in std_logic;
tm_time_valid_i : in std_logic := '0'; tm_time_valid_i : in std_logic := '0';
tm_tai_i : in std_logic_vector(39 downto 0) := x"0000000000"; tm_tai_i : in std_logic_vector(39 downto 0) := x"0000000000";
...@@ -103,6 +108,10 @@ entity xrtx_streamers_stats is ...@@ -103,6 +108,10 @@ entity xrtx_streamers_stats is
rcvd_frame_cnt_o : out std_logic_vector(g_cnt_width-1 downto 0); rcvd_frame_cnt_o : out std_logic_vector(g_cnt_width-1 downto 0);
lost_frame_cnt_o : out std_logic_vector(g_cnt_width-1 downto 0); lost_frame_cnt_o : out std_logic_vector(g_cnt_width-1 downto 0);
lost_block_cnt_o : out std_logic_vector(g_cnt_width-1 downto 0); lost_block_cnt_o : out std_logic_vector(g_cnt_width-1 downto 0);
rx_stat_match_cnt_o : out std_logic_vector(g_cnt_width-1 downto 0);
rx_stat_late_cnt_o : out std_logic_vector(g_cnt_width-1 downto 0);
rx_stat_timeout_cnt_o : out std_logic_vector(g_cnt_width-1 downto 0);
-- output statistics: latency -- output statistics: latency
latency_cnt_o : out std_logic_vector(g_cnt_width-1 downto 0); latency_cnt_o : out std_logic_vector(g_cnt_width-1 downto 0);
latency_acc_overflow_o : out std_logic; latency_acc_overflow_o : out std_logic;
...@@ -121,11 +130,14 @@ architecture rtl of xrtx_streamers_stats is ...@@ -121,11 +130,14 @@ architecture rtl of xrtx_streamers_stats is
signal reset_time_tai : std_logic_vector(39 downto 0); signal reset_time_tai : std_logic_vector(39 downto 0);
signal reset_time_cycles : std_logic_vector(27 downto 0); signal reset_time_cycles : std_logic_vector(27 downto 0);
signal sent_frame_cnt : unsigned(g_cnt_width-1 downto 0); -- signal sent_frame_cnt : unsigned(g_cnt_width-1 downto 0);
signal rcvd_frame_cnt : unsigned(g_cnt_width-1 downto 0); -- signal rcvd_frame_cnt : unsigned(g_cnt_width-1 downto 0);
signal lost_frame_cnt : unsigned(g_cnt_width-1 downto 0); -- signal lost_frame_cnt : unsigned(g_cnt_width-1 downto 0);
signal lost_block_cnt : unsigned(g_cnt_width-1 downto 0); -- signal lost_block_cnt : unsigned(g_cnt_width-1 downto 0);
signal latency_cnt : unsigned(g_cnt_width-1 downto 0); signal rx_stat_match_cnt_out : std_logic_vector(g_cnt_width-1 downto 0);
signal rx_stat_timeout_cnt_out : std_logic_vector(g_cnt_width-1 downto 0);
signal rx_stat_late_cnt_out : std_logic_vector(g_cnt_width-1 downto 0);
-- signal latency_cnt : unsigned(g_cnt_width-1 downto 0);
signal latency_max : std_logic_vector(27 downto 0); signal latency_max : std_logic_vector(27 downto 0);
signal latency_min : std_logic_vector(27 downto 0); signal latency_min : std_logic_vector(27 downto 0);
...@@ -136,6 +148,11 @@ architecture rtl of xrtx_streamers_stats is ...@@ -136,6 +148,11 @@ architecture rtl of xrtx_streamers_stats is
signal rcvd_frame_cnt_out : std_logic_vector(g_cnt_width-1 downto 0); signal rcvd_frame_cnt_out : std_logic_vector(g_cnt_width-1 downto 0);
signal lost_frame_cnt_out : std_logic_vector(g_cnt_width-1 downto 0); signal lost_frame_cnt_out : std_logic_vector(g_cnt_width-1 downto 0);
signal lost_block_cnt_out : std_logic_vector(g_cnt_width-1 downto 0); signal lost_block_cnt_out : std_logic_vector(g_cnt_width-1 downto 0);
signal rx_match_frame_cnt_out : std_logic_vector(g_cnt_width-1 downto 0);
signal rx_late_frame_cnt_out : std_logic_vector(g_cnt_width-1 downto 0);
signal rx_timeout_frame_cnt_out : std_logic_vector(g_cnt_width-1 downto 0);
signal latency_cnt_out : std_logic_vector(g_cnt_width-1 downto 0); signal latency_cnt_out : std_logic_vector(g_cnt_width-1 downto 0);
signal latency_acc_overflow_out : std_logic; signal latency_acc_overflow_out : std_logic;
signal latency_acc_out : std_logic_vector(g_acc_width-1 downto 0); signal latency_acc_out : std_logic_vector(g_acc_width-1 downto 0);
...@@ -245,12 +262,20 @@ begin ...@@ -245,12 +262,20 @@ begin
lost_frames_cnt_i => lost_frames_cnt_i, lost_frames_cnt_i => lost_frames_cnt_i,
rcvd_latency_i => rcvd_latency_i, rcvd_latency_i => rcvd_latency_i,
rcvd_latency_valid_i => rcvd_latency_valid_i, rcvd_latency_valid_i => rcvd_latency_valid_i,
rx_stat_timeout_p1_i => rx_stat_timeout_p1_i,
rx_stat_match_p1_i => rx_stat_match_p1_i,
rx_stat_late_p1_i => rx_stat_late_p1_i,
tm_time_valid_i => tm_time_valid_i, tm_time_valid_i => tm_time_valid_i,
snapshot_ena_i => snapshot_ena, snapshot_ena_i => snapshot_ena,
reset_stats_i => reset_stats, reset_stats_i => reset_stats,
rcvd_frame_cnt_o => rcvd_frame_cnt_out, rcvd_frame_cnt_o => rcvd_frame_cnt_out,
lost_frame_cnt_o => lost_frame_cnt_out, lost_frame_cnt_o => lost_frame_cnt_out,
lost_block_cnt_o => lost_block_cnt_out, lost_block_cnt_o => lost_block_cnt_out,
rx_stat_match_cnt_o => rx_stat_match_cnt_out,
rx_stat_late_cnt_o => rx_stat_late_cnt_out,
rx_stat_timeout_cnt_o => rx_stat_timeout_cnt_out,
latency_cnt_o => latency_cnt_out, latency_cnt_o => latency_cnt_out,
latency_acc_overflow_o => latency_acc_overflow_out, latency_acc_overflow_o => latency_acc_overflow_out,
latency_acc_o => latency_acc_out, latency_acc_o => latency_acc_out,
...@@ -279,6 +304,12 @@ begin ...@@ -279,6 +304,12 @@ begin
latency_acc_o <= latency_acc_out; latency_acc_o <= latency_acc_out;
latency_cnt_o <= latency_cnt_out; latency_cnt_o <= latency_cnt_out;
latency_acc_overflow_o <= latency_acc_overflow_out; latency_acc_overflow_o <= latency_acc_overflow_out;
rx_stat_timeout_cnt_o <= rx_stat_timeout_cnt_out;
rx_stat_late_cnt_o <= rx_stat_late_cnt_out;
rx_stat_match_cnt_o <= rx_stat_match_cnt_out;
-- fixme: add rx late/miss/match stats to SNMP array
------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------
-- SNMP remote output -- SNMP remote output
......
modules/wr_streamers/xrx_streamer.vhd
View file @ cdad3f33
...@@ -122,6 +122,12 @@ entity xrx_streamer is ...@@ -122,6 +122,12 @@ entity xrx_streamer is
rx_data_o : out std_logic_vector(g_data_width-1 downto 0); rx_data_o : out std_logic_vector(g_data_width-1 downto 0);
-- 1 indicted that rx_data_o is outputting a valid data word. -- 1 indicted that rx_data_o is outputting a valid data word.
rx_valid_o : out std_logic; rx_valid_o : out std_logic;
-- 1 indicates the frame has been reproduced later than its desired fixed latency
rx_late_o : out std_logic;
-- 1 indicates the frame has been reproduced earlier than its desired fixed
-- latency due to the RX latency timeout
rx_timeout_o : out std_logic;
-- Synchronous data request input: when 1, the streamer may output another -- Synchronous data request input: when 1, the streamer may output another
-- data word in the subsequent clock cycle. -- data word in the subsequent clock cycle.
rx_dreq_i : in std_logic; rx_dreq_i : in std_logic;
...@@ -140,7 +146,10 @@ entity xrx_streamer is ...@@ -140,7 +146,10 @@ entity xrx_streamer is
-- 1 when the latency on rx_latency_o is valid. -- 1 when the latency on rx_latency_o is valid.
rx_latency_valid_o : out std_logic; rx_latency_valid_o : out std_logic;
-- pulse when a frame was dropped due to buffer overflow -- pulse when a frame was dropped due to buffer overflow
rx_overflow_p1_o : out std_logic; rx_stat_overflow_p1_o : out std_logic;
rx_stat_match_p1_o : out std_logic;
rx_stat_late_p1_o : out std_logic;
rx_stat_timeout_p1_o : out std_logic;
-- received streamer frame (counts all frames, corrupted and not) -- received streamer frame (counts all frames, corrupted and not)
rx_frame_p1_o : out std_logic; rx_frame_p1_o : out std_logic;
-- configuration -- configuration
...@@ -345,6 +354,11 @@ begin -- rtl ...@@ -345,6 +354,11 @@ begin -- rtl
rx_data_o => rx_data_o, rx_data_o => rx_data_o,
rx_valid_o => rx_valid_o, rx_valid_o => rx_valid_o,
rx_dreq_i => rx_dreq_i, rx_dreq_i => rx_dreq_i,
rx_late_o => rx_late_o,
rx_timeout_o => rx_timeout_o,
stat_match_p1_o => rx_stat_match_p1_o,
stat_late_p1_o => rx_stat_late_p1_o,
stat_timeout_p1_o => rx_stat_timeout_p1_o,
rx_streamer_cfg_i => rx_streamer_cfg_i); rx_streamer_cfg_i => rx_streamer_cfg_i);
......
modules/wr_streamers/xrx_streamers_stats.vhd
View file @ cdad3f33
...@@ -65,14 +65,23 @@ entity xrx_streamers_stats is ...@@ -65,14 +65,23 @@ entity xrx_streamers_stats is
rcvd_latency_valid_i : in std_logic; rcvd_latency_valid_i : in std_logic;
tm_time_valid_i : in std_logic; tm_time_valid_i : in std_logic;
snapshot_ena_i : in std_logic := '0'; snapshot_ena_i : in std_logic := '0';
reset_stats_i : in std_logic; reset_stats_i : in std_logic;
rx_stat_match_p1_i : in std_logic;
rx_stat_late_p1_i : in std_logic;
rx_stat_timeout_p1_i : in std_logic;
----------------------- statistics ---------------------------------------- ----------------------- statistics ----------------------------------------
-- output statistics: tx/rx counters -- output statistics: tx/rx counters
rcvd_frame_cnt_o : out std_logic_vector(g_cnt_width-1 downto 0); rcvd_frame_cnt_o : out std_logic_vector(g_cnt_width-1 downto 0);
lost_frame_cnt_o : out std_logic_vector(g_cnt_width-1 downto 0); lost_frame_cnt_o : out std_logic_vector(g_cnt_width-1 downto 0);
lost_block_cnt_o : out std_logic_vector(g_cnt_width-1 downto 0); lost_block_cnt_o : out std_logic_vector(g_cnt_width-1 downto 0);
-- output statistics: latency rx_stat_match_cnt_o : out std_logic_vector(g_cnt_width-1 downto 0);
rx_stat_late_cnt_o : out std_logic_vector(g_cnt_width-1 downto 0);
rx_stat_timeout_cnt_o : out std_logic_vector(g_cnt_width-1 downto 0);
-- output statistics: latency
latency_cnt_o : out std_logic_vector(g_cnt_width-1 downto 0); latency_cnt_o : out std_logic_vector(g_cnt_width-1 downto 0);
latency_acc_overflow_o : out std_logic; latency_acc_overflow_o : out std_logic;
latency_acc_o : out std_logic_vector(g_acc_width-1 downto 0); latency_acc_o : out std_logic_vector(g_acc_width-1 downto 0);
...@@ -88,6 +97,9 @@ architecture rtl of xrx_streamers_stats is ...@@ -88,6 +97,9 @@ architecture rtl of xrx_streamers_stats is
signal rcvd_frame_cnt : unsigned(g_cnt_width-1 downto 0); signal rcvd_frame_cnt : unsigned(g_cnt_width-1 downto 0);
signal lost_frame_cnt : unsigned(g_cnt_width-1 downto 0); signal lost_frame_cnt : unsigned(g_cnt_width-1 downto 0);
signal lost_block_cnt : unsigned(g_cnt_width-1 downto 0); signal lost_block_cnt : unsigned(g_cnt_width-1 downto 0);
signal rx_stat_late_cnt : unsigned(g_cnt_width-1 downto 0);
signal rx_stat_match_cnt : unsigned(g_cnt_width-1 downto 0);
signal rx_stat_timeout_cnt : unsigned(g_cnt_width-1 downto 0);
signal latency_cnt : unsigned(g_cnt_width-1 downto 0); signal latency_cnt : unsigned(g_cnt_width-1 downto 0);
signal latency_max : std_logic_vector(27 downto 0); signal latency_max : std_logic_vector(27 downto 0);
...@@ -100,6 +112,9 @@ architecture rtl of xrx_streamers_stats is ...@@ -100,6 +112,9 @@ architecture rtl of xrx_streamers_stats is
signal lost_frame_cnt_d1 : unsigned(g_cnt_width-1 downto 0); signal lost_frame_cnt_d1 : unsigned(g_cnt_width-1 downto 0);
signal lost_block_cnt_d1 : unsigned(g_cnt_width-1 downto 0); signal lost_block_cnt_d1 : unsigned(g_cnt_width-1 downto 0);
signal latency_cnt_d1 : unsigned(g_cnt_width-1 downto 0); signal latency_cnt_d1 : unsigned(g_cnt_width-1 downto 0);
signal rx_stat_late_cnt_d1 : unsigned(g_cnt_width-1 downto 0);
signal rx_stat_match_cnt_d1 : unsigned(g_cnt_width-1 downto 0);
signal rx_stat_timeout_cnt_d1 : unsigned(g_cnt_width-1 downto 0);
signal latency_max_d1 : std_logic_vector(27 downto 0); signal latency_max_d1 : std_logic_vector(27 downto 0);
signal latency_min_d1 : std_logic_vector(27 downto 0); signal latency_min_d1 : std_logic_vector(27 downto 0);
...@@ -121,6 +136,10 @@ begin ...@@ -121,6 +136,10 @@ begin
rcvd_frame_cnt <= (others => '0'); rcvd_frame_cnt <= (others => '0');
lost_frame_cnt <= (others => '0'); lost_frame_cnt <= (others => '0');
lost_block_cnt <= (others => '0'); lost_block_cnt <= (others => '0');
rx_stat_timeout_cnt <= (others => '0');
rx_stat_late_cnt <= (others => '0');
rx_stat_match_cnt <= (others => '0');
else else
-- count received frames -- count received frames
if(rcvd_frame_i = '1') then if(rcvd_frame_i = '1') then
...@@ -134,6 +153,19 @@ begin ...@@ -134,6 +153,19 @@ begin
if(lost_block_i = '1') then if(lost_block_i = '1') then
lost_block_cnt <= lost_block_cnt + 1; lost_block_cnt <= lost_block_cnt + 1;
end if; end if;
-- count fixed latency on-time frames
if(rx_stat_match_p1_i = '1') then
rx_stat_match_cnt <= rx_stat_match_cnt + 1;
end if;
-- count fixed latency late frames
if(rx_stat_late_p1_i = '1') then
rx_stat_late_cnt <= rx_stat_late_cnt + 1;
end if;
-- count fixed latency timed-out frames
if(rx_stat_timeout_p1_i = '1') then
rx_stat_timeout_cnt <= rx_stat_timeout_cnt + 1;
end if;
end if; end if;
end if; end if;
end process; end process;
...@@ -198,6 +230,10 @@ begin ...@@ -198,6 +230,10 @@ begin
lost_block_cnt_d1 <= lost_block_cnt; lost_block_cnt_d1 <= lost_block_cnt;
latency_cnt_d1 <= latency_cnt; latency_cnt_d1 <= latency_cnt;
rx_stat_timeout_cnt_d1 <= rx_stat_timeout_cnt;
rx_stat_match_cnt_d1 <= rx_stat_match_cnt;
rx_stat_late_cnt_d1 <= rx_stat_late_cnt;
latency_max_d1 <= latency_max; latency_max_d1 <= latency_max;
latency_min_d1 <= latency_min; latency_min_d1 <= latency_min;
latency_acc_d1 <= latency_acc; latency_acc_d1 <= latency_acc;
...@@ -211,6 +247,13 @@ begin ...@@ -211,6 +247,13 @@ begin
------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------
-- snapshot or current value -- snapshot or current value
------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------
rx_stat_match_cnt_o <= std_logic_vector(rx_stat_match_cnt_d1) when (snapshot_ena_d1 = '1') else
std_logic_vector(rx_stat_match_cnt);
rx_stat_late_cnt_o <= std_logic_vector(rx_stat_late_cnt_d1) when (snapshot_ena_d1 = '1') else
std_logic_vector(rx_stat_late_cnt);
rx_stat_timeout_cnt_o <= std_logic_vector(rx_stat_timeout_cnt_d1) when (snapshot_ena_d1 = '1') else
std_logic_vector(rx_stat_timeout_cnt);
rcvd_frame_cnt_o <= std_logic_vector(rcvd_frame_cnt_d1) when (snapshot_ena_d1 = '1') else rcvd_frame_cnt_o <= std_logic_vector(rcvd_frame_cnt_d1) when (snapshot_ena_d1 = '1') else
std_logic_vector(rcvd_frame_cnt); std_logic_vector(rcvd_frame_cnt);
lost_frame_cnt_o <= std_logic_vector(lost_frame_cnt_d1) when (snapshot_ena_d1 = '1') else lost_frame_cnt_o <= std_logic_vector(lost_frame_cnt_d1) when (snapshot_ena_d1 = '1') else
......
modules/wr_streamers/xwr_streamers.vhd
View file @ cdad3f33
...@@ -161,6 +161,9 @@ entity xwr_streamers is ...@@ -161,6 +161,9 @@ entity xwr_streamers is
-- data word in the subsequent clock cycle. -- data word in the subsequent clock cycle.
rx_dreq_i : in std_logic; rx_dreq_i : in std_logic;
rx_late_o : out std_logic;
rx_timeout_o : out std_logic;
--------------------------------------------------------------------------- ---------------------------------------------------------------------------
-- WRC Timing interface, used for latency measurement -- WRC Timing interface, used for latency measurement
--------------------------------------------------------------------------- ---------------------------------------------------------------------------
...@@ -194,11 +197,12 @@ architecture rtl of xwr_streamers is ...@@ -194,11 +197,12 @@ architecture rtl of xwr_streamers is
signal to_wb : t_wr_streamers_in_registers; signal to_wb : t_wr_streamers_in_registers;
signal from_wb : t_wr_streamers_out_registers; signal from_wb : t_wr_streamers_out_registers;
signal dbg_word : std_logic_vector(31 downto 0); signal dbg_word : std_logic_vector(31 downto 0);
signal start_bit : std_logic_vector(from_wb.dbg_ctrl_start_byte_o'length-1+3 downto 0); signal start_bit : std_logic_vector(from_wb.dbg_ctrl_start_byte_o'length-1+3 downto 0);
signal rx_data : std_logic_vector(g_rx_streamer_params.data_width-1 downto 0); signal rx_data : std_logic_vector(g_rx_streamer_params.data_width-1 downto 0);
signal wb_regs_slave_in : t_wishbone_slave_in; signal wb_regs_slave_in : t_wishbone_slave_in;
signal wb_regs_slave_out : t_wishbone_slave_out; signal wb_regs_slave_out : t_wishbone_slave_out;
signal tx_frame : std_logic; signal tx_frame : std_logic;
signal reset_time_tai : std_logic_vector(39 downto 0); signal reset_time_tai : std_logic_vector(39 downto 0);
signal latency_acc : std_logic_vector(g_stats_acc_width-1 downto 0); signal latency_acc : std_logic_vector(g_stats_acc_width-1 downto 0);
...@@ -207,8 +211,12 @@ architecture rtl of xwr_streamers is ...@@ -207,8 +211,12 @@ architecture rtl of xwr_streamers is
signal rcvd_frame_cnt_out : std_logic_vector(g_stats_cnt_width-1 downto 0); signal rcvd_frame_cnt_out : std_logic_vector(g_stats_cnt_width-1 downto 0);
signal lost_frame_cnt_out : std_logic_vector(g_stats_cnt_width-1 downto 0); signal lost_frame_cnt_out : std_logic_vector(g_stats_cnt_width-1 downto 0);
signal lost_block_cnt_out : std_logic_vector(g_stats_cnt_width-1 downto 0); signal lost_block_cnt_out : std_logic_vector(g_stats_cnt_width-1 downto 0);
signal rx_stat_match_cnt : std_logic_vector(g_stats_cnt_width-1 downto 0);
signal rx_stat_timeout_cnt : std_logic_vector(g_stats_cnt_width-1 downto 0);
signal rx_stat_late_cnt : std_logic_vector(g_stats_cnt_width-1 downto 0);
signal rx_valid : std_logic; signal rx_valid : std_logic;
signal rx_latency_valid : std_logic; signal rx_latency_valid : std_logic;
signal rx_latency : std_logic_vector(27 downto 0); signal rx_latency : std_logic_vector(27 downto 0);
signal rx_lost_frames : std_logic; signal rx_lost_frames : std_logic;
...@@ -216,6 +224,11 @@ architecture rtl of xwr_streamers is ...@@ -216,6 +224,11 @@ architecture rtl of xwr_streamers is
signal rx_lost_blocks : std_logic; signal rx_lost_blocks : std_logic;
signal rx_frame : std_logic; signal rx_frame : std_logic;
signal rx_stat_match_p1 : std_logic;
signal rx_stat_late_p1 : std_logic;
signal rx_stat_timeout_p1 : std_logic;
signal tx_streamer_cfg : t_tx_streamer_cfg; signal tx_streamer_cfg : t_tx_streamer_cfg;
signal rx_streamer_cfg : t_rx_streamer_cfg; signal rx_streamer_cfg : t_rx_streamer_cfg;
...@@ -294,9 +307,15 @@ begin ...@@ -294,9 +307,15 @@ begin
rx_data_o => rx_data, rx_data_o => rx_data,
rx_valid_o => rx_valid, rx_valid_o => rx_valid,
rx_dreq_i => rx_dreq_i, rx_dreq_i => rx_dreq_i,
rx_late_o => rx_late_o,
rx_timeout_o => rx_timeout_o,
rx_lost_p1_o => rx_lost_blocks, rx_lost_p1_o => rx_lost_blocks,
rx_lost_frames_p1_o => rx_lost_frames, rx_lost_frames_p1_o => rx_lost_frames,
rx_lost_frames_cnt_o => rx_lost_frames_cnt, rx_lost_frames_cnt_o => rx_lost_frames_cnt,
rx_stat_match_p1_o => rx_stat_match_p1,
rx_stat_late_p1_o => rx_stat_late_p1,
rx_stat_timeout_p1_o => rx_stat_timeout_p1,
rx_latency_o => rx_latency, rx_latency_o => rx_latency,
rx_latency_valid_o => rx_latency_valid, rx_latency_valid_o => rx_latency_valid,
rx_frame_p1_o => rx_frame, rx_frame_p1_o => rx_frame,
...@@ -321,6 +340,7 @@ begin ...@@ -321,6 +340,7 @@ begin
g_clk_ref_rate => g_clk_ref_rate g_clk_ref_rate => g_clk_ref_rate
) )
port map( port map(
clk_i => clk_sys_i, clk_i => clk_sys_i,
rst_n_i => rst_n_i, rst_n_i => rst_n_i,
sent_frame_i => tx_frame, sent_frame_i => tx_frame,
...@@ -342,6 +362,13 @@ begin ...@@ -342,6 +362,13 @@ begin
rcvd_frame_cnt_o => rcvd_frame_cnt_out, rcvd_frame_cnt_o => rcvd_frame_cnt_out,
lost_frame_cnt_o => lost_frame_cnt_out, lost_frame_cnt_o => lost_frame_cnt_out,
lost_block_cnt_o => lost_block_cnt_out, lost_block_cnt_o => lost_block_cnt_out,
rx_stat_timeout_cnt_o => rx_stat_timeout_cnt,
rx_stat_match_cnt_o => rx_stat_match_cnt,
rx_stat_late_cnt_o => rx_stat_late_cnt,
rx_stat_match_p1_i => rx_stat_match_p1,
rx_stat_late_p1_i => rx_stat_late_p1,
rx_stat_timeout_p1_i => rx_stat_timeout_p1,
latency_cnt_o => latency_cnt, latency_cnt_o => latency_cnt,
latency_acc_o => latency_acc, latency_acc_o => latency_acc,
latency_max_o => to_wb.rx_stat0_rx_latency_max_i, latency_max_o => to_wb.rx_stat0_rx_latency_max_i,
...@@ -372,6 +399,11 @@ begin ...@@ -372,6 +399,11 @@ begin
to_wb.rx_stat12_rx_latency_acc_cnt_lsb_i <= latency_cnt (31 downto 0); to_wb.rx_stat12_rx_latency_acc_cnt_lsb_i <= latency_cnt (31 downto 0);
to_wb.rx_stat13_rx_latency_acc_cnt_msb_i(c_cw-32-1 downto 0) <= latency_cnt (c_cw-1 downto 32); to_wb.rx_stat13_rx_latency_acc_cnt_msb_i(c_cw-32-1 downto 0) <= latency_cnt (c_cw-1 downto 32);
to_wb.rx_stat15_rx_late_frames_cnt_i <= rx_stat_late_cnt(31 downto 0);
to_wb.rx_stat16_rx_timeout_frames_cnt_i <= rx_stat_timeout_cnt(31 downto 0);
to_wb.rx_stat17_rx_match_frames_cnt_i <= rx_stat_match_cnt(31 downto 0);
rx_data_o <= rx_data; rx_data_o <= rx_data;
rx_valid_o <= rx_valid; rx_valid_o <= rx_valid;
...@@ -492,6 +524,8 @@ begin ...@@ -492,6 +524,8 @@ begin
rx_streamer_cfg_i.filter_remote; rx_streamer_cfg_i.filter_remote;
rx_streamer_cfg.fixed_latency <= from_wb.rx_cfg5_fixed_latency_o when (from_wb.cfg_or_rx_fix_lat_o='1') else rx_streamer_cfg.fixed_latency <= from_wb.rx_cfg5_fixed_latency_o when (from_wb.cfg_or_rx_fix_lat_o='1') else
rx_streamer_cfg_i.fixed_latency; rx_streamer_cfg_i.fixed_latency;
rx_streamer_cfg.fixed_latency_timeout <= from_wb.rx_cfg6_rx_fixed_latency_timeout_o when (from_wb.cfg_or_rx_fix_lat_o = '1') else
rx_streamer_cfg_i.fixed_latency_timeout;
rx_streamer_cfg.sw_reset <= from_wb.rstr_rst_sw_o; rx_streamer_cfg.sw_reset <= from_wb.rstr_rst_sw_o;
......
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