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White Rabbit core collection
Commit ceaf5c62 authored by Wesley W. Terpstra's avatar Wesley W. Terpstra
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Added PCIe to the project

parent 7df1693d
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Showing with 37 additions and 5 deletions
syn/gsi_scu/wr_core_demo/scu.qsf
View file @ ceaf5c62
......@@ -27,7 +27,7 @@ set_global_assignment -name DEVICE EP2AGX125EF29C5
set_global_assignment -name TOP_LEVEL_ENTITY scu_top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 11.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:00:25 FEBRUARY 13, 2012"
set_global_assignment -name LAST_QUARTUS_VERSION 11.1
set_global_assignment -name LAST_QUARTUS_VERSION "11.1 SP1"
set_global_assignment -name SEARCH_PATH ./
set_global_assignment -name SEARCH_PATH "pci_express_compiler-library/"
set_global_assignment -name SEARCH_PATH "pci_megacore-library/"
......@@ -139,6 +139,10 @@ set_location_assignment PIN_Y1 -to sfp1_mod2
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sfp1_mod0
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sfp1_mod1
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sfp1_mod2
set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_pcie/altera_reconfig.vhd"
set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_pcie/altera_pcie_serdes.vhd"
set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_pcie/altera_pcie_core.vhd"
set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_pcie/altera_pcie.vhd"
set_global_assignment -name VHDL_FILE ../../../modules/wr_softpll_ng/wr_softpll_ng.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wr_softpll_ng/spll_wbgen2_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wr_softpll_ng/spll_wb_slave.vhd
......@@ -336,4 +340,8 @@ set_global_assignment -name VHDL_FILE ../../../top/gsi_scu/wr_core_demo/lpc_uart
set_global_assignment -name VHDL_FILE ../../../top/gsi_scu/wr_core_demo/uart/slib_input_filter.vhd
set_global_assignment -name VERILOG_FILE ../../../top/gsi_scu/wr_core_demo/serirq_slave.v
set_global_assignment -name VERILOG_FILE ../../../top/gsi_scu/wr_core_demo/serirq_defines.v
set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_pcie/pcie_altera.vhd"
set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_pcie/pcie_tlp.vhd"
set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_pcie/pcie_wb.vhd"
set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_pcie/pcie_wb_pkg.vhd"
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
top/gsi_scu/wr_core_demo/scu_top.vhd
View file @ ceaf5c62
......@@ -11,7 +11,7 @@ library work;
use work.wishbone_pkg.all;
use work.wb_cores_pkg_gsi.all;
use work.xwr_eca_pkg.all;
use work.pcie_wb_pkg.all;
entity scu_top is
port
......@@ -29,7 +29,14 @@ entity scu_top is
uart_txd_o : out std_logic_vector(1 downto 0);
serial_to_cb_o : out std_logic;
-----------------------------------------
-- PCI express pins
-----------------------------------------
pcie_refclk_i : in std_logic;
pcie_rstn_i : in std_logic;
pcie_rx_i : in std_logic;
pcie_tx_o : out std_logic;
------------------------------------------------------------------------
-- WR DAC signals
......@@ -314,7 +321,7 @@ architecture rtl of scu_top is
-- Top crossbar layout
constant c_slaves : natural := 3;
constant c_masters : natural := 1;
constant c_masters : natural := 2;
constant c_test_dpram_size : natural := 2048;
constant c_layout : t_sdwb_device_array(c_slaves-1 downto 0) :=
(0 => f_sdwb_set_address(f_xwb_dpram(c_test_dpram_size), x"00000000"),
......@@ -431,6 +438,8 @@ architecture rtl of scu_top is
signal sfp_scl_o: std_logic;
signal sfp_det_i: std_logic;
signal pcie_rx, pcie_tx : std_logic_vector(3 downto 0);
begin
......@@ -643,7 +652,22 @@ begin
snk_i => mb_snk_in,
master_o => cbar_slave_i(0),
master_i => cbar_slave_o(0));
pcie_tx_o <= pcie_tx(0);
pcie_rx <= "000" & pcie_rx_i;
PCIe : pcie_wb
port map(
clk125_i => pllout_clk_sys,
cal_clk50_i => clk_reconf,
rstn_i => nreset,
pcie_refclk_i => pcie_refclk_i,
pcie_rstn_i => pcie_rstn_i,
pcie_rx_i => pcie_rx,
pcie_tx_o => pcie_tx,
wb_clk => pllout_clk_sys,
master_o => cbar_slave_i(1),
master_i => cbar_slave_o(1));
triggers <= '0' & lemo_io2 & pio_reg(0 downto 0) & pps;
TLU : wb_timestamp_latch
......
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