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White Rabbit core collection
Commit d17e7b82 authored by Stefan Rauch's avatar Stefan Rauch Committed by Wesley W. Terpstra
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fixed pll comments

parent 19251141
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Showing with 8 additions and 8 deletions
top/gsi_scu/wr_core_demo/scu_top.vhd
View file @ d17e7b82
......@@ -375,14 +375,14 @@ begin
dmtd_clk_pll_inst : dmtd_clk_pll port map (
inclk0 => clk_20m_vcxo_i, -- 20Mhz
c0 => pllout_clk_dmtd -- 125Mhz
inclk0 => clk_20m_vcxo_i, -- 20MHz
c0 => pllout_clk_dmtd -- 62.5Mhz
);
sys_pll_inst : sys_pll port map (
inclk0 => L_CLKp, -- 125Mhz
c0 => pllout_clk_sys, -- 125Mhy sys clk
c1 => clk_reconf, -- 40Mhz for reconfig block
inclk0 => L_CLKp, -- 125MHz
c0 => pllout_clk_sys, -- 62.5MHz sys clk
c1 => clk_reconf, -- 50MHz for reconfig block
locked => open
);
......
top/gsi_scu2/wr_core_demo/scu_top.vhd
View file @ d17e7b82
......@@ -384,13 +384,13 @@ begin
dmtd_clk_pll_inst : dmtd_clk_pll port map (
inclk0 => clk_20m_vcxo_i, -- 20Mhz
c0 => pllout_clk_dmtd -- 125Mhz
c0 => pllout_clk_dmtd -- 62.5Mhz
);
sys_pll_inst : sys_pll port map (
inclk0 => L_CLKp, -- 125Mhz
c0 => pllout_clk_sys, -- 125Mhy sys clk
c1 => clk_reconf, -- 40Mhz for reconfig block
c0 => pllout_clk_sys, -- 62.5Mhy sys clk
c1 => clk_reconf, -- 50Mhz for reconfig block
locked => open
);
......
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