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Commit d45e32f4 authored by A. Hahn's avatar A. Hahn
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wr_arria10_e3p1_atx_pll: changed output frequency (fcmu = fatx)

parent ab32298e
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platform/altera/wr_arria10_e3p1_phy/wr_arria10_e3p1_atx_pll/.qsys_edit/preferences.xml
View file @ d45e32f4
......@@ -7,8 +7,8 @@
<irq preferredWidth="34" />
</columns>
</systemtable>
<library expandedCategories="Library,Project" />
<window width="1403" height="1046" x="1911" y="1260" />
<library expandedCategories="Project,Library" />
<window width="1492" height="1098" x="1677" y="1247" />
<generation
path=""
synthesis="VHDL"
......
platform/altera/wr_arria10_e3p1_phy/wr_arria10_e3p1_atx_pll/.qsys_edit/wr_arria10_e3p1_atx_pll.xml
View file @ d45e32f4
......@@ -740,7 +740,7 @@
<delegate id="delegate_CommonDockStationFactory">
<root>true</root>
<content delegate="flap dock">
<window auto="true" direction="SOUTH"/>
<window auto="true" direction="NORTH"/>
<placeholders>
<version>0</version>
<format>dock.PlaceholderList</format>
......@@ -771,7 +771,7 @@
<delegate id="delegate_CommonDockStationFactory">
<root>true</root>
<content delegate="flap dock">
<window auto="true" direction="SOUTH"/>
<window auto="true" direction="NORTH"/>
<placeholders>
<version>0</version>
<format>dock.PlaceholderList</format>
......@@ -868,7 +868,7 @@
</placeholders>
</leaf>
</node>
<leaf id="2" nodeId="1375899667061">
<leaf id="3" nodeId="1375899667061">
<placeholders>
<placeholder>dock.single.Connections</placeholder>
<placeholder>dock.single.System\ Contents</placeholder>
......@@ -936,7 +936,7 @@
</placeholder-map>
</leaf>
</node>
<leaf id="1" nodeId="1372710005745">
<leaf id="0" nodeId="1372710005745">
<placeholders>
<placeholder>dock.single.Messages</placeholder>
<placeholder>dock.single.Generation\ Messages</placeholder>
......@@ -958,7 +958,7 @@
</leaf>
</node>
<node nodeId="1375899673461" orientation="VERTICAL" divider="0.49909584086799275">
<leaf id="0" nodeId="1372710005741">
<leaf id="2" nodeId="1372710005741">
<placeholders>
<placeholder>dock.single.Element\ Docs</placeholder>
<placeholder>dock.single.Details</placeholder>
......@@ -969,7 +969,7 @@
<format>dock.PlaceholderList</format>
</placeholder-map>
</leaf>
<leaf id="3" nodeId="1372710005743">
<leaf id="1" nodeId="1372710005743">
<placeholders>
<placeholder>dock.single.Presets</placeholder>
<placeholder>dock.single.Device\ Family</placeholder>
......@@ -1001,6 +1001,26 @@
</layout>
</adjacent>
<children ignore="false">
<child>
<layout factory="predefined" placeholder="dock.single.Messages">
<replacement id="dockablesingle Messages"/>
<delegate id="delegate_ccontrol backup factory id">
<id>Messages</id>
<area/>
</delegate>
</layout>
<children ignore="false"/>
</child>
<child>
<layout factory="predefined" placeholder="dock.single.Presets">
<replacement id="dockablesingle Presets"/>
<delegate id="delegate_ccontrol backup factory id">
<id>Presets</id>
<area/>
</delegate>
</layout>
<children ignore="false"/>
</child>
<child>
<layout factory="delegate_StackDockStationFactory">
<selected>0</selected>
......@@ -1060,16 +1080,6 @@
</child>
</children>
</child>
<child>
<layout factory="predefined" placeholder="dock.single.Messages">
<replacement id="dockablesingle Messages"/>
<delegate id="delegate_ccontrol backup factory id">
<id>Messages</id>
<area/>
</delegate>
</layout>
<children ignore="false"/>
</child>
<child>
<layout factory="predefined" placeholder="dock.single.Parameters">
<replacement id="dockablesingle Parameters"/>
......@@ -1080,16 +1090,6 @@
</layout>
<children ignore="false"/>
</child>
<child>
<layout factory="predefined" placeholder="dock.single.Presets">
<replacement id="dockablesingle Presets"/>
<delegate id="delegate_ccontrol backup factory id">
<id>Presets</id>
<area/>
</delegate>
</layout>
<children ignore="false"/>
</child>
</children>
</root>
<root name="ccontrol west">
......@@ -1251,12 +1251,9 @@
<property factory="SplitDockPlaceholderProperty">
<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
<backup-path>
<node location="RIGHT" size="0.25" id="1372710005727"/>
<node location="LEFT" size="0.6950092421441774" id="1375899667063"/>
<node location="TOP" size="0.75" id="1386283918535"/>
<node location="LEFT" size="0.3570504527813712" id="1411773916307"/>
<node location="TOP" size="0.5092667203867848" id="1411773956584"/>
<leaf id="1411773916305"/>
<node location="LEFT" size="0.22181146025878004" id="1372710005721"/>
<node location="TOP" size="0.504054054054054" id="1375985011088"/>
<leaf id="1375985003630"/>
</backup-path>
</property>
<property factory="StackDockPropertyFactory">
......@@ -1816,15 +1813,13 @@
<property factory="SplitDockPlaceholderProperty">
<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
<backup-path>
<node location="RIGHT" size="0.25" id="1372710005727"/>
<node location="LEFT" size="0.6950092421441774" id="1375899667063"/>
<node location="TOP" size="0.75" id="1386283918535"/>
<node location="RIGHT" size="0.7106666666666666" id="1389811727550"/>
<leaf id="1375899667061"/>
<node location="LEFT" size="0.22181146025878004" id="1372710005721"/>
<node location="TOP" size="0.504054054054054" id="1375985011088"/>
<leaf id="1375985003630"/>
</backup-path>
</property>
<property factory="StackDockPropertyFactory">
<index>1</index>
<index>2</index>
<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
</property>
</location>
......
platform/altera/wr_arria10_e3p1_phy/wr_arria10_e3p1_atx_pll/.qsys_edit/wr_arria10_e3p1_atx_pll_schematic.nlv
View file @ d45e32f4
# # File gsaved with Nlview version 6.3.8 2013-12-19 bk=1.2992 VDI=34 GEI=35
#
preplace inst unsaved.xcvr_atx_pll_a10_0 -pg 1 -lvl 1 -y 30
preplace inst unsaved -pg 1 -lvl 1 -y 40 -regy -20
preplace netloc EXPORT<net_container>unsaved</net_container>(SLAVE)xcvr_atx_pll_a10_0.pll_locked,(SLAVE)unsaved.pll_locked) 1 0 1 NJ
preplace netloc EXPORT<net_container>unsaved</net_container>(SLAVE)xcvr_atx_pll_a10_0.pll_cal_busy,(SLAVE)unsaved.pll_cal_busy) 1 0 1 NJ
preplace netloc EXPORT<net_container>unsaved</net_container>(SLAVE)unsaved.pll_refclk0,(SLAVE)xcvr_atx_pll_a10_0.pll_refclk0) 1 0 1 NJ
preplace netloc EXPORT<net_container>unsaved</net_container>(SLAVE)unsaved.pll_powerdown,(SLAVE)xcvr_atx_pll_a10_0.pll_powerdown) 1 0 1 NJ
preplace netloc EXPORT<net_container>unsaved</net_container>(MASTER)unsaved.tx_serial_clk,(MASTER)xcvr_atx_pll_a10_0.tx_serial_clk) 1 1 1 N
preplace inst wr_arria10_e3p1_atx_pll -pg 1 -lvl 1 -y 40 -regy -20
preplace inst wr_arria10_e3p1_atx_pll.xcvr_atx_pll_a10_0 -pg 1 -lvl 1 -y 30
preplace netloc EXPORT<net_container>wr_arria10_e3p1_atx_pll</net_container>(SLAVE)xcvr_atx_pll_a10_0.pll_powerdown,(SLAVE)wr_arria10_e3p1_atx_pll.pll_powerdown) 1 0 1 NJ
preplace netloc EXPORT<net_container>wr_arria10_e3p1_atx_pll</net_container>(MASTER)xcvr_atx_pll_a10_0.tx_serial_clk,(MASTER)wr_arria10_e3p1_atx_pll.tx_serial_clk) 1 1 1 N
preplace netloc EXPORT<net_container>wr_arria10_e3p1_atx_pll</net_container>(SLAVE)xcvr_atx_pll_a10_0.pll_locked,(SLAVE)wr_arria10_e3p1_atx_pll.pll_locked) 1 0 1 NJ
preplace netloc EXPORT<net_container>wr_arria10_e3p1_atx_pll</net_container>(SLAVE)xcvr_atx_pll_a10_0.pll_cal_busy,(SLAVE)wr_arria10_e3p1_atx_pll.pll_cal_busy) 1 0 1 NJ
preplace netloc EXPORT<net_container>wr_arria10_e3p1_atx_pll</net_container>(SLAVE)xcvr_atx_pll_a10_0.pll_refclk0,(SLAVE)wr_arria10_e3p1_atx_pll.pll_refclk0) 1 0 1 NJ
levelinfo -pg 1 0 90 430
levelinfo -hier unsaved 100 130 320
levelinfo -hier wr_arria10_e3p1_atx_pll 100 130 320
platform/altera/wr_arria10_e3p1_phy/wr_arria10_e3p1_atx_pll/wr_arria10_e3p1_atx_pll.qsys
View file @ d45e32f4
......@@ -20,9 +20,9 @@
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
<parameter name="device" value="10AX115S2F45I2SG" />
<parameter name="device" value="10AX115S2F45I1SG" />
<parameter name="deviceFamily" value="Arria 10" />
<parameter name="deviceSpeedGrade" value="2" />
<parameter name="deviceSpeedGrade" value="1" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
......@@ -81,7 +81,7 @@
autoexport="1">
<parameter name="base_device" value="NIGHTFURY5" />
<parameter name="bw_sel" value="medium" />
<parameter name="device" value="10AX115S2F45I2SG" />
<parameter name="device" value="10AX115S2F45I1SG" />
<parameter name="device_family" value="Arria 10" />
<parameter name="enable_16G_path" value="0" />
<parameter name="enable_8G_path" value="1" />
......@@ -143,7 +143,7 @@
<parameter name="set_l_counter" value="16" />
<parameter name="set_m_counter" value="24" />
<parameter name="set_manual_reference_clock_frequency" value="200.0" />
<parameter name="set_output_clock_frequency" value="625.0" />
<parameter name="set_output_clock_frequency" value="2500.0" />
<parameter name="set_rcfg_emb_strm_enable" value="0" />
<parameter name="set_ref_clk_div" value="1" />
<parameter name="set_user_identifier" value="0" />
......
platform/altera/wr_arria10_e3p1_phy/wr_arria10_e3p1_atx_pll/wr_arria10_e3p1_atx_pll/altera_xcvr_atx_pll_a10_181/synth/wr_arria10_e3p1_atx_pll_pkg.vhd
View file @ d45e32f4
......@@ -3,7 +3,7 @@ use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package wr_arria10_e3p1_atx_pll_pkg is
component wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_lhyn27i is
component wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_z7ksuua is
generic (
enable_pll_reconfig : integer := 0;
rcfg_jtag_enable : integer := 0;
......@@ -148,6 +148,6 @@ package wr_arria10_e3p1_atx_pll_pkg is
mcgb_cal_busy : out std_logic; -- mcgb_cal_busy
mcgb_hip_cal_done : out std_logic -- hip_cal_done
);
end component wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_lhyn27i;
end component wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_z7ksuua;
end wr_arria10_e3p1_atx_pll_pkg;
platform/altera/wr_arria10_e3p1_phy/wr_arria10_e3p1_atx_pll/wr_arria10_e3p1_atx_pll/greybox/wr_arria10_e3p1_atx_pll.v
View file @ d45e32f4
......@@ -16,7 +16,7 @@
// PROGRAM "Quartus Prime"
// VERSION "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition"
// DATE "06/18/2019 13:51:18"
// DATE "06/21/2019 16:15:14"
//
// Device: Altera 10AX115S2F45I1SG Package FBGA1932
......@@ -56,7 +56,7 @@ wire \pll_powerdown~input_o ;
wire \pll_refclk0~input_o ;
wr_arria10_e3p1_atx_pll_wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_lhyn27i xcvr_atx_pll_a10_0(
wr_arria10_e3p1_atx_pll_wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_z7ksuua xcvr_atx_pll_a10_0(
.pld_cal_done_0(\xcvr_atx_pll_a10_0|a10_xcvr_avmm_inst|pld_cal_done[0] ),
.tx_serial_clk(\xcvr_atx_pll_a10_0|a10_xcvr_atx_pll_inst|pll_serial_clk_8g ),
.pll_locked(\xcvr_atx_pll_a10_0|a10_xcvr_atx_pll_inst|pll_locked ),
......@@ -74,7 +74,7 @@ assign \pll_powerdown~input_o = pll_powerdown;
endmodule
module wr_arria10_e3p1_atx_pll_wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_lhyn27i (
module wr_arria10_e3p1_atx_pll_wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_z7ksuua (
pld_cal_done_0,
tx_serial_clk,
pll_locked,
......@@ -278,7 +278,7 @@ defparam twentynm_atx_pll_inst.cp_lf_3rd_pole_freq = "lf_3rd_pole_setting1";
defparam twentynm_atx_pll_inst.cp_lf_order = "lf_3rd_order";
defparam twentynm_atx_pll_inst.cp_testmode = "cp_normal";
defparam twentynm_atx_pll_inst.d2a_voltage = "d2a_setting_4";
defparam twentynm_atx_pll_inst.datarate = "1250000000 bps";
defparam twentynm_atx_pll_inst.datarate = "5000000000 bps";
defparam twentynm_atx_pll_inst.device_variant = "device1";
defparam twentynm_atx_pll_inst.dprio_clk_vreg_boost_expected_voltage = 12'b000000000000;
defparam twentynm_atx_pll_inst.dprio_clk_vreg_boost_scratch = 3'b000;
......@@ -327,7 +327,7 @@ defparam twentynm_atx_pll_inst.iqclk_mux_sel = "iqtxrxclk0";
defparam twentynm_atx_pll_inst.is_cascaded_pll = "false";
defparam twentynm_atx_pll_inst.is_otn = "false";
defparam twentynm_atx_pll_inst.is_sdi = "false";
defparam twentynm_atx_pll_inst.l_counter = 16;
defparam twentynm_atx_pll_inst.l_counter = 4;
defparam twentynm_atx_pll_inst.l_counter_enable = "true";
defparam twentynm_atx_pll_inst.l_counter_scratch = 5'b00001;
defparam twentynm_atx_pll_inst.lc_atb = "atb_selectdisable";
......@@ -341,7 +341,7 @@ defparam twentynm_atx_pll_inst.m_counter = 40;
defparam twentynm_atx_pll_inst.max_fractional_percentage = 7'b0000000;
defparam twentynm_atx_pll_inst.min_fractional_percentage = 7'b0000000;
defparam twentynm_atx_pll_inst.n_counter_scratch = 3'b001;
defparam twentynm_atx_pll_inst.output_clock_frequency = "625000000 hz";
defparam twentynm_atx_pll_inst.output_clock_frequency = "2500000000 hz";
defparam twentynm_atx_pll_inst.output_regulator_supply = "vreg1v_setting0";
defparam twentynm_atx_pll_inst.overrange_voltage = "over_setting0";
defparam twentynm_atx_pll_inst.pfd_delay_compensation = "normal_delay";
......
platform/altera/wr_arria10_e3p1_phy/wr_arria10_e3p1_atx_pll/wr_arria10_e3p1_atx_pll/sim/aldec/rivierapro_setup.tcl
View file @ d45e32f4
......@@ -12,7 +12,7 @@
# or its authorized distributors. Please refer to the applicable
# agreement for further details.
# ACDS 18.1 625 linux 2019.06.18.13:51:03
# ACDS 18.1 625 linux 2019.06.21.16:14:58
# ----------------------------------------
# Auto-generated simulation script rivierapro_setup.tcl
# ----------------------------------------
......@@ -250,8 +250,8 @@ alias com {
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/../altera_xcvr_atx_pll_a10_181/sim/a10_xcvr_atx_pll.sv" -l altera_common_sv_packages -work wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/../altera_xcvr_atx_pll_a10_181/sim/alt_xcvr_pll_embedded_debug.sv" -l altera_common_sv_packages -work wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/../altera_xcvr_atx_pll_a10_181/sim/alt_xcvr_pll_avmm_csr.sv" -l altera_common_sv_packages -work wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/../altera_xcvr_atx_pll_a10_181/sim/wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_lhyn27i.sv" -l altera_common_sv_packages -work wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/../altera_xcvr_atx_pll_a10_181/sim/alt_xcvr_atx_pll_rcfg_opt_logic_lhyn27i.sv" -l altera_common_sv_packages -work wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/../altera_xcvr_atx_pll_a10_181/sim/wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_z7ksuua.sv" -l altera_common_sv_packages -work wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/../altera_xcvr_atx_pll_a10_181/sim/alt_xcvr_atx_pll_rcfg_opt_logic_z7ksuua.sv" -l altera_common_sv_packages -work wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/wr_arria10_e3p1_atx_pll.vhd"
}
......
platform/altera/wr_arria10_e3p1_phy/wr_arria10_e3p1_atx_pll/wr_arria10_e3p1_atx_pll/sim/cadence/ncsim_setup.sh
View file @ d45e32f4
......@@ -12,7 +12,7 @@
# or its authorized distributors. Please refer to the applicable
# agreement for further details.
# ACDS 18.1 625 linux 2019.06.18.13:51:03
# ACDS 18.1 625 linux 2019.06.21.16:14:58
# ----------------------------------------
# ncsim - auto-generated simulation script
......@@ -106,7 +106,7 @@
# within the Quartus project, and generate a unified
# script which supports all the Altera IP within the design.
# ----------------------------------------
# ACDS 18.1 625 linux 2019.06.18.13:51:03
# ACDS 18.1 625 linux 2019.06.21.16:14:58
# ----------------------------------------
# initialize variables
TOP_LEVEL_NAME="wr_arria10_e3p1_atx_pll"
......@@ -214,8 +214,8 @@ if [ $SKIP_COM -eq 0 ]; then
ncvlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/../altera_xcvr_atx_pll_a10_181/sim/a10_xcvr_atx_pll.sv" -work wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181 -cdslib ./cds_libs/wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181.cds.lib
ncvlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/../altera_xcvr_atx_pll_a10_181/sim/alt_xcvr_pll_embedded_debug.sv" -work wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181 -cdslib ./cds_libs/wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181.cds.lib
ncvlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/../altera_xcvr_atx_pll_a10_181/sim/alt_xcvr_pll_avmm_csr.sv" -work wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181 -cdslib ./cds_libs/wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181.cds.lib
ncvlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/../altera_xcvr_atx_pll_a10_181/sim/wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_lhyn27i.sv" -work wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181 -cdslib ./cds_libs/wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181.cds.lib
ncvlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/../altera_xcvr_atx_pll_a10_181/sim/alt_xcvr_atx_pll_rcfg_opt_logic_lhyn27i.sv" -work wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181 -cdslib ./cds_libs/wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181.cds.lib
ncvlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/../altera_xcvr_atx_pll_a10_181/sim/wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_z7ksuua.sv" -work wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181 -cdslib ./cds_libs/wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181.cds.lib
ncvlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/../altera_xcvr_atx_pll_a10_181/sim/alt_xcvr_atx_pll_rcfg_opt_logic_z7ksuua.sv" -work wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181 -cdslib ./cds_libs/wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181.cds.lib
ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/wr_arria10_e3p1_atx_pll.vhd"
fi
......
platform/altera/wr_arria10_e3p1_phy/wr_arria10_e3p1_atx_pll/wr_arria10_e3p1_atx_pll/sim/mentor/msim_setup.tcl
View file @ d45e32f4
......@@ -94,7 +94,7 @@
# within the Quartus project, and generate a unified
# script which supports all the Altera IP within the design.
# ----------------------------------------
# ACDS 18.1 625 linux 2019.06.18.13:51:03
# ACDS 18.1 625 linux 2019.06.21.16:14:58
# ----------------------------------------
# Initialize variables
......@@ -251,8 +251,8 @@ alias com {
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/../altera_xcvr_atx_pll_a10_181/sim/mentor/a10_xcvr_atx_pll.sv" -L altera_common_sv_packages -work wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/../altera_xcvr_atx_pll_a10_181/sim/mentor/alt_xcvr_pll_embedded_debug.sv" -L altera_common_sv_packages -work wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/../altera_xcvr_atx_pll_a10_181/sim/mentor/alt_xcvr_pll_avmm_csr.sv" -L altera_common_sv_packages -work wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/../altera_xcvr_atx_pll_a10_181/sim/wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_lhyn27i.sv" -L altera_common_sv_packages -work wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/../altera_xcvr_atx_pll_a10_181/sim/alt_xcvr_atx_pll_rcfg_opt_logic_lhyn27i.sv" -L altera_common_sv_packages -work wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/../altera_xcvr_atx_pll_a10_181/sim/wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_z7ksuua.sv" -L altera_common_sv_packages -work wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/../altera_xcvr_atx_pll_a10_181/sim/alt_xcvr_atx_pll_rcfg_opt_logic_z7ksuua.sv" -L altera_common_sv_packages -work wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/wr_arria10_e3p1_atx_pll.vhd"
}
......
platform/altera/wr_arria10_e3p1_phy/wr_arria10_e3p1_atx_pll/wr_arria10_e3p1_atx_pll/sim/synopsys/vcsmx/vcsmx_setup.sh
View file @ d45e32f4
......@@ -12,7 +12,7 @@
# or its authorized distributors. Please refer to the applicable
# agreement for further details.
# ACDS 18.1 625 linux 2019.06.18.13:51:03
# ACDS 18.1 625 linux 2019.06.21.16:14:58
# ----------------------------------------
# vcsmx - auto-generated simulation script
......@@ -107,7 +107,7 @@
# within the Quartus project, and generate a unified
# script which supports all the Altera IP within the design.
# ----------------------------------------
# ACDS 18.1 625 linux 2019.06.18.13:51:03
# ACDS 18.1 625 linux 2019.06.21.16:14:58
# ----------------------------------------
# initialize variables
TOP_LEVEL_NAME="wr_arria10_e3p1_atx_pll"
......@@ -220,8 +220,8 @@ if [ $SKIP_COM -eq 0 ]; then
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/../altera_xcvr_atx_pll_a10_181/sim/a10_xcvr_atx_pll.sv" -work wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/../altera_xcvr_atx_pll_a10_181/sim/alt_xcvr_pll_embedded_debug.sv" -work wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/../altera_xcvr_atx_pll_a10_181/sim/alt_xcvr_pll_avmm_csr.sv" -work wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/../altera_xcvr_atx_pll_a10_181/sim/wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_lhyn27i.sv" -work wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/../altera_xcvr_atx_pll_a10_181/sim/alt_xcvr_atx_pll_rcfg_opt_logic_lhyn27i.sv" -work wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/../altera_xcvr_atx_pll_a10_181/sim/wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_z7ksuua.sv" -work wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/../altera_xcvr_atx_pll_a10_181/sim/alt_xcvr_atx_pll_rcfg_opt_logic_z7ksuua.sv" -work wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181
vhdlan -xlrm $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/wr_arria10_e3p1_atx_pll.vhd"
fi
......
platform/altera/wr_arria10_e3p1_phy/wr_arria10_e3p1_atx_pll/wr_arria10_e3p1_atx_pll/sim/wr_arria10_e3p1_atx_pll.vhd
View file @ d45e32f4
......@@ -18,7 +18,7 @@ entity wr_arria10_e3p1_atx_pll is
end entity wr_arria10_e3p1_atx_pll;
architecture rtl of wr_arria10_e3p1_atx_pll is
component wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_lhyn27i is
component wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_z7ksuua is
generic (
enable_pll_reconfig : integer := 0;
rcfg_jtag_enable : integer := 0;
......@@ -163,13 +163,13 @@ architecture rtl of wr_arria10_e3p1_atx_pll is
mcgb_cal_busy : out std_logic; -- mcgb_cal_busy
mcgb_hip_cal_done : out std_logic -- hip_cal_done
);
end component wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_lhyn27i;
end component wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_z7ksuua;
for xcvr_atx_pll_a10_0 : wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_lhyn27i
use entity wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181.wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_lhyn27i;
for xcvr_atx_pll_a10_0 : wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_z7ksuua
use entity wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181.wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_z7ksuua;
begin
xcvr_atx_pll_a10_0 : component wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_lhyn27i
xcvr_atx_pll_a10_0 : component wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_z7ksuua
generic map (
enable_pll_reconfig => 0,
rcfg_jtag_enable => 0,
......@@ -219,7 +219,7 @@ begin
atx_pll_dsm_fractional_value_ready => "pll_k_ready",
atx_pll_iqclk_mux_sel => "iqtxrxclk0",
atx_pll_vco_bypass_enable => "false",
atx_pll_l_counter => 16,
atx_pll_l_counter => 4,
atx_pll_l_counter_enable => "true",
atx_pll_cascadeclk_test => "cascadetest_off",
atx_pll_hclk_divide => 1,
......@@ -227,11 +227,11 @@ begin
atx_pll_m_counter => 40,
atx_pll_ref_clk_div => 1,
atx_pll_bw_sel => "medium",
atx_pll_datarate => "1250000000 bps",
atx_pll_datarate => "5000000000 bps",
atx_pll_device_variant => "device1",
atx_pll_initial_settings => "true",
atx_pll_lc_mode => "lccmu_normal",
atx_pll_output_clock_frequency => "625000000 Hz",
atx_pll_output_clock_frequency => "2500000000 Hz",
atx_pll_powerdown_mode => "powerup",
atx_pll_prot_mode => "basic_tx",
atx_pll_reference_clock_frequency => "125000000 Hz",
......@@ -258,7 +258,7 @@ begin
hssi_pma_cgb_master_x1_div_m_sel => "divbypass",
hssi_pma_cgb_master_cgb_enable_iqtxrxclk => "disable_iqtxrxclk",
hssi_pma_cgb_master_ser_mode => "sixty_four_bit",
hssi_pma_cgb_master_datarate => "1250000000 bps",
hssi_pma_cgb_master_datarate => "5000000000 bps",
hssi_pma_cgb_master_cgb_power_down => "normal_cgb",
hssi_pma_cgb_master_observe_cgb_clocks => "observe_nothing",
hssi_pma_cgb_master_op_mode => "enabled",
......
platform/altera/wr_arria10_e3p1_phy/wr_arria10_e3p1_atx_pll/wr_arria10_e3p1_atx_pll/synth/wr_arria10_e3p1_atx_pll.vhd
View file @ d45e32f4
......@@ -21,7 +21,7 @@ end entity wr_arria10_e3p1_atx_pll;
architecture rtl of wr_arria10_e3p1_atx_pll is
begin
xcvr_atx_pll_a10_0 : component wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181.wr_arria10_e3p1_atx_pll_pkg.wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_lhyn27i
xcvr_atx_pll_a10_0 : component wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181.wr_arria10_e3p1_atx_pll_pkg.wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_z7ksuua
generic map (
enable_pll_reconfig => 0,
rcfg_jtag_enable => 0,
......@@ -71,7 +71,7 @@ begin
atx_pll_dsm_fractional_value_ready => "pll_k_ready",
atx_pll_iqclk_mux_sel => "iqtxrxclk0",
atx_pll_vco_bypass_enable => "false",
atx_pll_l_counter => 16,
atx_pll_l_counter => 4,
atx_pll_l_counter_enable => "true",
atx_pll_cascadeclk_test => "cascadetest_off",
atx_pll_hclk_divide => 1,
......@@ -79,11 +79,11 @@ begin
atx_pll_m_counter => 40,
atx_pll_ref_clk_div => 1,
atx_pll_bw_sel => "medium",
atx_pll_datarate => "1250000000 bps",
atx_pll_datarate => "5000000000 bps",
atx_pll_device_variant => "device1",
atx_pll_initial_settings => "true",
atx_pll_lc_mode => "lccmu_normal",
atx_pll_output_clock_frequency => "625000000 Hz",
atx_pll_output_clock_frequency => "2500000000 Hz",
atx_pll_powerdown_mode => "powerup",
atx_pll_prot_mode => "basic_tx",
atx_pll_reference_clock_frequency => "125000000 Hz",
......@@ -110,7 +110,7 @@ begin
hssi_pma_cgb_master_x1_div_m_sel => "divbypass",
hssi_pma_cgb_master_cgb_enable_iqtxrxclk => "disable_iqtxrxclk",
hssi_pma_cgb_master_ser_mode => "sixty_four_bit",
hssi_pma_cgb_master_datarate => "1250000000 bps",
hssi_pma_cgb_master_datarate => "5000000000 bps",
hssi_pma_cgb_master_cgb_power_down => "normal_cgb",
hssi_pma_cgb_master_observe_cgb_clocks => "observe_nothing",
hssi_pma_cgb_master_op_mode => "enabled",
......
platform/altera/wr_arria10_e3p1_phy/wr_arria10_e3p1_atx_pll/wr_arria10_e3p1_atx_pll/wr_arria10_e3p1_atx_pll.bsf
View file @ d45e32f4
......@@ -69,7 +69,7 @@ refer to the applicable agreement for further details.
(text "clk" (rect 101 107 220 224)(font "Arial" (color 0 0 0)))
(text "tx_serial_clk" (rect 241 123 560 259)(font "Arial" (color 128 0 0)(font_size 9)))
(text "clk" (rect 225 147 468 304)(font "Arial" (color 0 0 0)))
(text " wr_arria10_e3p1_atx_pll " (rect 229 168 608 346)(font "Arial" ))
(text " system " (rect 301 168 650 346)(font "Arial" ))
(line (pt 96 32)(pt 240 32)(line_width 1))
(line (pt 240 32)(pt 240 168)(line_width 1))
(line (pt 96 168)(pt 240 168)(line_width 1))
......
platform/altera/wr_arria10_e3p1_phy/wr_arria10_e3p1_atx_pll/wr_arria10_e3p1_atx_pll/wr_arria10_e3p1_atx_pll.csv
View file @ d45e32f4
# system info wr_arria10_e3p1_atx_pll on 2019.06.18.13:51:02
# system info wr_arria10_e3p1_atx_pll on 2019.06.21.16:14:58
system_info:
name,value
DEVICE,10AX115S2F45I1SG
DEVICE_FAMILY,Arria 10
GENERATION_ID,1560858662
GENERATION_ID,1561126498
#
#
# Files generated for wr_arria10_e3p1_atx_pll on 2019.06.18.13:51:02
# Files generated for wr_arria10_e3p1_atx_pll on 2019.06.21.16:14:58
files:
filepath,kind,attributes,module,is_top
sim/wr_arria10_e3p1_atx_pll.vhd,VHDL,CONTAINS_INLINE_CONFIGURATION,wr_arria10_e3p1_atx_pll,true
altera_xcvr_atx_pll_a10_181/sim/twentynm_xcvr_avmm.sv,SYSTEM_VERILOG,,wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_lhyn27i,false
altera_xcvr_atx_pll_a10_181/sim/mentor/twentynm_xcvr_avmm.sv,SYSTEM_VERILOG_ENCRYPT,MENTOR_SPECIFIC,wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_lhyn27i,false
altera_xcvr_atx_pll_a10_181/sim/alt_xcvr_resync.sv,SYSTEM_VERILOG,,wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_lhyn27i,false
altera_xcvr_atx_pll_a10_181/sim/alt_xcvr_arbiter.sv,SYSTEM_VERILOG,,wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_lhyn27i,false
altera_xcvr_atx_pll_a10_181/sim/mentor/alt_xcvr_resync.sv,SYSTEM_VERILOG_ENCRYPT,MENTOR_SPECIFIC,wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_lhyn27i,false
altera_xcvr_atx_pll_a10_181/sim/mentor/alt_xcvr_arbiter.sv,SYSTEM_VERILOG_ENCRYPT,MENTOR_SPECIFIC,wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_lhyn27i,false
altera_xcvr_atx_pll_a10_181/sim/a10_avmm_h.sv,SYSTEM_VERILOG,,wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_lhyn27i,false
altera_xcvr_atx_pll_a10_181/sim/altera_xcvr_native_a10_functions_h.sv,SYSTEM_VERILOG, COMMON_SYSTEMVERILOG_PACKAGE=altera_xcvr_native_a10_functions_h,wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_lhyn27i,false
altera_xcvr_atx_pll_a10_181/sim/alt_xcvr_atx_pll_rcfg_arb.sv,SYSTEM_VERILOG,,wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_lhyn27i,false
altera_xcvr_atx_pll_a10_181/sim/a10_xcvr_atx_pll.sv,SYSTEM_VERILOG,,wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_lhyn27i,false
altera_xcvr_atx_pll_a10_181/sim/alt_xcvr_pll_embedded_debug.sv,SYSTEM_VERILOG,,wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_lhyn27i,false
altera_xcvr_atx_pll_a10_181/sim/alt_xcvr_pll_avmm_csr.sv,SYSTEM_VERILOG,,wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_lhyn27i,false
altera_xcvr_atx_pll_a10_181/sim/mentor/alt_xcvr_atx_pll_rcfg_arb.sv,SYSTEM_VERILOG_ENCRYPT,MENTOR_SPECIFIC,wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_lhyn27i,false
altera_xcvr_atx_pll_a10_181/sim/mentor/a10_xcvr_atx_pll.sv,SYSTEM_VERILOG_ENCRYPT,MENTOR_SPECIFIC,wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_lhyn27i,false
altera_xcvr_atx_pll_a10_181/sim/mentor/alt_xcvr_pll_embedded_debug.sv,SYSTEM_VERILOG_ENCRYPT,MENTOR_SPECIFIC,wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_lhyn27i,false
altera_xcvr_atx_pll_a10_181/sim/mentor/alt_xcvr_pll_avmm_csr.sv,SYSTEM_VERILOG_ENCRYPT,MENTOR_SPECIFIC,wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_lhyn27i,false
altera_xcvr_atx_pll_a10_181/sim/plain_files.txt,OTHER,,wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_lhyn27i,false
altera_xcvr_atx_pll_a10_181/sim/mentor_files.txt,OTHER,,wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_lhyn27i,false
altera_xcvr_atx_pll_a10_181/sim/cadence_files.txt,OTHER,,wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_lhyn27i,false
altera_xcvr_atx_pll_a10_181/sim/synopsys_files.txt,OTHER,,wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_lhyn27i,false
altera_xcvr_atx_pll_a10_181/sim/aldec_files.txt,OTHER,,wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_lhyn27i,false
altera_xcvr_atx_pll_a10_181/sim/wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_lhyn27i.sv,SYSTEM_VERILOG,,wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_lhyn27i,false
altera_xcvr_atx_pll_a10_181/sim/alt_xcvr_atx_pll_rcfg_opt_logic_lhyn27i.sv,SYSTEM_VERILOG,,wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_lhyn27i,false
altera_xcvr_atx_pll_a10_181/sim/twentynm_xcvr_avmm.sv,SYSTEM_VERILOG,,wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_z7ksuua,false
altera_xcvr_atx_pll_a10_181/sim/mentor/twentynm_xcvr_avmm.sv,SYSTEM_VERILOG_ENCRYPT,MENTOR_SPECIFIC,wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_z7ksuua,false
altera_xcvr_atx_pll_a10_181/sim/alt_xcvr_resync.sv,SYSTEM_VERILOG,,wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_z7ksuua,false
altera_xcvr_atx_pll_a10_181/sim/alt_xcvr_arbiter.sv,SYSTEM_VERILOG,,wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_z7ksuua,false
altera_xcvr_atx_pll_a10_181/sim/mentor/alt_xcvr_resync.sv,SYSTEM_VERILOG_ENCRYPT,MENTOR_SPECIFIC,wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_z7ksuua,false
altera_xcvr_atx_pll_a10_181/sim/mentor/alt_xcvr_arbiter.sv,SYSTEM_VERILOG_ENCRYPT,MENTOR_SPECIFIC,wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_z7ksuua,false
altera_xcvr_atx_pll_a10_181/sim/a10_avmm_h.sv,SYSTEM_VERILOG,,wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_z7ksuua,false
altera_xcvr_atx_pll_a10_181/sim/altera_xcvr_native_a10_functions_h.sv,SYSTEM_VERILOG, COMMON_SYSTEMVERILOG_PACKAGE=altera_xcvr_native_a10_functions_h,wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_z7ksuua,false
altera_xcvr_atx_pll_a10_181/sim/alt_xcvr_atx_pll_rcfg_arb.sv,SYSTEM_VERILOG,,wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_z7ksuua,false
altera_xcvr_atx_pll_a10_181/sim/a10_xcvr_atx_pll.sv,SYSTEM_VERILOG,,wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_z7ksuua,false
altera_xcvr_atx_pll_a10_181/sim/alt_xcvr_pll_embedded_debug.sv,SYSTEM_VERILOG,,wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_z7ksuua,false
altera_xcvr_atx_pll_a10_181/sim/alt_xcvr_pll_avmm_csr.sv,SYSTEM_VERILOG,,wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_z7ksuua,false
altera_xcvr_atx_pll_a10_181/sim/mentor/alt_xcvr_atx_pll_rcfg_arb.sv,SYSTEM_VERILOG_ENCRYPT,MENTOR_SPECIFIC,wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_z7ksuua,false
altera_xcvr_atx_pll_a10_181/sim/mentor/a10_xcvr_atx_pll.sv,SYSTEM_VERILOG_ENCRYPT,MENTOR_SPECIFIC,wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_z7ksuua,false
altera_xcvr_atx_pll_a10_181/sim/mentor/alt_xcvr_pll_embedded_debug.sv,SYSTEM_VERILOG_ENCRYPT,MENTOR_SPECIFIC,wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_z7ksuua,false
altera_xcvr_atx_pll_a10_181/sim/mentor/alt_xcvr_pll_avmm_csr.sv,SYSTEM_VERILOG_ENCRYPT,MENTOR_SPECIFIC,wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_z7ksuua,false
altera_xcvr_atx_pll_a10_181/sim/plain_files.txt,OTHER,,wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_z7ksuua,false
altera_xcvr_atx_pll_a10_181/sim/mentor_files.txt,OTHER,,wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_z7ksuua,false
altera_xcvr_atx_pll_a10_181/sim/cadence_files.txt,OTHER,,wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_z7ksuua,false
altera_xcvr_atx_pll_a10_181/sim/synopsys_files.txt,OTHER,,wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_z7ksuua,false
altera_xcvr_atx_pll_a10_181/sim/aldec_files.txt,OTHER,,wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_z7ksuua,false
altera_xcvr_atx_pll_a10_181/sim/wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_z7ksuua.sv,SYSTEM_VERILOG,,wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_z7ksuua,false
altera_xcvr_atx_pll_a10_181/sim/alt_xcvr_atx_pll_rcfg_opt_logic_z7ksuua.sv,SYSTEM_VERILOG,,wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_z7ksuua,false
#
# Map from instance-path to kind of module
instances:
instancePath,module
wr_arria10_e3p1_atx_pll.xcvr_atx_pll_a10_0,wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_lhyn27i
wr_arria10_e3p1_atx_pll.xcvr_atx_pll_a10_0,wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_z7ksuua
platform/altera/wr_arria10_e3p1_phy/wr_arria10_e3p1_atx_pll/wr_arria10_e3p1_atx_pll/wr_arria10_e3p1_atx_pll.sip
View file @ d45e32f4
......@@ -26,5 +26,5 @@ set_global_assignment -library "lib_wr_arria10_e3p1_atx_pll" -name MISC_FILE [fi
set_global_assignment -library "lib_wr_arria10_e3p1_atx_pll" -name MISC_FILE [file join $::quartus(sip_path) "altera_xcvr_atx_pll_a10_181/sim/cadence_files.txt"]
set_global_assignment -library "lib_wr_arria10_e3p1_atx_pll" -name MISC_FILE [file join $::quartus(sip_path) "altera_xcvr_atx_pll_a10_181/sim/synopsys_files.txt"]
set_global_assignment -library "lib_wr_arria10_e3p1_atx_pll" -name MISC_FILE [file join $::quartus(sip_path) "altera_xcvr_atx_pll_a10_181/sim/aldec_files.txt"]
set_global_assignment -library "lib_wr_arria10_e3p1_atx_pll" -name MISC_FILE [file join $::quartus(sip_path) "altera_xcvr_atx_pll_a10_181/sim/wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_lhyn27i.sv"]
set_global_assignment -library "lib_wr_arria10_e3p1_atx_pll" -name MISC_FILE [file join $::quartus(sip_path) "altera_xcvr_atx_pll_a10_181/sim/alt_xcvr_atx_pll_rcfg_opt_logic_lhyn27i.sv"]
set_global_assignment -library "lib_wr_arria10_e3p1_atx_pll" -name MISC_FILE [file join $::quartus(sip_path) "altera_xcvr_atx_pll_a10_181/sim/wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_z7ksuua.sv"]
set_global_assignment -library "lib_wr_arria10_e3p1_atx_pll" -name MISC_FILE [file join $::quartus(sip_path) "altera_xcvr_atx_pll_a10_181/sim/alt_xcvr_atx_pll_rcfg_opt_logic_z7ksuua.sv"]
platform/altera/wr_arria10_e3p1_phy/wr_arria10_e3p1_atx_pll/wr_arria10_e3p1_atx_pll/wr_arria10_e3p1_atx_pll.spd
View file @ d45e32f4
......@@ -93,11 +93,11 @@
type="OTHER"
library="wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181" />
<file
path="altera_xcvr_atx_pll_a10_181/sim/wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_lhyn27i.sv"
path="altera_xcvr_atx_pll_a10_181/sim/wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_z7ksuua.sv"
type="SYSTEM_VERILOG"
library="wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181" />
<file
path="altera_xcvr_atx_pll_a10_181/sim/alt_xcvr_atx_pll_rcfg_opt_logic_lhyn27i.sv"
path="altera_xcvr_atx_pll_a10_181/sim/alt_xcvr_atx_pll_rcfg_opt_logic_z7ksuua.sv"
type="SYSTEM_VERILOG"
library="wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181" />
<file
......
platform/altera/wr_arria10_e3p1_phy/wr_arria10_e3p1_atx_pll/wr_arria10_e3p1_atx_pll/wr_arria10_e3p1_atx_pll_bb.v
View file @ d45e32f4
module wr_arria10_e3p1_atx_pll (
pll_cal_busy,
pll_locked,
pll_powerdown,
pll_refclk0,
tx_serial_clk,
pll_locked,
pll_cal_busy);
tx_serial_clk);
output pll_cal_busy;
output pll_locked;
input pll_powerdown;
input pll_refclk0;
output tx_serial_clk;
output pll_locked;
output pll_cal_busy;
endmodule
platform/altera/wr_arria10_e3p1_phy/wr_arria10_e3p1_atx_pll/wr_arria10_e3p1_atx_pll/wr_arria10_e3p1_atx_pll_inst.v
View file @ d45e32f4
wr_arria10_e3p1_atx_pll u0 (
.pll_cal_busy (<connected-to-pll_cal_busy>), // pll_cal_busy.pll_cal_busy
.pll_locked (<connected-to-pll_locked>), // pll_locked.pll_locked
.pll_powerdown (<connected-to-pll_powerdown>), // pll_powerdown.pll_powerdown
.pll_refclk0 (<connected-to-pll_refclk0>), // pll_refclk0.clk
.tx_serial_clk (<connected-to-tx_serial_clk>), // tx_serial_clk.clk
.pll_locked (<connected-to-pll_locked>), // pll_locked.pll_locked
.pll_cal_busy (<connected-to-pll_cal_busy>) // pll_cal_busy.pll_cal_busy
.tx_serial_clk (<connected-to-tx_serial_clk>) // tx_serial_clk.clk
);
platform/altera/wr_arria10_e3p1_phy/wr_arria10_e3p1_atx_pll/wr_arria10_e3p1_atx_pll/wr_arria10_e3p1_atx_pll_inst.vhd
View file @ d45e32f4
component wr_arria10_e3p1_atx_pll is
port (
pll_cal_busy : out std_logic; -- pll_cal_busy
pll_locked : out std_logic; -- pll_locked
pll_powerdown : in std_logic := 'X'; -- pll_powerdown
pll_refclk0 : in std_logic := 'X'; -- clk
tx_serial_clk : out std_logic; -- clk
pll_locked : out std_logic; -- pll_locked
pll_cal_busy : out std_logic -- pll_cal_busy
tx_serial_clk : out std_logic -- clk
);
end component wr_arria10_e3p1_atx_pll;
u0 : component wr_arria10_e3p1_atx_pll
port map (
pll_cal_busy => CONNECTED_TO_pll_cal_busy, -- pll_cal_busy.pll_cal_busy
pll_locked => CONNECTED_TO_pll_locked, -- pll_locked.pll_locked
pll_powerdown => CONNECTED_TO_pll_powerdown, -- pll_powerdown.pll_powerdown
pll_refclk0 => CONNECTED_TO_pll_refclk0, -- pll_refclk0.clk
tx_serial_clk => CONNECTED_TO_tx_serial_clk, -- tx_serial_clk.clk
pll_locked => CONNECTED_TO_pll_locked, -- pll_locked.pll_locked
pll_cal_busy => CONNECTED_TO_pll_cal_busy -- pll_cal_busy.pll_cal_busy
tx_serial_clk => CONNECTED_TO_tx_serial_clk -- tx_serial_clk.clk
);
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