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White Rabbit core collection
Commit d8fb37e6 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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wrcore: parametrized number of clk_aux inputs

parent 4b87684a
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Showing with 22 additions and 17 deletions
modules/wrc_core/wr_core.vhd
View file @ d8fb37e6
......@@ -5,7 +5,7 @@
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-02-02
-- Last update: 2012-04-12
-- Last update: 2012-04-20
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -63,6 +63,7 @@ entity wr_core is
g_phys_uart : boolean := true;
g_virtual_uart : boolean := false;
g_with_external_clock_input : boolean := false;
g_aux_clks : integer := 1;
g_rx_buffer_size : integer := 1024;
g_dpram_initf : string := "";
g_dpram_initv : t_xwb_dpram_init := c_xwb_dpram_init_nothing;
......@@ -85,8 +86,8 @@ entity wr_core is
-- Timing reference (125 MHz)
clk_ref_i : in std_logic;
-- Aux clock (i.e. the FMC clock), which can be disciplined by the WR Core
clk_aux_i : in std_logic;
-- Aux clocks (i.e. the FMC clock), which can be disciplined by the WR Core
clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
-- External 10 MHz reference (cesium, GPSDO, etc.), used in Grandmaster mode
clk_ext_i : in std_logic;
......@@ -413,11 +414,11 @@ begin
-----------------------------------------------------------------------------
PPS_GEN : xwr_pps_gen
generic map(
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_ref_clock_rate => 125000000,
g_ext_clock_rate => 10000000,
g_with_ext_clock_input=> g_with_external_clock_input)
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_ref_clock_rate => 125000000,
g_ext_clock_rate => 10000000,
g_with_ext_clock_input => g_with_external_clock_input)
port map(
clk_ref_i => clk_ref_i,
clk_sys_i => clk_sys_i,
......@@ -471,8 +472,8 @@ begin
-- DMTD Offset clock
clk_dmtd_i => clk_dmtd_i,
clk_ext_i => clk_ext_i,
sync_p_i => pps_ext_i,
clk_ext_i => clk_ext_i,
sync_p_i => pps_ext_i,
-- DMTD oscillator drive
dac_dmtd_data_o => dac_hpll_data_o,
......
modules/wrc_core/xwr_core.vhd
View file @ d8fb37e6
......@@ -6,7 +6,7 @@
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-02-02
-- Last update: 2012-04-12
-- Last update: 2012-04-20
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -50,6 +50,7 @@ entity xwr_core is
g_phys_uart : boolean := true;
g_virtual_uart : boolean := false;
g_with_external_clock_input : boolean := false;
g_aux_clks : integer := 1;
g_ep_rxbuf_size : integer := 1024;
g_dpram_initf : string := "";
g_dpram_initv : t_xwb_dpram_init := c_xwb_dpram_init_nothing;
......@@ -72,7 +73,7 @@ entity xwr_core is
clk_ref_i : in std_logic;
-- Aux clock (i.e. the FMC clock), which can be disciplined by the WR Core
clk_aux_i : in std_logic;
clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
-- External 10 MHz reference (cesium, GPSDO, etc.), used in Grandmaster mode
clk_ext_i : in std_logic;
......@@ -189,6 +190,7 @@ architecture struct of xwr_core is
g_phys_uart : boolean := true;
g_virtual_uart : boolean := false;
g_with_external_clock_input : boolean := false;
g_aux_clks : integer := 1;
g_rx_buffer_size : integer := 12;
g_dpram_initf : string := "";
g_dpram_initv : t_xwb_dpram_init := c_xwb_dpram_init_nothing;
......@@ -199,7 +201,7 @@ architecture struct of xwr_core is
clk_sys_i : in std_logic;
clk_dmtd_i : in std_logic;
clk_ref_i : in std_logic;
clk_aux_i : in std_logic;
clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
clk_ext_i : in std_logic;
pps_ext_i : in std_logic;
rst_n_i : in std_logic;
......
top/spec_1_1/wr_core_demo/spec_top.vhd
View file @ d8fb37e6
......@@ -233,6 +233,7 @@ architecture rtl of spec_top is
g_phys_uart : boolean := true;
g_virtual_uart : boolean := false;
g_with_external_clock_input : boolean := false;
g_aux_clks : integer := 1;
g_ep_rxbuf_size : integer := 1024;
g_dpram_initf : string := "";
g_dpram_size : integer := 16384; --in 32-bit words
......@@ -243,9 +244,9 @@ architecture rtl of spec_top is
clk_sys_i : in std_logic;
clk_dmtd_i : in std_logic;
clk_ref_i : in std_logic;
clk_aux_i : in std_logic;
clk_ext_i : in std_logic := '0';
pps_ext_i : in std_logic := '0';
clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
clk_ext_i : in std_logic := '0';
pps_ext_i : in std_logic := '0';
rst_n_i : in std_logic;
dac_hpll_load_p1_o : out std_logic;
......@@ -757,6 +758,7 @@ begin
g_phys_uart => true,
g_virtual_uart => false,
g_with_external_clock_input => true,
g_aux_clks => 1,
g_ep_rxbuf_size => 1024,
g_dpram_initf => "",
g_dpram_size => 16384,
......@@ -766,7 +768,7 @@ begin
clk_sys_i => clk_sys,
clk_dmtd_i => clk_dmtd,
clk_ref_i => clk_125m_pllref,
clk_aux_i => '0',
clk_aux_i => (others => '0'),
clk_ext_i => dio_clk,
pps_ext_i => dio_in(3),
rst_n_i => local_reset_n,
......
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