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White Rabbit core collection
Commit da2a99aa authored by Dimitris Lampridis's avatar Dimitris Lampridis
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board/svec: switch to new gc_reset_multi_aasd reset core

parent f9ab6b4e
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Showing with 10 additions and 12 deletions
board/svec/xwrc_board_svec.vhd
View file @ da2a99aa
...@@ -357,7 +357,7 @@ begin -- architecture struct ...@@ -357,7 +357,7 @@ begin -- architecture struct
-- generate rstlogic_arst_n. This is needed to connect optional reset like PCIe -- generate rstlogic_arst_n. This is needed to connect optional reset like PCIe
-- reset. When baord runs standalone, we need to ignore PCIe reset being -- reset. When baord runs standalone, we need to ignore PCIe reset being
-- constantly low. -- constantly low.
cmp_arst_edge: gc_sync_ffs cmp_arst_edge : gc_sync_ffs
generic map ( generic map (
g_sync_edge => "positive") g_sync_edge => "positive")
port map ( port map (
...@@ -366,23 +366,21 @@ begin -- architecture struct ...@@ -366,23 +366,21 @@ begin -- architecture struct
data_i => areset_edge_n_i, data_i => areset_edge_n_i,
ppulse_o => areset_edge_ppulse); ppulse_o => areset_edge_ppulse);
-- logic AND of all async reset sources (active low) -- logic AND of all async reset sources (active high)
rstlogic_arst_n <= pll_locked and areset_n_i and (not areset_edge_ppulse); rstlogic_arst <= (not pll_locked) and (not areset_n_i) and areset_edge_ppulse;
-- concatenation of all clocks required to have synced resets -- concatenation of all clocks required to have synced resets
rstlogic_clk_in(0) <= clk_pll_62m5; rstlogic_clk_in(0) <= clk_pll_62m5;
rstlogic_clk_in(1) <= clk_pll_125m; rstlogic_clk_in(1) <= clk_pll_125m;
cmp_rstlogic_reset : gc_reset cmp_rstlogic_reset : gc_reset_multi_aasd
generic map ( generic map (
g_clocks => 2, -- 62.5MHz, 125MHz g_CLOCKS => 2, -- 62.5MHz, 125MHz
g_logdelay => 4, -- 16 clock cycles g_RST_LEN => 16) -- 16 clock cycles
g_syncdepth => 3) -- length of sync chains
port map ( port map (
free_clk_i => clk_125m_pllref_buf, arst_i => rstlogic_arst,
locked_i => rstlogic_arst_n, clks_i => rstlogic_clk_in,
clks_i => rstlogic_clk_in, rst_n_o => rstlogic_rst_out);
rstn_o => rstlogic_rst_out);
-- distribution of resets (already synchronized to their clock domains) -- distribution of resets (already synchronized to their clock domains)
rst_62m5_n <= rstlogic_rst_out(0); rst_62m5_n <= rstlogic_rst_out(0);
......
general-cores @ 6477d447
Subproject commit c322bafa6cd0d62ae1d2c487d77048b7ee926391 Subproject commit 6477d44787f40dcede9a4848a10ee00d47def6bf
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