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dd82e961
Commit
dd82e961
authored
Jun 20, 2017
by
Maciej Lipinski
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Plain Diff
[wbgen-ver] update streamers to have version of the wbgen registers
parent
42a6bf88
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4 changed files
with
88 additions
and
78 deletions
+88
-78
wr_streamers_wb.vhd
modules/wr_streamers/wr_streamers_wb.vhd
+46
-44
wr_streamers_wb.wb
modules/wr_streamers/wr_streamers_wb.wb
+1
-0
wr_streamers_wbgen2_pkg.vhd
modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd
+4
-1
wr_streamers_wb.svh
sim/wr_streamers_wb.svh
+37
-33
No files found.
modules/wr_streamers/wr_streamers_wb.vhd
View file @
dd82e961
This diff is collapsed.
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modules/wr_streamers/wr_streamers_wb.wb
View file @
dd82e961
...
@@ -28,6 +28,7 @@ peripheral {
...
@@ -28,6 +28,7 @@ peripheral {
-----------------------------------------------------------------";
-----------------------------------------------------------------";
prefix = "wr_streamers";
prefix = "wr_streamers";
hdl_entity = "wr_streamers_wb";
hdl_entity = "wr_streamers_wb";
version= 1;
reg {
reg {
name = "Statistics status and ctrl register";
name = "Statistics status and ctrl register";
...
...
modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd
View file @
dd82e961
...
@@ -3,7 +3,8 @@
...
@@ -3,7 +3,8 @@
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
-- File : wr_streamers_wbgen2_pkg.vhd
-- File : wr_streamers_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from wr_streamers_wb.wb
-- Author : auto-generated by wbgen2 from wr_streamers_wb.wb
-- Created : Tue May 16 18:11:13 2017
-- Created : Tue Jun 20 08:53:54 2017
-- Version : 0x00000001
-- Standard : VHDL'87
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_streamers_wb.wb
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_streamers_wb.wb
...
@@ -68,6 +69,7 @@ package wr_streamers_wbgen2_pkg is
...
@@ -68,6 +69,7 @@ package wr_streamers_wbgen2_pkg is
-- Output registers (WB slave -> user design)
-- Output registers (WB slave -> user design)
type
t_wr_streamers_out_registers
is
record
type
t_wr_streamers_out_registers
is
record
ver_id_o
:
std_logic_vector
(
31
downto
0
);
sscr1_rst_stats_o
:
std_logic
;
sscr1_rst_stats_o
:
std_logic
;
sscr1_rst_seq_id_o
:
std_logic
;
sscr1_rst_seq_id_o
:
std_logic
;
sscr1_snapshot_stats_o
:
std_logic
;
sscr1_snapshot_stats_o
:
std_logic
;
...
@@ -102,6 +104,7 @@ package wr_streamers_wbgen2_pkg is
...
@@ -102,6 +104,7 @@ package wr_streamers_wbgen2_pkg is
end
record
;
end
record
;
constant
c_wr_streamers_out_registers_init_value
:
t_wr_streamers_out_registers
:
=
(
constant
c_wr_streamers_out_registers_init_value
:
t_wr_streamers_out_registers
:
=
(
ver_id_o
=>
(
others
=>
'0'
),
sscr1_rst_stats_o
=>
'0'
,
sscr1_rst_stats_o
=>
'0'
,
sscr1_rst_seq_id_o
=>
'0'
,
sscr1_rst_seq_id_o
=>
'0'
,
sscr1_snapshot_stats_o
=>
'0'
,
sscr1_snapshot_stats_o
=>
'0'
,
...
...
sim/wr_streamers_wb.svh
View file @
dd82e961
`define
ADDR_WR_STREAMERS_SSCR1
8'h0
`define
WBGEN2_WR_STREAMERS_VERSION
32'h00000001
`define
ADDR_WR_STREAMERS_VER 8
'
h0
`define
WR_STREAMERS_VER_ID_OFFSET 0
`define
WR_STREAMERS_VER_ID 32
'
hffffffff
`define
ADDR_WR_STREAMERS_SSCR1 8
'
h4
`define
WR_STREAMERS_SSCR1_RST_STATS_OFFSET 0
`define
WR_STREAMERS_SSCR1_RST_STATS_OFFSET 0
`define
WR_STREAMERS_SSCR1_RST_STATS 32
'
h00000001
`define
WR_STREAMERS_SSCR1_RST_STATS 32
'
h00000001
`define
WR_STREAMERS_SSCR1_RST_SEQ_ID_OFFSET 1
`define
WR_STREAMERS_SSCR1_RST_SEQ_ID_OFFSET 1
...
@@ -9,99 +13,99 @@
...
@@ -9,99 +13,99 @@
`define
WR_STREAMERS_SSCR1_RX_LATENCY_ACC_OVERFLOW 32
'
h00000008
`define
WR_STREAMERS_SSCR1_RX_LATENCY_ACC_OVERFLOW 32
'
h00000008
`define
WR_STREAMERS_SSCR1_RST_TS_CYC_OFFSET 4
`define
WR_STREAMERS_SSCR1_RST_TS_CYC_OFFSET 4
`define
WR_STREAMERS_SSCR1_RST_TS_CYC 32
'
hfffffff0
`define
WR_STREAMERS_SSCR1_RST_TS_CYC 32
'
hfffffff0
`define
ADDR_WR_STREAMERS_SSCR2 8
'
h
4
`define
ADDR_WR_STREAMERS_SSCR2 8
'
h
8
`define
WR_STREAMERS_SSCR2_RST_TS_TAI_LSB_OFFSET 0
`define
WR_STREAMERS_SSCR2_RST_TS_TAI_LSB_OFFSET 0
`define
WR_STREAMERS_SSCR2_RST_TS_TAI_LSB 32
'
hffffffff
`define
WR_STREAMERS_SSCR2_RST_TS_TAI_LSB 32
'
hffffffff
`define
ADDR_WR_STREAMERS_SSCR3 8
'
h
8
`define
ADDR_WR_STREAMERS_SSCR3 8
'
h
c
`define
WR_STREAMERS_SSCR3_RST_TS_TAI_MSB_OFFSET 0
`define
WR_STREAMERS_SSCR3_RST_TS_TAI_MSB_OFFSET 0
`define
WR_STREAMERS_SSCR3_RST_TS_TAI_MSB 32
'
h000000ff
`define
WR_STREAMERS_SSCR3_RST_TS_TAI_MSB 32
'
h000000ff
`define
ADDR_WR_STREAMERS_RX_STAT0 8
'
h
c
`define
ADDR_WR_STREAMERS_RX_STAT0 8
'
h
10
`define
WR_STREAMERS_RX_STAT0_RX_LATENCY_MAX_OFFSET 0
`define
WR_STREAMERS_RX_STAT0_RX_LATENCY_MAX_OFFSET 0
`define
WR_STREAMERS_RX_STAT0_RX_LATENCY_MAX 32
'
h0fffffff
`define
WR_STREAMERS_RX_STAT0_RX_LATENCY_MAX 32
'
h0fffffff
`define
ADDR_WR_STREAMERS_RX_STAT1 8
'
h1
0
`define
ADDR_WR_STREAMERS_RX_STAT1 8
'
h1
4
`define
WR_STREAMERS_RX_STAT1_RX_LATENCY_MIN_OFFSET 0
`define
WR_STREAMERS_RX_STAT1_RX_LATENCY_MIN_OFFSET 0
`define
WR_STREAMERS_RX_STAT1_RX_LATENCY_MIN 32
'
h0fffffff
`define
WR_STREAMERS_RX_STAT1_RX_LATENCY_MIN 32
'
h0fffffff
`define
ADDR_WR_STREAMERS_TX_STAT2 8
'
h1
4
`define
ADDR_WR_STREAMERS_TX_STAT2 8
'
h1
8
`define
WR_STREAMERS_TX_STAT2_TX_SENT_CNT_LSB_OFFSET 0
`define
WR_STREAMERS_TX_STAT2_TX_SENT_CNT_LSB_OFFSET 0
`define
WR_STREAMERS_TX_STAT2_TX_SENT_CNT_LSB 32
'
hffffffff
`define
WR_STREAMERS_TX_STAT2_TX_SENT_CNT_LSB 32
'
hffffffff
`define
ADDR_WR_STREAMERS_TX_STAT3 8
'
h1
8
`define
ADDR_WR_STREAMERS_TX_STAT3 8
'
h1
c
`define
WR_STREAMERS_TX_STAT3_TX_SENT_CNT_MSB_OFFSET 0
`define
WR_STREAMERS_TX_STAT3_TX_SENT_CNT_MSB_OFFSET 0
`define
WR_STREAMERS_TX_STAT3_TX_SENT_CNT_MSB 32
'
hffffffff
`define
WR_STREAMERS_TX_STAT3_TX_SENT_CNT_MSB 32
'
hffffffff
`define
ADDR_WR_STREAMERS_RX_STAT4 8
'
h
1c
`define
ADDR_WR_STREAMERS_RX_STAT4 8
'
h
20
`define
WR_STREAMERS_RX_STAT4_RX_RCVD_CNT_LSB_OFFSET 0
`define
WR_STREAMERS_RX_STAT4_RX_RCVD_CNT_LSB_OFFSET 0
`define
WR_STREAMERS_RX_STAT4_RX_RCVD_CNT_LSB 32
'
hffffffff
`define
WR_STREAMERS_RX_STAT4_RX_RCVD_CNT_LSB 32
'
hffffffff
`define
ADDR_WR_STREAMERS_RX_STAT5 8
'
h2
0
`define
ADDR_WR_STREAMERS_RX_STAT5 8
'
h2
4
`define
WR_STREAMERS_RX_STAT5_RX_RCVD_CNT_MSB_OFFSET 0
`define
WR_STREAMERS_RX_STAT5_RX_RCVD_CNT_MSB_OFFSET 0
`define
WR_STREAMERS_RX_STAT5_RX_RCVD_CNT_MSB 32
'
hffffffff
`define
WR_STREAMERS_RX_STAT5_RX_RCVD_CNT_MSB 32
'
hffffffff
`define
ADDR_WR_STREAMERS_RX_STAT6 8
'
h2
4
`define
ADDR_WR_STREAMERS_RX_STAT6 8
'
h2
8
`define
WR_STREAMERS_RX_STAT6_RX_LOSS_CNT_LSB_OFFSET 0
`define
WR_STREAMERS_RX_STAT6_RX_LOSS_CNT_LSB_OFFSET 0
`define
WR_STREAMERS_RX_STAT6_RX_LOSS_CNT_LSB 32
'
hffffffff
`define
WR_STREAMERS_RX_STAT6_RX_LOSS_CNT_LSB 32
'
hffffffff
`define
ADDR_WR_STREAMERS_RX_STAT7 8
'
h2
8
`define
ADDR_WR_STREAMERS_RX_STAT7 8
'
h2
c
`define
WR_STREAMERS_RX_STAT7_RX_LOSS_CNT_MSB_OFFSET 0
`define
WR_STREAMERS_RX_STAT7_RX_LOSS_CNT_MSB_OFFSET 0
`define
WR_STREAMERS_RX_STAT7_RX_LOSS_CNT_MSB 32
'
hffffffff
`define
WR_STREAMERS_RX_STAT7_RX_LOSS_CNT_MSB 32
'
hffffffff
`define
ADDR_WR_STREAMERS_RX_STAT8 8
'
h
2c
`define
ADDR_WR_STREAMERS_RX_STAT8 8
'
h
30
`define
WR_STREAMERS_RX_STAT8_RX_LOST_BLOCK_CNT_LSB_OFFSET 0
`define
WR_STREAMERS_RX_STAT8_RX_LOST_BLOCK_CNT_LSB_OFFSET 0
`define
WR_STREAMERS_RX_STAT8_RX_LOST_BLOCK_CNT_LSB 32
'
hffffffff
`define
WR_STREAMERS_RX_STAT8_RX_LOST_BLOCK_CNT_LSB 32
'
hffffffff
`define
ADDR_WR_STREAMERS_RX_STAT9 8
'
h3
0
`define
ADDR_WR_STREAMERS_RX_STAT9 8
'
h3
4
`define
WR_STREAMERS_RX_STAT9_RX_LOST_BLOCK_CNT_MSB_OFFSET 0
`define
WR_STREAMERS_RX_STAT9_RX_LOST_BLOCK_CNT_MSB_OFFSET 0
`define
WR_STREAMERS_RX_STAT9_RX_LOST_BLOCK_CNT_MSB 32
'
hffffffff
`define
WR_STREAMERS_RX_STAT9_RX_LOST_BLOCK_CNT_MSB 32
'
hffffffff
`define
ADDR_WR_STREAMERS_RX_STAT10 8
'
h3
4
`define
ADDR_WR_STREAMERS_RX_STAT10 8
'
h3
8
`define
WR_STREAMERS_RX_STAT10_RX_LATENCY_ACC_LSB_OFFSET 0
`define
WR_STREAMERS_RX_STAT10_RX_LATENCY_ACC_LSB_OFFSET 0
`define
WR_STREAMERS_RX_STAT10_RX_LATENCY_ACC_LSB 32
'
hffffffff
`define
WR_STREAMERS_RX_STAT10_RX_LATENCY_ACC_LSB 32
'
hffffffff
`define
ADDR_WR_STREAMERS_RX_STAT11 8
'
h3
8
`define
ADDR_WR_STREAMERS_RX_STAT11 8
'
h3
c
`define
WR_STREAMERS_RX_STAT11_RX_LATENCY_ACC_MSB_OFFSET 0
`define
WR_STREAMERS_RX_STAT11_RX_LATENCY_ACC_MSB_OFFSET 0
`define
WR_STREAMERS_RX_STAT11_RX_LATENCY_ACC_MSB 32
'
hffffffff
`define
WR_STREAMERS_RX_STAT11_RX_LATENCY_ACC_MSB 32
'
hffffffff
`define
ADDR_WR_STREAMERS_RX_STAT12 8
'
h
3c
`define
ADDR_WR_STREAMERS_RX_STAT12 8
'
h
40
`define
WR_STREAMERS_RX_STAT12_RX_LATENCY_ACC_CNT_LSB_OFFSET 0
`define
WR_STREAMERS_RX_STAT12_RX_LATENCY_ACC_CNT_LSB_OFFSET 0
`define
WR_STREAMERS_RX_STAT12_RX_LATENCY_ACC_CNT_LSB 32
'
hffffffff
`define
WR_STREAMERS_RX_STAT12_RX_LATENCY_ACC_CNT_LSB 32
'
hffffffff
`define
ADDR_WR_STREAMERS_RX_STAT13 8
'
h4
0
`define
ADDR_WR_STREAMERS_RX_STAT13 8
'
h4
4
`define
WR_STREAMERS_RX_STAT13_RX_LATENCY_ACC_CNT_MSB_OFFSET 0
`define
WR_STREAMERS_RX_STAT13_RX_LATENCY_ACC_CNT_MSB_OFFSET 0
`define
WR_STREAMERS_RX_STAT13_RX_LATENCY_ACC_CNT_MSB 32
'
hffffffff
`define
WR_STREAMERS_RX_STAT13_RX_LATENCY_ACC_CNT_MSB 32
'
hffffffff
`define
ADDR_WR_STREAMERS_TX_CFG0 8
'
h4
4
`define
ADDR_WR_STREAMERS_TX_CFG0 8
'
h4
8
`define
WR_STREAMERS_TX_CFG0_ETHERTYPE_OFFSET 0
`define
WR_STREAMERS_TX_CFG0_ETHERTYPE_OFFSET 0
`define
WR_STREAMERS_TX_CFG0_ETHERTYPE 32
'
h0000ffff
`define
WR_STREAMERS_TX_CFG0_ETHERTYPE 32
'
h0000ffff
`define
ADDR_WR_STREAMERS_TX_CFG1 8
'
h4
8
`define
ADDR_WR_STREAMERS_TX_CFG1 8
'
h4
c
`define
WR_STREAMERS_TX_CFG1_MAC_LOCAL_LSB_OFFSET 0
`define
WR_STREAMERS_TX_CFG1_MAC_LOCAL_LSB_OFFSET 0
`define
WR_STREAMERS_TX_CFG1_MAC_LOCAL_LSB 32
'
hffffffff
`define
WR_STREAMERS_TX_CFG1_MAC_LOCAL_LSB 32
'
hffffffff
`define
ADDR_WR_STREAMERS_TX_CFG2 8
'
h
4c
`define
ADDR_WR_STREAMERS_TX_CFG2 8
'
h
50
`define
WR_STREAMERS_TX_CFG2_MAC_LOCAL_MSB_OFFSET 0
`define
WR_STREAMERS_TX_CFG2_MAC_LOCAL_MSB_OFFSET 0
`define
WR_STREAMERS_TX_CFG2_MAC_LOCAL_MSB 32
'
h0000ffff
`define
WR_STREAMERS_TX_CFG2_MAC_LOCAL_MSB 32
'
h0000ffff
`define
ADDR_WR_STREAMERS_TX_CFG3 8
'
h5
0
`define
ADDR_WR_STREAMERS_TX_CFG3 8
'
h5
4
`define
WR_STREAMERS_TX_CFG3_MAC_TARGET_LSB_OFFSET 0
`define
WR_STREAMERS_TX_CFG3_MAC_TARGET_LSB_OFFSET 0
`define
WR_STREAMERS_TX_CFG3_MAC_TARGET_LSB 32
'
hffffffff
`define
WR_STREAMERS_TX_CFG3_MAC_TARGET_LSB 32
'
hffffffff
`define
ADDR_WR_STREAMERS_TX_CFG4 8
'
h5
4
`define
ADDR_WR_STREAMERS_TX_CFG4 8
'
h5
8
`define
WR_STREAMERS_TX_CFG4_MAC_TARGET_MSB_OFFSET 0
`define
WR_STREAMERS_TX_CFG4_MAC_TARGET_MSB_OFFSET 0
`define
WR_STREAMERS_TX_CFG4_MAC_TARGET_MSB 32
'
h0000ffff
`define
WR_STREAMERS_TX_CFG4_MAC_TARGET_MSB 32
'
h0000ffff
`define
ADDR_WR_STREAMERS_TX_CFG5 8
'
h5
8
`define
ADDR_WR_STREAMERS_TX_CFG5 8
'
h5
c
`define
WR_STREAMERS_TX_CFG5_QTAG_ENA_OFFSET 0
`define
WR_STREAMERS_TX_CFG5_QTAG_ENA_OFFSET 0
`define
WR_STREAMERS_TX_CFG5_QTAG_ENA 32
'
h00000001
`define
WR_STREAMERS_TX_CFG5_QTAG_ENA 32
'
h00000001
`define
WR_STREAMERS_TX_CFG5_QTAG_VID_OFFSET 8
`define
WR_STREAMERS_TX_CFG5_QTAG_VID_OFFSET 8
`define
WR_STREAMERS_TX_CFG5_QTAG_VID 32
'
h000fff00
`define
WR_STREAMERS_TX_CFG5_QTAG_VID 32
'
h000fff00
`define
WR_STREAMERS_TX_CFG5_QTAG_PRIO_OFFSET 24
`define
WR_STREAMERS_TX_CFG5_QTAG_PRIO_OFFSET 24
`define
WR_STREAMERS_TX_CFG5_QTAG_PRIO 32
'
h07000000
`define
WR_STREAMERS_TX_CFG5_QTAG_PRIO 32
'
h07000000
`define
ADDR_WR_STREAMERS_RX_CFG0 8
'
h
5c
`define
ADDR_WR_STREAMERS_RX_CFG0 8
'
h
60
`define
WR_STREAMERS_RX_CFG0_ETHERTYPE_OFFSET 0
`define
WR_STREAMERS_RX_CFG0_ETHERTYPE_OFFSET 0
`define
WR_STREAMERS_RX_CFG0_ETHERTYPE 32
'
h0000ffff
`define
WR_STREAMERS_RX_CFG0_ETHERTYPE 32
'
h0000ffff
`define
WR_STREAMERS_RX_CFG0_ACCEPT_BROADCAST_OFFSET 16
`define
WR_STREAMERS_RX_CFG0_ACCEPT_BROADCAST_OFFSET 16
`define
WR_STREAMERS_RX_CFG0_ACCEPT_BROADCAST 32
'
h00010000
`define
WR_STREAMERS_RX_CFG0_ACCEPT_BROADCAST 32
'
h00010000
`define
WR_STREAMERS_RX_CFG0_FILTER_REMOTE_OFFSET 17
`define
WR_STREAMERS_RX_CFG0_FILTER_REMOTE_OFFSET 17
`define
WR_STREAMERS_RX_CFG0_FILTER_REMOTE 32
'
h00020000
`define
WR_STREAMERS_RX_CFG0_FILTER_REMOTE 32
'
h00020000
`define
ADDR_WR_STREAMERS_RX_CFG1 8
'
h6
0
`define
ADDR_WR_STREAMERS_RX_CFG1 8
'
h6
4
`define
WR_STREAMERS_RX_CFG1_MAC_LOCAL_LSB_OFFSET 0
`define
WR_STREAMERS_RX_CFG1_MAC_LOCAL_LSB_OFFSET 0
`define
WR_STREAMERS_RX_CFG1_MAC_LOCAL_LSB 32
'
hffffffff
`define
WR_STREAMERS_RX_CFG1_MAC_LOCAL_LSB 32
'
hffffffff
`define
ADDR_WR_STREAMERS_RX_CFG2 8
'
h6
4
`define
ADDR_WR_STREAMERS_RX_CFG2 8
'
h6
8
`define
WR_STREAMERS_RX_CFG2_MAC_LOCAL_MSB_OFFSET 0
`define
WR_STREAMERS_RX_CFG2_MAC_LOCAL_MSB_OFFSET 0
`define
WR_STREAMERS_RX_CFG2_MAC_LOCAL_MSB 32
'
h0000ffff
`define
WR_STREAMERS_RX_CFG2_MAC_LOCAL_MSB 32
'
h0000ffff
`define
ADDR_WR_STREAMERS_RX_CFG3 8
'
h6
8
`define
ADDR_WR_STREAMERS_RX_CFG3 8
'
h6
c
`define
WR_STREAMERS_RX_CFG3_MAC_REMOTE_LSB_OFFSET 0
`define
WR_STREAMERS_RX_CFG3_MAC_REMOTE_LSB_OFFSET 0
`define
WR_STREAMERS_RX_CFG3_MAC_REMOTE_LSB 32
'
hffffffff
`define
WR_STREAMERS_RX_CFG3_MAC_REMOTE_LSB 32
'
hffffffff
`define
ADDR_WR_STREAMERS_RX_CFG4 8
'
h
6c
`define
ADDR_WR_STREAMERS_RX_CFG4 8
'
h
70
`define
WR_STREAMERS_RX_CFG4_MAC_REMOTE_MSB_OFFSET 0
`define
WR_STREAMERS_RX_CFG4_MAC_REMOTE_MSB_OFFSET 0
`define
WR_STREAMERS_RX_CFG4_MAC_REMOTE_MSB 32
'
h0000ffff
`define
WR_STREAMERS_RX_CFG4_MAC_REMOTE_MSB 32
'
h0000ffff
`define
ADDR_WR_STREAMERS_RX_CFG5 8
'
h7
0
`define
ADDR_WR_STREAMERS_RX_CFG5 8
'
h7
4
`define
WR_STREAMERS_RX_CFG5_FIXED_LATENCY_OFFSET 0
`define
WR_STREAMERS_RX_CFG5_FIXED_LATENCY_OFFSET 0
`define
WR_STREAMERS_RX_CFG5_FIXED_LATENCY 32
'
h0fffffff
`define
WR_STREAMERS_RX_CFG5_FIXED_LATENCY 32
'
h0fffffff
`define
ADDR_WR_STREAMERS_CFG 8
'
h7
4
`define
ADDR_WR_STREAMERS_CFG 8
'
h7
8
`define
WR_STREAMERS_CFG_OR_TX_ETHTYPE_OFFSET 0
`define
WR_STREAMERS_CFG_OR_TX_ETHTYPE_OFFSET 0
`define
WR_STREAMERS_CFG_OR_TX_ETHTYPE 32
'
h00000001
`define
WR_STREAMERS_CFG_OR_TX_ETHTYPE 32
'
h00000001
`define
WR_STREAMERS_CFG_OR_TX_MAC_LOC_OFFSET 1
`define
WR_STREAMERS_CFG_OR_TX_MAC_LOC_OFFSET 1
...
@@ -122,12 +126,12 @@
...
@@ -122,12 +126,12 @@
`define
WR_STREAMERS_CFG_OR_RX_FTR_REMOTE 32
'
h00100000
`define
WR_STREAMERS_CFG_OR_RX_FTR_REMOTE 32
'
h00100000
`define
WR_STREAMERS_CFG_OR_RX_FIX_LAT_OFFSET 21
`define
WR_STREAMERS_CFG_OR_RX_FIX_LAT_OFFSET 21
`define
WR_STREAMERS_CFG_OR_RX_FIX_LAT 32
'
h00200000
`define
WR_STREAMERS_CFG_OR_RX_FIX_LAT 32
'
h00200000
`define
ADDR_WR_STREAMERS_DBG_CTRL 8
'
h7
8
`define
ADDR_WR_STREAMERS_DBG_CTRL 8
'
h7
c
`define
WR_STREAMERS_DBG_CTRL_MUX_OFFSET 0
`define
WR_STREAMERS_DBG_CTRL_MUX_OFFSET 0
`define
WR_STREAMERS_DBG_CTRL_MUX 32
'
h00000001
`define
WR_STREAMERS_DBG_CTRL_MUX 32
'
h00000001
`define
WR_STREAMERS_DBG_CTRL_START_BYTE_OFFSET 8
`define
WR_STREAMERS_DBG_CTRL_START_BYTE_OFFSET 8
`define
WR_STREAMERS_DBG_CTRL_START_BYTE 32
'
h0000ff00
`define
WR_STREAMERS_DBG_CTRL_START_BYTE 32
'
h0000ff00
`define
ADDR_WR_STREAMERS_DBG_DATA 8
'
h
7c
`define
ADDR_WR_STREAMERS_DBG_DATA 8
'
h
80
`define
ADDR_WR_STREAMERS_DUMMY 8
'
h8
0
`define
ADDR_WR_STREAMERS_DUMMY 8
'
h8
4
`define
WR_STREAMERS_DUMMY_DUMMY_OFFSET 0
`define
WR_STREAMERS_DUMMY_DUMMY_OFFSET 0
`define
WR_STREAMERS_DUMMY_DUMMY 32
'
hffffffff
`define
WR_STREAMERS_DUMMY_DUMMY 32
'
hffffffff
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