Skip to content

W
White Rabbit core collection
Commit e5246fa3 authored by A. Hahn's avatar A. Hahn
Browse files
Options

platform: added cmu pll for arria 10

parent 72021622
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 5115 additions and 2 deletions
platform/altera/wr_altera_pkg.vhd
View file @ e5246fa3
......@@ -225,6 +225,7 @@ package wr_altera_pkg is
generic (
g_use_atx_pll : boolean := true;
g_use_cmu_pll : boolean := false;
g_use_simple_wa : boolean := false;
g_use_det_phy : boolean := true;
g_use_sfp_los_rst : boolean := true;
g_use_tx_lcr_dbg : boolean := false;
......@@ -423,6 +424,16 @@ package wr_altera_pkg is
);
end component wr_arria10_e3p1_atx_pll;
component wr_arria10_e3p1_cmu_pll is
port (
pll_powerdown : in std_logic := 'X';
pll_refclk0 : in std_logic := 'X';
tx_serial_clk : out std_logic;
pll_locked : out std_logic;
pll_cal_busy : out std_logic
);
end component wr_arria10_e3p1_cmu_pll;
component wr_arria10_scu4_atx_pll is
port (
pll_refclk0 : in std_logic := 'X';
......
platform/altera/wr_arria10_e3p1_phy/wr_arria10_e3p1_cmu_pll/.qsys_edit/preferences.xml
View file @ e5246fa3
......@@ -7,6 +7,7 @@
<irq preferredWidth="34" />
</columns>
</systemtable>
<library expandedCategories="Library,Project" />
<window width="1100" height="800" x="1745" y="1408" />
<library expandedCategories="Project,Library" />
<window width="1667" height="1170" x="1440" y="1120" />
<generation path="" synthesis="VHDL" block_symbol_file="0" />
</preferences>
platform/altera/wr_arria10_e3p1_phy/wr_arria10_e3p1_cmu_pll/.qsys_edit/wr_arria10_e3p1_cmu_pll_schematic.nlv 0 → 100644
View file @ e5246fa3
# # File gsaved with Nlview version 6.3.8 2013-12-19 bk=1.2992 VDI=34 GEI=35
#
preplace inst wr_arria10_e3p1_cmu_pll -pg 1 -lvl 1 -y 40 -regy -20
preplace inst wr_arria10_e3p1_cmu_pll.xcvr_cdr_pll_a10_0 -pg 1 -lvl 1 -y 30
preplace netloc EXPORT<net_container>wr_arria10_e3p1_cmu_pll</net_container>(SLAVE)xcvr_cdr_pll_a10_0.pll_locked,(SLAVE)wr_arria10_e3p1_cmu_pll.pll_locked) 1 0 1 NJ
preplace netloc EXPORT<net_container>wr_arria10_e3p1_cmu_pll</net_container>(MASTER)xcvr_cdr_pll_a10_0.tx_serial_clk,(MASTER)wr_arria10_e3p1_cmu_pll.tx_serial_clk) 1 1 1 N
preplace netloc EXPORT<net_container>wr_arria10_e3p1_cmu_pll</net_container>(SLAVE)xcvr_cdr_pll_a10_0.pll_refclk0,(SLAVE)wr_arria10_e3p1_cmu_pll.pll_refclk0) 1 0 1 NJ
preplace netloc EXPORT<net_container>wr_arria10_e3p1_cmu_pll</net_container>(SLAVE)wr_arria10_e3p1_cmu_pll.pll_cal_busy,(SLAVE)xcvr_cdr_pll_a10_0.pll_cal_busy) 1 0 1 NJ
preplace netloc EXPORT<net_container>wr_arria10_e3p1_cmu_pll</net_container>(SLAVE)xcvr_cdr_pll_a10_0.pll_powerdown,(SLAVE)wr_arria10_e3p1_cmu_pll.pll_powerdown) 1 0 1 NJ
levelinfo -pg 1 0 90 430
levelinfo -hier wr_arria10_e3p1_cmu_pll 100 130 320
platform/altera/wr_arria10_e3p1_phy/wr_arria10_e3p1_cmu_pll/wr_arria10_e3p1_cmu_pll.qsys 0 → 100644
View file @ e5246fa3
<?xml version="1.0" encoding="UTF-8"?>
<system name="$${FILENAME}">
<component
name="$${FILENAME}"
displayName="$${FILENAME}"
version="1.0"
description=""
tags="INTERNAL_COMPONENT=true"
categories="System" />
<parameter name="bonusData"><![CDATA[bonusData
{
element xcvr_cdr_pll_a10_0
{
datum _sortIndex
{
value = "0";
type = "int";
}
}
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
<parameter name="device" value="10AX115S2F45I1SG" />
<parameter name="deviceFamily" value="Arria 10" />
<parameter name="deviceSpeedGrade" value="1" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="true" />
<parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="0" />
<parameter name="testBenchDutName" value="" />
<parameter name="timeStamp" value="0" />
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface
name="pll_cal_busy"
internal="xcvr_cdr_pll_a10_0.pll_cal_busy"
type="conduit"
dir="end">
<port name="pll_cal_busy" internal="pll_cal_busy" />
</interface>
<interface
name="pll_locked"
internal="xcvr_cdr_pll_a10_0.pll_locked"
type="conduit"
dir="end">
<port name="pll_locked" internal="pll_locked" />
</interface>
<interface
name="pll_powerdown"
internal="xcvr_cdr_pll_a10_0.pll_powerdown"
type="conduit"
dir="end">
<port name="pll_powerdown" internal="pll_powerdown" />
</interface>
<interface
name="pll_refclk0"
internal="xcvr_cdr_pll_a10_0.pll_refclk0"
type="clock"
dir="end">
<port name="pll_refclk0" internal="pll_refclk0" />
</interface>
<interface
name="tx_serial_clk"
internal="xcvr_cdr_pll_a10_0.tx_serial_clk"
type="hssi_serial_clock"
dir="start">
<port name="tx_serial_clk" internal="tx_serial_clk" />
</interface>
<module
name="xcvr_cdr_pll_a10_0"
kind="altera_xcvr_cdr_pll_a10"
version="18.1"
enabled="1"
autoexport="1">
<parameter name="base_device" value="NIGHTFURY5" />
<parameter name="bw_sel" value="Medium" />
<parameter name="cdr_pll_cgb_div" value="1" />
<parameter name="cdr_pll_initial_settings" value="true" />
<parameter name="cdr_pll_is_cascaded_pll" value="false" />
<parameter name="cdr_pll_optimal" value="false" />
<parameter name="device" value="10AX115S2F45I1SG" />
<parameter name="device_family" value="Arria 10" />
<parameter name="enable_analog_resets" value="0" />
<parameter name="enable_pll_reconfig" value="0" />
<parameter name="generate_add_hdl_instance_example" value="0" />
<parameter name="generate_docs" value="0" />
<parameter name="gui_tx_pll_prot_mode" value="Basic" />
<parameter name="manual_counters" value="" />
<parameter name="message_level" value="error" />
<parameter name="output_clock_frequency" value="2500" />
<parameter name="rcfg_debug" value="0" />
<parameter name="rcfg_enable_avmm_busy_port" value="0" />
<parameter name="rcfg_file_prefix">altera_xcvr_cdr_pll_a10</parameter>
<parameter name="rcfg_h_file_enable" value="0" />
<parameter name="rcfg_jtag_enable" value="0" />
<parameter name="rcfg_mif_file_enable" value="0" />
<parameter name="rcfg_separate_avmm_busy" value="0" />
<parameter name="rcfg_sv_file_enable" value="0" />
<parameter name="rcfg_txt_file_enable" value="0" />
<parameter name="refclk_cnt" value="1" />
<parameter name="refclk_index" value="0" />
<parameter name="refclk_select_mux_powerdown_mode" value="powerup" />
<parameter name="reference_clock_frequency" value="125.0" />
<parameter name="select_manual_config" value="false" />
<parameter name="set_altera_xcvr_cdr_pll_a10_calibration_en" value="1" />
<parameter name="set_capability_reg_enable" value="0" />
<parameter name="set_csr_soft_logic_enable" value="0" />
<parameter name="set_user_identifier" value="0" />
<parameter name="support_mode" value="user_mode" />
</module>
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
<interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
</system>
platform/altera/wr_arria10_e3p1_phy/wr_arria10_e3p1_cmu_pll/wr_arria10_e3p1_cmu_pll/altera_xcvr_cdr_pll_a10_181/synth/a10_avmm_h.sv 0 → 100644
View file @ e5246fa3
// (C) 2001-2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps/1 ps
package a10_avmm_h;
// localparam to define unused bus
localparam RD_UNUSED = 8'h0;
// localparams for common capability registers
localparam A10_XR_ADDR_ID_0 = 9'h0;
localparam A10_XR_ADDR_ID_1 = 9'h1;
localparam A10_XR_ADDR_ID_2 = 9'h2;
localparam A10_XR_ADDR_ID_3 = 9'h3;
localparam A10_XR_ADDR_STATUS_EN = 9'h4;
localparam A10_XR_ADDR_CONTROL_EN = 9'h5;
// Reserve Address 9'h6 to 9'hF for common capablities
// native phy capability
localparam A10_XR_ADDR_NAT_CHNLS = 9'h10;
localparam A10_XR_ADDR_NAT_CHNL_NUM = 9'h11;
localparam A10_XR_ADDR_NAT_DUPLEX = 9'h12;
localparam A10_XR_ADDR_NAT_PRBS_EN = 9'h13;
localparam A10_XR_ADDR_NAT_ODI_EN = 9'h14;
// pll ip capability
localparam A10_XR_ADDR_PLL_MCGB_EN = 9'h10;
// localparams for csr for pll locked and cal busy
localparam A10_XR_ADDR_GP_PLL_LOCK = 9'h80;
localparam A10_XR_OFFSET_GP_LOCK = 0;
localparam A10_XR_OFFSET_GP_CAL_BUSY = 1;
localparam A10_XR_OFFSET_GP_AVMM_BUSY = 2;
localparam A10_XR_OFFSET_LOCK_UNUSED = 3;
localparam A10_XR_LOCK_UNUSED_LEN = 5;
// localparams for pll powerdown
localparam A10_XR_ADDR_GP_PLL_RST = 9'hE0;
localparam A10_XR_OFFSET_PLL_RST = 0;
localparam A10_XR_OFFSET_PLL_RST_OVR = 1;
localparam A10_XR_OFFSET_PLL_RST_UNUSED = 2;
localparam A10_XR_PLL_RST_UNUSED_LEN = 6;
// localparams for csr for lock to ref and lock to data
localparam A10_XR_ADDR_GP_RD_LTR = 9'h80;
localparam A10_XR_OFFSET_RD_LTD = 0;
localparam A10_XR_OFFSET_RD_LTR = 1;
localparam A10_XR_OFFSET_LTR_UNUSED = 2;
localparam A10_XR_LTR_UNUSED_LEN = 6;
// localparams for csr for cal busy
localparam A10_XR_ADDR_GP_CAL_BUSY = 9'h81;
localparam A10_XR_OFFSET_TX_CAL_BUSY = 0;
localparam A10_XR_OFFSET_RX_CAL_BUSY = 1;
localparam A10_XR_OFFSET_AVMM_BUSY = 2;
localparam A10_XR_OFFSET_CAL_DUMMY = 3;
localparam A10_XR_OFFSET_TX_CAL_MASK = 4;
localparam A10_XR_OFFSET_RX_CAL_MASK = 5;
localparam A10_XR_OFFSET_CAL_UNUSED = 6;
localparam A10_XR_CAL_UNUSED_LEN = 2;
// localparams for setting lock to ref and lock to data
localparam A10_XR_ADDR_GP_SET_LTR = 9'hE0;
localparam A10_XR_OFFSET_SET_LTD = 0;
localparam A10_XR_OFFSET_SET_LTR = 1;
localparam A10_XR_OFFSET_SET_LTD_OVR = 2;
localparam A10_XR_OFFSET_SET_LTR_OVR = 3;
localparam A10_XR_OFFSET_SET_LTR_UNUSED = 4;
localparam A10_XR_SET_LTR_UNUSED_LEN = 4;
// localparams for setting loopback
localparam A10_XR_ADDR_GP_LPBK = 9'hE1;
localparam A10_XR_OFFSET_LPBK = 0;
localparam A10_XR_OFFSET_LPBK_UNUSED = 1;
localparam A10_XR_LPBK_UNUSED_LEN = 7;
// localparams for setting channel resets
localparam A10_XR_ADDR_CHNL_RESET = 9'hE2;
localparam A10_XR_OFFSET_RX_ANA = 0;
localparam A10_XR_OFFSET_RX_DIG = 1;
localparam A10_XR_OFFSET_TX_ANA = 2;
localparam A10_XR_OFFSET_TX_DIG = 3;
localparam A10_XR_OFFSET_RX_ANA_OVR = 4;
localparam A10_XR_OFFSET_RX_DIG_OVR = 5;
localparam A10_XR_OFFSET_TX_ANA_OVR = 6;
localparam A10_XR_OFFSET_TX_DIG_OVR = 7;
// localparams for prbs addresses
localparam A10_XR_ADDR_PRBS_CTRL = 9'h100;
localparam A10_XR_ADDR_PRBS_ERR_0 = 9'h101;
localparam A10_XR_ADDR_PRBS_ERR_1 = 9'h102;
localparam A10_XR_ADDR_PRBS_ERR_2 = 9'h103;
localparam A10_XR_ADDR_PRBS_ERR_3 = 9'h104;
localparam A10_XR_ADDR_PRBS_ERR_4 = 9'h105;
localparam A10_XR_ADDR_PRBS_ERR_5 = 9'h106;
localparam A10_XR_ADDR_PRBS_ERR_6 = 9'h107;
localparam A10_XR_ADDR_PRBS_BIT_0 = 9'h10D;
localparam A10_XR_ADDR_PRBS_BIT_1 = 9'h10E;
localparam A10_XR_ADDR_PRBS_BIT_2 = 9'h10F;
localparam A10_XR_ADDR_PRBS_BIT_3 = 9'h110;
localparam A10_XR_ADDR_PRBS_BIT_4 = 9'h111;
localparam A10_XR_ADDR_PRBS_BIT_5 = 9'h112;
localparam A10_XR_ADDR_PRBS_BIT_6 = 9'h113;
// localparams for prbs bit offsets
localparam A10_XR_OFFSET_PRBS_EN = 0;
localparam A10_XR_OFFSET_PRBS_RESET = 1;
localparam A10_XR_OFFSET_PRBS_SNAP = 2;
localparam A10_XR_OFFSET_PRBS_DONE = 3;
localparam A10_XR_OFFSET_PRBS_UNUSED = 4;
localparam A10_XR_PRBS_UNUSED_LEN = 4;
// localparams for odi addresses
localparam A10_XR_ADDR_ODI_CTRL = 9'h120;
localparam A10_XR_ADDR_ODI_ERR_0 = 9'h121;
localparam A10_XR_ADDR_ODI_ERR_1 = 9'h122;
localparam A10_XR_ADDR_ODI_ERR_2 = 9'h123;
localparam A10_XR_ADDR_ODI_ERR_3 = 9'h124;
localparam A10_XR_ADDR_ODI_ERR_4 = 9'h125;
localparam A10_XR_ADDR_ODI_ERR_5 = 9'h126;
localparam A10_XR_ADDR_ODI_ERR_6 = 9'h127;
localparam A10_XR_ADDR_ODI_BIT_0 = 9'h12D;
localparam A10_XR_ADDR_ODI_BIT_1 = 9'h12E;
localparam A10_XR_ADDR_ODI_BIT_2 = 9'h12F;
localparam A10_XR_ADDR_ODI_BIT_3 = 9'h130;
localparam A10_XR_ADDR_ODI_BIT_4 = 9'h131;
localparam A10_XR_ADDR_ODI_BIT_5 = 9'h132;
localparam A10_XR_ADDR_ODI_BIT_6 = 9'h133;
// localparams for odi bit offsets
localparam A10_XR_OFFSET_ODI_EN = 0;
localparam A10_XR_OFFSET_ODI_RESET = 1;
localparam A10_XR_OFFSET_ODI_SNAP = 2;
localparam A10_XR_OFFSET_ODI_DONE = 3;
localparam A10_XR_OFFSET_ODI_UNUSED = 4;
localparam A10_XR_ODI_UNUSED_LEN = 4;
// localparams for embedded reconfig addresses
// Control reg and offsets
localparam A10_XR_ADDR_EMBED_RCFG_CTRL = 9'h140;
localparam A10_XR_OFFSET_EMBED_RCFG_CFG_SEL = 0;
localparam A10_XR_EMBED_RCFG_CFG_SEL_LEN = 6; //bits [5:0] are alloted for cfg_sel even though GUI currently only supports upto 8 profiles.
localparam A10_XR_OFFSET_EMBED_RCFG_BCAST_EN = 6;
localparam A10_XR_OFFSET_EMBED_RCFG_CFG_LOAD = 7;
// Status reg and offsets
localparam A10_XR_ADDR_EMBED_RCFG_STATUS = 9'h141;
localparam A10_XR_OFFSET_EMBED_RCFG_STRM_BUSY = 0;
endpackage
platform/altera/wr_arria10_e3p1_phy/wr_arria10_e3p1_cmu_pll/wr_arria10_e3p1_cmu_pll/altera_xcvr_cdr_pll_a10_181/synth/alt_xcvr_native_avmm_nf.sv 0 → 100644
View file @ e5246fa3
// (C) 2001-2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps/1 ps
module alt_xcvr_native_avmm_nf #(
parameter CHANNELS = 1,
parameter RECONFIG_SHARED = 0,
parameter JTAG_ENABLED = 0,
parameter ADME_SLAVE_MAP = "altera_xcvr_native_a10",
parameter ADME_ASSGN_MAP = " ",
// The following are not intended to be directly set
parameter IFACES = RECONFIG_SHARED ? 1 : CHANNELS,
parameter ADDR_BITS = 9,
parameter SEL_BITS = (RECONFIG_SHARED ? clogb2(CHANNELS-1) : 0)
) (
// Reconfig interface ports
input wire [IFACES-1:0] reconfig_clk,
input wire [IFACES-1:0] reconfig_reset,
input wire [IFACES-1:0] reconfig_write,
input wire [IFACES-1:0] reconfig_read,
input wire [IFACES*(ADDR_BITS+SEL_BITS)-1:0] reconfig_address,
input wire [IFACES*32-1:0] reconfig_writedata,
output wire [IFACES*32-1:0] reconfig_readdata,
output wire [IFACES-1:0] reconfig_waitrequest,
// AVMM ports to transceiver
output wire [CHANNELS-1:0] avmm_clk,
output wire [CHANNELS-1:0] avmm_reset,
output wire [CHANNELS-1:0] avmm_write,
output wire [CHANNELS-1:0] avmm_read,
output wire [CHANNELS*ADDR_BITS-1:0] avmm_address,
output wire [CHANNELS*8-1:0] avmm_writedata,
input wire [CHANNELS*8-1:0] avmm_readdata,
input wire [CHANNELS-1:0] avmm_waitrequest
);
// AVMM connections from the interface sharing logic to the JTAG arbitration
wire [IFACES-1:0] arb_write;
wire [IFACES-1:0] arb_read;
wire [IFACES*(ADDR_BITS+SEL_BITS)-1:0] arb_address;
wire [IFACES*32-1:0] arb_writedata;
wire [IFACES*32-1:0] arb_readdata;
wire [IFACES-1:0] arb_waitrequest;
// Set the slave type for the ADME. Since the span neesd to be a string, 2^(total addr_bits) will
// give the max value, however since the adme uses byte alignment, shift the span by two bits.
localparam set_slave_span = int2str(2**(ADDR_BITS+SEL_BITS+2));
localparam set_slave_map = {"{typeName ",ADME_SLAVE_MAP," address 0x0 span ",set_slave_span," hpath {}",ADME_ASSGN_MAP,"}"};
genvar ig;
//***************************************************************************
//********************** Embedded JTAG Debug Master *************************
generate
if(!JTAG_ENABLED) begin : g_no_jtag
assign arb_address = reconfig_address;
assign arb_write = reconfig_write;
assign arb_read = reconfig_read;
assign arb_writedata = reconfig_writedata;
assign reconfig_readdata = arb_readdata;
assign reconfig_waitrequest= arb_waitrequest;
end else begin : g_jtag
reg sel; // Arbitration bit
wire [(ADDR_BITS+SEL_BITS)-1:0] jtag_address;
wire [31:0] jtag_readdata;
wire jtag_read;
wire jtag_write;
wire [31:0] jtag_writedata;
wire jtag_waitrequest;
wire jtag_readdatavalid;
// When doing RTL sims, remove the altera_debug_master_endpoint, as
// there is no RTL simulation model. Pre and Post Fit sims are ok.
`ifdef ALTERA_RESERVED_QIS
altera_debug_master_endpoint
#(
.ADDR_WIDTH ( (ADDR_BITS+SEL_BITS) ),
.DATA_WIDTH ( 32 ),
.HAS_RDV ( 0 ),
.SLAVE_MAP ( set_slave_map ),
.PREFER_HOST ( " " ),
.CLOCK_RATE_CLK ( 0 )
) adme (
.clk (reconfig_clk),
.reset (reconfig_reset),
.master_write (jtag_write),
.master_read (jtag_read),
.master_address (jtag_address),
.master_writedata (jtag_writedata),
.master_waitrequest (jtag_waitrequest),
.master_readdatavalid (jtag_readdatavalid),
.master_readdata (jtag_readdata)
);
`else
assign jtag_write = 1'b0;
assign jtag_read = 1'b0;
assign jtag_writedata = 32'b0;
assign jtag_address = {ADDR_BITS+SEL_BITS{1'b0}};
`endif
//************************************************************************
//*********************** JTAG<->Reconfig Arbitration ********************
// Drop the lower two address bits from the jtag master (byte addressed)
assign arb_address = sel ? jtag_address[(ADDR_BITS+SEL_BITS-1):0] : reconfig_address;
assign arb_write = sel ? jtag_write : reconfig_write;
assign arb_read = sel ? jtag_read : reconfig_read;
assign arb_writedata = sel ? jtag_writedata : reconfig_writedata;
assign reconfig_readdata = arb_readdata;
assign jtag_readdata = arb_readdata;
assign reconfig_waitrequest= arb_waitrequest | sel;
assign jtag_waitrequest = arb_waitrequest | ~sel;
// Arbitration
always @(posedge reconfig_clk or posedge reconfig_reset)
if(reconfig_reset) sel <= 1'b0;
else begin
if(sel) sel <= arb_waitrequest;
else sel <= (jtag_write|jtag_read) & ~(reconfig_write|reconfig_read);
end
//********************* End JTAG<->Reconfig Arbitration ******************
//************************************************************************
end
endgenerate
//******************** End Embedded JTAG Debug Master ***********************
//***************************************************************************
//***************************************************************************
//********************** AVMM Reconfig Connections **************************
generate
if(!RECONFIG_SHARED) begin : g_not_shared
// We wire straight between the interfaces if there is no sharing logic
assign avmm_clk = reconfig_clk;
assign avmm_reset = reconfig_reset;
assign avmm_write = arb_write;
assign avmm_read = arb_read;
assign avmm_address = arb_address;
assign arb_waitrequest = avmm_waitrequest;
for(ig=0;ig<CHANNELS;ig=ig+1) begin : g_shared
assign avmm_writedata[ig*8 +:8] = arb_writedata[ig*32 +: 8];
assign arb_readdata [ig*32 +:32] = {24'd0,avmm_readdata[ig*8 +: 8]};
end
end else begin : g_shared
wire [SEL_BITS-1:0] arb_sel;
assign arb_sel = arb_address[ADDR_BITS+:SEL_BITS];
for(ig=0;ig<CHANNELS;ig=ig+1) begin : g_shared
assign avmm_clk [ig] = reconfig_clk;
assign avmm_reset [ig] = reconfig_reset;
// Use the upper address bits as the interface select if shared
assign avmm_write [ig] = arb_write & (arb_sel == ig);
assign avmm_read [ig] = arb_read & (arb_sel == ig);
assign avmm_address [ig*ADDR_BITS +: ADDR_BITS] = arb_address[0+:ADDR_BITS];
assign avmm_writedata[ig*8 +: 8] = arb_writedata[7:0];
end
assign arb_readdata = {24'd0,avmm_readdata[arb_sel*8 +: 8]};
assign arb_waitrequest = avmm_waitrequest[arb_sel];
end
endgenerate
//********************** AVMM Reconfig Connections **************************
//***************************************************************************
////////////////////////////////////////////////////////////////////
// Return the number of bits required to represent an integer
// E.g. 0->1; 1->1; 2->2; 3->2 ... 31->5; 32->6
//
function integer clogb2;
input integer input_num;
begin
for (clogb2=0; input_num>0; clogb2=clogb2+1)
input_num = input_num >> 1;
if(clogb2 == 0)
clogb2 = 1;
end
endfunction
// Returns an inst as a string for using string concatenation
function [30*8-1:0] int2str(
input integer in_int
);
integer i;
integer this_char;
i = 0;
int2str = "";
do
begin
this_char = (in_int % 10) + 48;
int2str[i*8+:8] = this_char[7:0];
i=i+1;
in_int = in_int / 10;
end
while(in_int > 0);
endfunction
endmodule
platform/altera/wr_arria10_e3p1_phy/wr_arria10_e3p1_cmu_pll/wr_arria10_e3p1_cmu_pll/altera_xcvr_cdr_pll_a10_181/synth/alt_xcvr_pll_embedded_debug.sv 0 → 100644
View file @ e5246fa3
// (C) 2001-2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
module alt_xcvr_pll_embedded_debug #(
parameter dbg_capability_reg_enable = 0,
parameter dbg_user_identifier = 0,
parameter dbg_stat_soft_logic_enable = 0,
parameter dbg_ctrl_soft_logic_enable = 0,
parameter en_master_cgb = 0
) (
// avmm signals
input avmm_clk,
input avmm_reset,
input [8:0] avmm_address,
input [7:0] avmm_writedata,
input avmm_write,
input avmm_read,
output [7:0] avmm_readdata,
output avmm_waitrequest,
// input signals from the core
input in_pll_powerdown,
input in_pll_locked,
input in_pll_cal_busy,
input in_avmm_busy,
// output signals to the ip
output out_pll_powerdown
);
wire prbs_done_sync;
wire csr_prbs_snapshot;
wire csr_prbs_count_en;
wire csr_prbs_reset;
wire [47:0] prbs_err_count;
wire [47:0] prbs_bit_count;
alt_xcvr_pll_avmm_csr #(
.dbg_capability_reg_enable ( dbg_capability_reg_enable ),
.dbg_user_identifier ( dbg_user_identifier ),
.dbg_stat_soft_logic_enable ( dbg_stat_soft_logic_enable ),
.dbg_ctrl_soft_logic_enable ( dbg_ctrl_soft_logic_enable ),
.en_master_cgb ( en_master_cgb)
) embedded_debug_soft_csr (
// avmm signals
.avmm_clk (avmm_clk),
.avmm_reset (avmm_reset),
.avmm_address (avmm_address),
.avmm_writedata (avmm_writedata),
.avmm_write (avmm_write),
.avmm_read (avmm_read),
.avmm_readdata (avmm_readdata),
.avmm_waitrequest (avmm_waitrequest),
// input status signals from the channel
.pll_powerdown (in_pll_powerdown),
.pll_locked (in_pll_locked),
.pll_cal_busy (in_pll_cal_busy),
.avmm_busy (in_avmm_busy),
// output control signals
.csr_pll_powerdown (out_pll_powerdown)
);
endmodule
platform/altera/wr_arria10_e3p1_phy/wr_arria10_e3p1_cmu_pll/wr_arria10_e3p1_cmu_pll/altera_xcvr_cdr_pll_a10_181/synth/alt_xcvr_resync.sv 0 → 100644
View file @ e5246fa3
// (C) 2001-2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// Module: alt_xcvr_resync
//
// Description:
// A general purpose resynchronization module.
//
// Parameters:
// SYNC_CHAIN_LENGTH
// - Specifies the length of the synchronizer chain for metastability
// retiming.
// WIDTH
// - Specifies the number of bits you want to synchronize. Controls the width of the
// d and q ports.
// SLOW_CLOCK - USE WITH CAUTION.
// - Leaving this setting at its default will create a standard resynch circuit that
// merely passes the input data through a chain of flip-flops. This setting assumes
// that the input data has a pulse width longer than one clock cycle sufficient to
// satisfy setup and hold requirements on at least one clock edge.
// - By setting this to 1 (USE CAUTION) you are creating an asynchronous
// circuit that will capture the input data regardless of the pulse width and
// its relationship to the clock. However it is more difficult to apply static
// timing constraints as it ties the data input to the clock input of the flop.
// This implementation assumes the data rate is slow enough
// INIT_VALUE
// - Specifies the initial values of the synchronization registers.
//
// Apply embedded false path timing constraint
(* altera_attribute = "-name SDC_STATEMENT \"set regs [get_registers -nowarn *alt_xcvr_resync*sync_r[0]]; if {[llength [query_collection -report -all $regs]] > 0} {set_false_path -to $regs}\"" *)
`timescale 1ps/1ps
module alt_xcvr_resync #(
parameter SYNC_CHAIN_LENGTH = 2, // Number of flip-flops for retiming. Must be >1
parameter WIDTH = 1, // Number of bits to resync
parameter SLOW_CLOCK = 0, // See description above
parameter INIT_VALUE = 0
) (
input wire clk,
input wire reset,
input wire [WIDTH-1:0] d,
output wire [WIDTH-1:0] q
);
localparam INT_LEN = (SYNC_CHAIN_LENGTH > 1) ? SYNC_CHAIN_LENGTH : 2;
localparam [INT_LEN-1:0] L_INIT_VALUE = (INIT_VALUE == 1) ? {INT_LEN{1'b1}} : {INT_LEN{1'b0}};
genvar ig;
// Generate a synchronizer chain for each bit
generate begin
for(ig=0;ig<WIDTH;ig=ig+1) begin : resync_chains
wire d_in; // Input to sychronization chain.
(* altera_attribute = "disable_da_rule=D103" *)
reg [INT_LEN-1:0] sync_r = L_INIT_VALUE;
assign q[ig] = sync_r[INT_LEN-1]; // Output signal
always @(posedge clk or posedge reset)
if(reset)
sync_r <= L_INIT_VALUE;
else
sync_r <= {sync_r[INT_LEN-2:0],d_in};
// Generate asynchronous capture circuit if specified.
if(SLOW_CLOCK == 0) begin
assign d_in = d[ig];
end else begin
wire d_clk;
reg d_r = L_INIT_VALUE[0];
wire clr_n;
assign d_clk = d[ig];
assign d_in = d_r;
assign clr_n = ~q[ig] | d_clk; // Clear when output is logic 1 and input is logic 0
// Asynchronously latch the input signal.
always @(posedge d_clk or negedge clr_n)
if(!clr_n) d_r <= 1'b0;
else if(d_clk) d_r <= 1'b1;
end // SLOW_CLOCK
end // for loop
end // generate
endgenerate
endmodule
platform/altera/wr_arria10_e3p1_phy/wr_arria10_e3p1_cmu_pll/wr_arria10_e3p1_cmu_pll/altera_xcvr_cdr_pll_a10_181/synth/plain_files.txt 0 → 100644
View file @ e5246fa3
./twentynm_xcvr_avmm.sv
./alt_xcvr_resync.sv
./altera_xcvr_cdr_pll_a10.sv
./a10_avmm_h.sv
./alt_xcvr_native_avmm_nf.sv
./alt_xcvr_pll_embedded_debug.sv
./alt_xcvr_pll_avmm_csr.sv
platform/altera/wr_arria10_e3p1_phy/wr_arria10_e3p1_cmu_pll/wr_arria10_e3p1_cmu_pll/altera_xcvr_cdr_pll_a10_181/synth/wr_arria10_e3p1_cmu_pll_pkg.vhd 0 → 100644
View file @ e5246fa3
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package wr_arria10_e3p1_cmu_pll_pkg is
component altera_xcvr_cdr_pll_a10 is
generic (
enable_pll_reconfig : integer := 0;
rcfg_jtag_enable : integer := 0;
rcfg_separate_avmm_busy : integer := 0;
dbg_embedded_debug_enable : integer := 0;
dbg_capability_reg_enable : integer := 0;
dbg_user_identifier : integer := 0;
dbg_stat_soft_logic_enable : integer := 0;
dbg_ctrl_soft_logic_enable : integer := 0;
cdr_pll_silicon_rev : string := "20nm5es";
cdr_pll_pma_width : integer := 8;
cdr_pll_cgb_div : integer := 1;
cdr_pll_is_cascaded_pll : string := "false";
cdr_pll_datarate : string := "0 bps";
cdr_pll_lpd_counter : integer := 1;
cdr_pll_lpfd_counter : integer := 1;
cdr_pll_n_counter_scratch : integer := 1;
cdr_pll_output_clock_frequency : string := "0 hz";
cdr_pll_reference_clock_frequency : string := "0 hz";
cdr_pll_set_cdr_vco_speed : integer := 1;
cdr_pll_set_cdr_vco_speed_fix : integer := 0;
cdr_pll_vco_freq : string := "0 hz";
cdr_pll_atb_select_control : string := "atb_off";
cdr_pll_auto_reset_on : string := "auto_reset_on";
cdr_pll_bbpd_data_pattern_filter_select : string := "bbpd_data_pat_off";
cdr_pll_bw_sel : string := "low";
cdr_pll_cdr_odi_select : string := "sel_cdr";
cdr_pll_cdr_phaselock_mode : string := "no_ignore_lock";
cdr_pll_cdr_powerdown_mode : string := "power_down";
cdr_pll_chgpmp_current_pd : string := "cp_current_pd_setting0";
cdr_pll_chgpmp_current_pfd : string := "cp_current_pfd_setting0";
cdr_pll_chgpmp_replicate : string := "false";
cdr_pll_chgpmp_testmode : string := "cp_test_disable";
cdr_pll_clklow_mux_select : string := "clklow_mux_cdr_fbclk";
cdr_pll_disable_up_dn : string := "true";
cdr_pll_fref_clklow_div : integer := 1;
cdr_pll_fref_mux_select : string := "fref_mux_cdr_refclk";
cdr_pll_gpon_lck2ref_control : string := "gpon_lck2ref_off";
cdr_pll_initial_settings : string := "true";
cdr_pll_lck2ref_delay_control : string := "lck2ref_delay_off";
cdr_pll_lf_resistor_pd : string := "lf_pd_setting0";
cdr_pll_lf_resistor_pfd : string := "lf_pfd_setting0";
cdr_pll_lf_ripple_cap : string := "lf_no_ripple";
cdr_pll_loop_filter_bias_select : string := "lpflt_bias_off";
cdr_pll_ltd_ltr_micro_controller_select : string := "ltd_ltr_pcs";
cdr_pll_m_counter : integer := 16;
cdr_pll_n_counter : integer := 1;
cdr_pll_optimal : string := "false";
cdr_pll_pd_fastlock_mode : string := "false";
cdr_pll_pd_l_counter : integer := 1;
cdr_pll_pfd_l_counter : integer := 1;
cdr_pll_primary_use : string := "cmu";
cdr_pll_prot_mode : string := "unused";
cdr_pll_set_cdr_v2i_enable : string := "true";
cdr_pll_set_cdr_vco_reset : string := "false";
cdr_pll_set_cdr_vco_speed_pciegen3 : string := "cdr_vco_max_speedbin_pciegen3";
cdr_pll_pm_speed_grade : string := "e2";
cdr_pll_sup_mode : string := "user_mode";
cdr_pll_tx_pll_prot_mode : string := "txpll_unused";
cdr_pll_txpll_hclk_driver_enable : string := "false";
cdr_pll_vco_overrange_voltage : string := "vco_overrange_off";
cdr_pll_vco_underrange_voltage : string := "vco_underange_off";
cdr_pll_fb_select : string := "direct_fb";
cdr_pll_uc_ro_cal : string := "uc_ro_cal_off";
cdr_pll_iqclk_mux_sel : string := "power_down";
cdr_pll_pcie_gen : string := "non_pcie";
cdr_pll_set_cdr_input_freq_range : integer := 0;
cdr_pll_chgpmp_current_dn_trim : string := "cp_current_trimming_dn_setting0";
cdr_pll_chgpmp_up_pd_trim_double : string := "normal_up_trim_current";
cdr_pll_chgpmp_current_up_pd : string := "cp_current_pd_up_setting0";
cdr_pll_chgpmp_current_up_trim : string := "cp_current_trimming_up_setting0";
cdr_pll_chgpmp_dn_pd_trim_double : string := "normal_dn_trim_current";
cdr_pll_cal_vco_count_length : string := "sel_8b_count";
cdr_pll_chgpmp_current_dn_pd : string := "cp_current_pd_dn_setting0";
enable_analog_resets : integer := 0;
calibration_en : string := "enable";
pma_cdr_refclk_select_mux_silicon_rev : string := "";
pma_cdr_refclk_select_mux_refclk_select : string := "";
pma_cdr_refclk_select_mux_powerdown_mode : string := "";
pma_cdr_refclk_select_mux_inclk0_logical_to_physical_mapping : string := "";
pma_cdr_refclk_select_mux_inclk1_logical_to_physical_mapping : string := "";
pma_cdr_refclk_select_mux_inclk2_logical_to_physical_mapping : string := "";
pma_cdr_refclk_select_mux_inclk3_logical_to_physical_mapping : string := "";
pma_cdr_refclk_select_mux_inclk4_logical_to_physical_mapping : string := ""
);
port (
pll_powerdown : in std_logic := 'X'; -- pll_powerdown
pll_refclk0 : in std_logic := 'X'; -- clk
tx_serial_clk : out std_logic; -- clk
pll_locked : out std_logic; -- pll_locked
pll_cal_busy : out std_logic; -- pll_cal_busy
pll_refclk1 : in std_logic := 'X'; -- clk
pll_refclk2 : in std_logic := 'X'; -- clk
pll_refclk3 : in std_logic := 'X'; -- clk
pll_refclk4 : in std_logic := 'X'; -- clk
reconfig_clk0 : in std_logic := 'X'; -- clk
reconfig_reset0 : in std_logic := 'X'; -- reset
reconfig_write0 : in std_logic := 'X'; -- write
reconfig_read0 : in std_logic := 'X'; -- read
reconfig_address0 : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
reconfig_writedata0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
reconfig_readdata0 : out std_logic_vector(31 downto 0); -- readdata
reconfig_waitrequest0 : out std_logic; -- waitrequest
avmm_busy0 : out std_logic; -- avmm_busy0
hip_cal_done : out std_logic -- hip_cal_done
);
end component altera_xcvr_cdr_pll_a10;
end wr_arria10_e3p1_cmu_pll_pkg;
platform/altera/wr_arria10_e3p1_phy/wr_arria10_e3p1_cmu_pll/wr_arria10_e3p1_cmu_pll/synth/wr_arria10_e3p1_cmu_pll.qicache 0 → 100644
View file @ e5246fa3
<?xml version='1.0' encoding='us-ascii'?>
<qsys_generation_info>
<qsys_file path="/home/alex/workspace/a10_wrpc-4.2_cmu_pinning_fix_simple_wa/ip_cores/wr-cores/platform/altera/wr_arria10_e3p1_phy/wr_arria10_e3p1_cmu_pll/wr_arria10_e3p1_cmu_pll.qsys" />
<gen_dir path="/home/alex/workspace/a10_wrpc-4.2_cmu_pinning_fix_simple_wa/ip_cores/wr-cores/platform/altera/wr_arria10_e3p1_phy/wr_arria10_e3p1_cmu_pll/wr_arria10_e3p1_cmu_pll/" />
<user_regen_policy value="Never Regenerate Existing IP" />
<actual_regen_policy value="Never Regenerate Existing IP" />
<gen_action value="IP Generation Skipped" />
<gen_status value="IP Generation Succeeded" />
</qsys_generation_info>
\ No newline at end of file
platform/altera/wr_arria10_e3p1_phy/wr_arria10_e3p1_cmu_pll/wr_arria10_e3p1_cmu_pll/synth/wr_arria10_e3p1_cmu_pll.vhd 0 → 100644
View file @ e5246fa3
-- wr_arria10_e3p1_cmu_pll.vhd
-- Generated using ACDS version 18.1 625
library IEEE;
library wr_arria10_e3p1_cmu_pll_altera_xcvr_cdr_pll_a10_181;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use wr_arria10_e3p1_cmu_pll_altera_xcvr_cdr_pll_a10_181.wr_arria10_e3p1_cmu_pll_pkg.all;
entity wr_arria10_e3p1_cmu_pll is
port (
pll_cal_busy : out std_logic; -- pll_cal_busy.pll_cal_busy
pll_locked : out std_logic; -- pll_locked.pll_locked
pll_powerdown : in std_logic := '0'; -- pll_powerdown.pll_powerdown
pll_refclk0 : in std_logic := '0'; -- pll_refclk0.clk
tx_serial_clk : out std_logic -- tx_serial_clk.clk
);
end entity wr_arria10_e3p1_cmu_pll;
architecture rtl of wr_arria10_e3p1_cmu_pll is
begin
xcvr_cdr_pll_a10_0 : component wr_arria10_e3p1_cmu_pll_altera_xcvr_cdr_pll_a10_181.wr_arria10_e3p1_cmu_pll_pkg.altera_xcvr_cdr_pll_a10
generic map (
enable_pll_reconfig => 0,
rcfg_jtag_enable => 0,
rcfg_separate_avmm_busy => 0,
dbg_embedded_debug_enable => 0,
dbg_capability_reg_enable => 0,
dbg_user_identifier => 0,
dbg_stat_soft_logic_enable => 0,
dbg_ctrl_soft_logic_enable => 0,
cdr_pll_silicon_rev => "20nm5",
cdr_pll_pma_width => 8,
cdr_pll_cgb_div => 1,
cdr_pll_is_cascaded_pll => "false",
cdr_pll_datarate => "5000000000 bps",
cdr_pll_lpd_counter => 0,
cdr_pll_lpfd_counter => 2,
cdr_pll_n_counter_scratch => 1,
cdr_pll_output_clock_frequency => "2500000000 Hz",
cdr_pll_reference_clock_frequency => "125000000 Hz",
cdr_pll_set_cdr_vco_speed => 3,
cdr_pll_set_cdr_vco_speed_fix => 60,
cdr_pll_vco_freq => "5000000000 Hz",
cdr_pll_atb_select_control => "atb_off",
cdr_pll_auto_reset_on => "auto_reset_off",
cdr_pll_bbpd_data_pattern_filter_select => "bbpd_data_pat_off",
cdr_pll_bw_sel => "medium",
cdr_pll_cdr_odi_select => "sel_cdr",
cdr_pll_cdr_phaselock_mode => "no_ignore_lock",
cdr_pll_cdr_powerdown_mode => "power_up",
cdr_pll_chgpmp_current_pd => "cp_current_pd_setting0",
cdr_pll_chgpmp_current_pfd => "cp_current_pfd_setting3",
cdr_pll_chgpmp_replicate => "false",
cdr_pll_chgpmp_testmode => "cp_test_disable",
cdr_pll_clklow_mux_select => "clklow_mux_cdr_fbclk",
cdr_pll_disable_up_dn => "true",
cdr_pll_fref_clklow_div => 1,
cdr_pll_fref_mux_select => "fref_mux_cdr_refclk",
cdr_pll_gpon_lck2ref_control => "gpon_lck2ref_off",
cdr_pll_initial_settings => "true",
cdr_pll_lck2ref_delay_control => "lck2ref_delay_2",
cdr_pll_lf_resistor_pd => "lf_pd_setting0",
cdr_pll_lf_resistor_pfd => "lf_pfd_setting2",
cdr_pll_lf_ripple_cap => "lf_no_ripple",
cdr_pll_loop_filter_bias_select => "lpflt_bias_7",
cdr_pll_ltd_ltr_micro_controller_select => "ltd_ltr_pcs",
cdr_pll_m_counter => 20,
cdr_pll_n_counter => 1,
cdr_pll_optimal => "false",
cdr_pll_pd_fastlock_mode => "false",
cdr_pll_pd_l_counter => 0,
cdr_pll_pfd_l_counter => 2,
cdr_pll_primary_use => "cmu",
cdr_pll_prot_mode => "unused",
cdr_pll_set_cdr_v2i_enable => "true",
cdr_pll_set_cdr_vco_reset => "false",
cdr_pll_set_cdr_vco_speed_pciegen3 => "cdr_vco_max_speedbin_pciegen3",
cdr_pll_pm_speed_grade => "i2",
cdr_pll_sup_mode => "user_mode",
cdr_pll_tx_pll_prot_mode => "txpll_enable",
cdr_pll_txpll_hclk_driver_enable => "false",
cdr_pll_vco_overrange_voltage => "vco_overrange_off",
cdr_pll_vco_underrange_voltage => "vco_underange_off",
cdr_pll_fb_select => "direct_fb",
cdr_pll_uc_ro_cal => "uc_ro_cal_on",
cdr_pll_iqclk_mux_sel => "power_down",
cdr_pll_pcie_gen => "non_pcie",
cdr_pll_set_cdr_input_freq_range => 0,
cdr_pll_chgpmp_current_dn_trim => "cp_current_trimming_dn_setting0",
cdr_pll_chgpmp_up_pd_trim_double => "normal_up_trim_current",
cdr_pll_chgpmp_current_up_pd => "cp_current_pd_up_setting0",
cdr_pll_chgpmp_current_up_trim => "cp_current_trimming_up_setting0",
cdr_pll_chgpmp_dn_pd_trim_double => "normal_dn_trim_current",
cdr_pll_cal_vco_count_length => "sel_8b_count",
cdr_pll_chgpmp_current_dn_pd => "cp_current_pd_dn_setting0",
enable_analog_resets => 0,
calibration_en => "enable",
pma_cdr_refclk_select_mux_silicon_rev => "20nm5",
pma_cdr_refclk_select_mux_refclk_select => "ref_iqclk0",
pma_cdr_refclk_select_mux_powerdown_mode => "powerup",
pma_cdr_refclk_select_mux_inclk0_logical_to_physical_mapping => "ref_iqclk0",
pma_cdr_refclk_select_mux_inclk1_logical_to_physical_mapping => "power_down",
pma_cdr_refclk_select_mux_inclk2_logical_to_physical_mapping => "power_down",
pma_cdr_refclk_select_mux_inclk3_logical_to_physical_mapping => "power_down",
pma_cdr_refclk_select_mux_inclk4_logical_to_physical_mapping => "power_down"
)
port map (
pll_powerdown => pll_powerdown, -- pll_powerdown.pll_powerdown
pll_refclk0 => pll_refclk0, -- pll_refclk0.clk
tx_serial_clk => tx_serial_clk, -- tx_serial_clk.clk
pll_locked => pll_locked, -- pll_locked.pll_locked
pll_cal_busy => pll_cal_busy, -- pll_cal_busy.pll_cal_busy
pll_refclk1 => '0', -- (terminated)
pll_refclk2 => '0', -- (terminated)
pll_refclk3 => '0', -- (terminated)
pll_refclk4 => '0', -- (terminated)
reconfig_clk0 => '0', -- (terminated)
reconfig_reset0 => '0', -- (terminated)
reconfig_write0 => '0', -- (terminated)
reconfig_read0 => '0', -- (terminated)
reconfig_address0 => "0000000000", -- (terminated)
reconfig_writedata0 => "00000000000000000000000000000000", -- (terminated)
reconfig_readdata0 => open, -- (terminated)
reconfig_waitrequest0 => open, -- (terminated)
avmm_busy0 => open, -- (terminated)
hip_cal_done => open -- (terminated)
);
end architecture rtl; -- of wr_arria10_e3p1_cmu_pll
platform/altera/wr_arria10_e3p1_phy/wr_arria10_e3p1_cmu_pll/wr_arria10_e3p1_cmu_pll/wr_arria10_e3p1_cmu_pll.bsf 0 → 100644
View file @ e5246fa3
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2018 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 336 184)
(text "wr_arria10_e3p1_cmu_pll" (rect 94 -1 195 11)(font "Arial" (font_size 10)))
(text "inst" (rect 8 168 20 180)(font "Arial" ))
(port
(pt 0 72)
(input)
(text "pll_powerdown" (rect 0 0 56 12)(font "Arial" (font_size 8)))
(text "pll_powerdown" (rect 4 61 82 72)(font "Arial" (font_size 8)))
(line (pt 0 72)(pt 96 72)(line_width 1))
)
(port
(pt 0 112)
(input)
(text "pll_refclk0" (rect 0 0 40 12)(font "Arial" (font_size 8)))
(text "pll_refclk0" (rect 4 101 70 112)(font "Arial" (font_size 8)))
(line (pt 0 112)(pt 96 112)(line_width 1))
)
(port
(pt 336 72)
(output)
(text "pll_cal_busy" (rect 0 0 49 12)(font "Arial" (font_size 8)))
(text "pll_cal_busy" (rect 272 61 344 72)(font "Arial" (font_size 8)))
(line (pt 336 72)(pt 240 72)(line_width 1))
)
(port
(pt 336 112)
(output)
(text "pll_locked" (rect 0 0 37 12)(font "Arial" (font_size 8)))
(text "pll_locked" (rect 286 101 346 112)(font "Arial" (font_size 8)))
(line (pt 336 112)(pt 240 112)(line_width 1))
)
(port
(pt 336 152)
(output)
(text "tx_serial_clk" (rect 0 0 49 12)(font "Arial" (font_size 8)))
(text "tx_serial_clk" (rect 272 141 350 152)(font "Arial" (font_size 8)))
(line (pt 336 152)(pt 240 152)(line_width 1))
)
(drawing
(text "pll_cal_busy" (rect 241 43 554 99)(font "Arial" (color 128 0 0)(font_size 9)))
(text "pll_cal_busy" (rect 183 67 438 144)(font "Arial" (color 0 0 0)))
(text "pll_locked" (rect 241 83 542 179)(font "Arial" (color 128 0 0)(font_size 9)))
(text "pll_locked" (rect 195 107 450 224)(font "Arial" (color 0 0 0)))
(text "pll_powerdown" (rect 9 43 96 99)(font "Arial" (color 128 0 0)(font_size 9)))
(text "pll_powerdown" (rect 101 67 280 144)(font "Arial" (color 0 0 0)))
(text "pll_refclk0" (rect 36 83 138 179)(font "Arial" (color 128 0 0)(font_size 9)))
(text "clk" (rect 101 107 220 224)(font "Arial" (color 0 0 0)))
(text "tx_serial_clk" (rect 241 123 560 259)(font "Arial" (color 128 0 0)(font_size 9)))
(text "clk" (rect 225 147 468 304)(font "Arial" (color 0 0 0)))
(text " system " (rect 301 168 650 346)(font "Arial" ))
(line (pt 96 32)(pt 240 32)(line_width 1))
(line (pt 240 32)(pt 240 168)(line_width 1))
(line (pt 96 168)(pt 240 168)(line_width 1))
(line (pt 96 32)(pt 96 168)(line_width 1))
(line (pt 239 52)(pt 239 76)(line_width 1))
(line (pt 238 52)(pt 238 76)(line_width 1))
(line (pt 239 92)(pt 239 116)(line_width 1))
(line (pt 238 92)(pt 238 116)(line_width 1))
(line (pt 97 52)(pt 97 76)(line_width 1))
(line (pt 98 52)(pt 98 76)(line_width 1))
(line (pt 97 92)(pt 97 116)(line_width 1))
(line (pt 98 92)(pt 98 116)(line_width 1))
(line (pt 239 132)(pt 239 156)(line_width 1))
(line (pt 238 132)(pt 238 156)(line_width 1))
(line (pt 0 0)(pt 336 0)(line_width 1))
(line (pt 336 0)(pt 336 184)(line_width 1))
(line (pt 0 184)(pt 336 184)(line_width 1))
(line (pt 0 0)(pt 0 184)(line_width 1))
)
)
platform/altera/wr_arria10_e3p1_phy/wr_arria10_e3p1_cmu_pll/wr_arria10_e3p1_cmu_pll/wr_arria10_e3p1_cmu_pll.cmp 0 → 100644
View file @ e5246fa3
component wr_arria10_e3p1_cmu_pll is
port (
pll_cal_busy : out std_logic; -- pll_cal_busy
pll_locked : out std_logic; -- pll_locked
pll_powerdown : in std_logic := 'X'; -- pll_powerdown
pll_refclk0 : in std_logic := 'X'; -- clk
tx_serial_clk : out std_logic -- clk
);
end component wr_arria10_e3p1_cmu_pll;
platform/altera/wr_arria10_e3p1_phy/wr_arria10_e3p1_cmu_pll/wr_arria10_e3p1_cmu_pll/wr_arria10_e3p1_cmu_pll.ppf 0 → 100644
View file @ e5246fa3
<?xml version="1.0" encoding="UTF-8"?>
<pinplan
variation_name="xcvr_cdr_pll_a10_0"
megafunction_name="ALTERA_XCVR_CDR_PLL_A10"
intended_family="Arria 10"
specifies="all_ports">
<global>
<pin name="pll_powerdown" direction="input" scope="external" />
<pin name="pll_refclk0" direction="input" scope="external" />
<pin name="tx_serial_clk" direction="output" scope="external" />
<pin name="pll_locked" direction="output" scope="external" />
<pin name="pll_cal_busy" direction="output" scope="external" />
</global>
</pinplan>
platform/altera/wr_arria10_e3p1_phy/wr_arria10_e3p1_cmu_pll/wr_arria10_e3p1_cmu_pll/wr_arria10_e3p1_cmu_pll_bb.v 0 → 100644
View file @ e5246fa3
module wr_arria10_e3p1_cmu_pll (
pll_cal_busy,
pll_locked,
pll_powerdown,
pll_refclk0,
tx_serial_clk);
output pll_cal_busy;
output pll_locked;
input pll_powerdown;
input pll_refclk0;
output tx_serial_clk;
endmodule
platform/altera/wr_arria10_e3p1_phy/wr_arria10_e3p1_cmu_pll/wr_arria10_e3p1_cmu_pll/wr_arria10_e3p1_cmu_pll_generation.rpt 0 → 100644
View file @ e5246fa3
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate /home/alex/workspace/a10_wrpc-4.2_cmu/ip_cores/wr-cores/platform/altera/wr_arria10_e3p1_phy/wr_arria10_e3p1_cmu_pll/wr_arria10_e3p1_cmu_pll.qsys --synthesis=VHDL --output-directory=/home/alex/workspace/a10_wrpc-4.2_cmu/ip_cores/wr-cores/platform/altera/wr_arria10_e3p1_phy/wr_arria10_e3p1_cmu_pll/wr_arria10_e3p1_cmu_pll --family="Arria 10" --part=10AX115S2F45I1SG
Progress: Loading wr_arria10_e3p1_cmu_pll/wr_arria10_e3p1_cmu_pll.qsys
Progress: Reading input file
Progress: Adding xcvr_cdr_pll_a10_0 [altera_xcvr_cdr_pll_a10 18.1]
Progress: Parameterizing module xcvr_cdr_pll_a10_0
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Info: wr_arria10_e3p1_cmu_pll.xcvr_cdr_pll_a10_0: Please note that the Arria 10 Transceiver CMU PLL does not support feedback compensation bonding or xN/x6 clock line usage (bonded or non-bonded modes).
Info: wr_arria10_e3p1_cmu_pll.xcvr_cdr_pll_a10_0: For the selected device(10AX115S2F45I1SG), transceiver PLL speed grade is 2.
Info: wr_arria10_e3p1_cmu_pll: "Transforming system: wr_arria10_e3p1_cmu_pll"
Info: wr_arria10_e3p1_cmu_pll: Running transform generation_view_transform
Info: wr_arria10_e3p1_cmu_pll: Running transform generation_view_transform took 0.000s
Info: xcvr_cdr_pll_a10_0: Running transform generation_view_transform
Info: xcvr_cdr_pll_a10_0: Running transform generation_view_transform took 0.000s
Info: wr_arria10_e3p1_cmu_pll: Running transform merlin_avalon_transform
Info: wr_arria10_e3p1_cmu_pll: Running transform merlin_avalon_transform took 0.030s
Info: wr_arria10_e3p1_cmu_pll: "Naming system components in system: wr_arria10_e3p1_cmu_pll"
Info: wr_arria10_e3p1_cmu_pll: "Processing generation queue"
Info: wr_arria10_e3p1_cmu_pll: "Generating: wr_arria10_e3p1_cmu_pll"
Info: wr_arria10_e3p1_cmu_pll: "Generating: altera_xcvr_cdr_pll_a10"
Info: xcvr_cdr_pll_a10_0: add_fileset_file ./twentynm_xcvr_avmm.sv SYSTEM_VERILOG PATH ../../../alt_xcvr_core/nf/twentynm_xcvr_avmm.sv
Info: xcvr_cdr_pll_a10_0: add_fileset_file ./alt_xcvr_resync.sv SYSTEM_VERILOG PATH ../../../../altera_xcvr_generic/ctrl/alt_xcvr_resync.sv
Info: xcvr_cdr_pll_a10_0: add_fileset_file ./altera_xcvr_cdr_pll_a10.sv SYSTEM_VERILOG PATH ../source/altera_xcvr_cdr_pll_a10.sv
Info: xcvr_cdr_pll_a10_0: add_fileset_file ./a10_avmm_h.sv SYSTEM_VERILOG PATH ../../../altera_xcvr_native_phy/altera_xcvr_native_vi/a10_avmm_h.sv
Info: xcvr_cdr_pll_a10_0: add_fileset_file ./alt_xcvr_native_avmm_nf.sv SYSTEM_VERILOG PATH ../../../altera_xcvr_native_phy/altera_xcvr_native_vi/alt_xcvr_native_avmm_nf.sv
Info: xcvr_cdr_pll_a10_0: add_fileset_file ./alt_xcvr_pll_embedded_debug.sv SYSTEM_VERILOG PATH ../../altera_xcvr_atx_pll_vi/source/alt_xcvr_pll_embedded_debug.sv
Info: xcvr_cdr_pll_a10_0: add_fileset_file ./alt_xcvr_pll_avmm_csr.sv SYSTEM_VERILOG PATH ../../altera_xcvr_atx_pll_vi/source/alt_xcvr_pll_avmm_csr.sv
Info: wr_arria10_e3p1_cmu_pll: Done "wr_arria10_e3p1_cmu_pll" with 2 modules, 10 files
Info: qsys-generate succeeded.
Info: Finished: Create HDL design files for synthesis
platform/altera/wr_arria10_e3p1_phy/wr_arria10_e3p1_cmu_pll/wr_arria10_e3p1_cmu_pll/wr_arria10_e3p1_cmu_pll_generation_previous.rpt 0 → 100644
View file @ e5246fa3
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate /home/alex/workspace/a10_wrpc-4.2_cmu/ip_cores/wr-cores/platform/altera/wr_arria10_e3p1_phy/wr_arria10_e3p1_cmu_pll/wr_arria10_e3p1_cmu_pll.qsys --synthesis=VHDL --output-directory=/home/alex/workspace/a10_wrpc-4.2_cmu/ip_cores/wr-cores/platform/altera/wr_arria10_e3p1_phy/wr_arria10_e3p1_cmu_pll/wr_arria10_e3p1_cmu_pll --family="Arria 10" --part=10AX115S2F45I1SG
Progress: Loading wr_arria10_e3p1_cmu_pll/wr_arria10_e3p1_cmu_pll.qsys
Progress: Reading input file
Progress: Adding xcvr_cdr_pll_a10_0 [altera_xcvr_cdr_pll_a10 18.1]
Progress: Parameterizing module xcvr_cdr_pll_a10_0
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Info: wr_arria10_e3p1_cmu_pll.xcvr_cdr_pll_a10_0: Please note that the Arria 10 Transceiver CMU PLL does not support feedback compensation bonding or xN/x6 clock line usage (bonded or non-bonded modes).
Info: wr_arria10_e3p1_cmu_pll.xcvr_cdr_pll_a10_0: For the selected device(10AX115S2F45I1SG), transceiver PLL speed grade is 2.
Info: wr_arria10_e3p1_cmu_pll: "Transforming system: wr_arria10_e3p1_cmu_pll"
Info: wr_arria10_e3p1_cmu_pll: Running transform generation_view_transform
Info: wr_arria10_e3p1_cmu_pll: Running transform generation_view_transform took 0.000s
Info: xcvr_cdr_pll_a10_0: Running transform generation_view_transform
Info: xcvr_cdr_pll_a10_0: Running transform generation_view_transform took 0.000s
Info: wr_arria10_e3p1_cmu_pll: Running transform merlin_avalon_transform
Info: wr_arria10_e3p1_cmu_pll: Running transform merlin_avalon_transform took 0.030s
Info: wr_arria10_e3p1_cmu_pll: "Naming system components in system: wr_arria10_e3p1_cmu_pll"
Info: wr_arria10_e3p1_cmu_pll: "Processing generation queue"
Info: wr_arria10_e3p1_cmu_pll: "Generating: wr_arria10_e3p1_cmu_pll"
Info: wr_arria10_e3p1_cmu_pll: "Generating: altera_xcvr_cdr_pll_a10"
Info: xcvr_cdr_pll_a10_0: add_fileset_file ./twentynm_xcvr_avmm.sv SYSTEM_VERILOG PATH ../../../alt_xcvr_core/nf/twentynm_xcvr_avmm.sv
Info: xcvr_cdr_pll_a10_0: add_fileset_file ./alt_xcvr_resync.sv SYSTEM_VERILOG PATH ../../../../altera_xcvr_generic/ctrl/alt_xcvr_resync.sv
Info: xcvr_cdr_pll_a10_0: add_fileset_file ./altera_xcvr_cdr_pll_a10.sv SYSTEM_VERILOG PATH ../source/altera_xcvr_cdr_pll_a10.sv
Info: xcvr_cdr_pll_a10_0: add_fileset_file ./a10_avmm_h.sv SYSTEM_VERILOG PATH ../../../altera_xcvr_native_phy/altera_xcvr_native_vi/a10_avmm_h.sv
Info: xcvr_cdr_pll_a10_0: add_fileset_file ./alt_xcvr_native_avmm_nf.sv SYSTEM_VERILOG PATH ../../../altera_xcvr_native_phy/altera_xcvr_native_vi/alt_xcvr_native_avmm_nf.sv
Info: xcvr_cdr_pll_a10_0: add_fileset_file ./alt_xcvr_pll_embedded_debug.sv SYSTEM_VERILOG PATH ../../altera_xcvr_atx_pll_vi/source/alt_xcvr_pll_embedded_debug.sv
Info: xcvr_cdr_pll_a10_0: add_fileset_file ./alt_xcvr_pll_avmm_csr.sv SYSTEM_VERILOG PATH ../../altera_xcvr_atx_pll_vi/source/alt_xcvr_pll_avmm_csr.sv
Info: wr_arria10_e3p1_cmu_pll: Done "wr_arria10_e3p1_cmu_pll" with 2 modules, 10 files
Info: qsys-generate succeeded.
Info: Finished: Create HDL design files for synthesis
platform/altera/wr_arria10_e3p1_phy/wr_arria10_e3p1_cmu_pll/wr_arria10_e3p1_cmu_pll/wr_arria10_e3p1_cmu_pll_inst.v 0 → 100644
View file @ e5246fa3
wr_arria10_e3p1_cmu_pll u0 (
.pll_cal_busy (<connected-to-pll_cal_busy>), // pll_cal_busy.pll_cal_busy
.pll_locked (<connected-to-pll_locked>), // pll_locked.pll_locked
.pll_powerdown (<connected-to-pll_powerdown>), // pll_powerdown.pll_powerdown
.pll_refclk0 (<connected-to-pll_refclk0>), // pll_refclk0.clk
.tx_serial_clk (<connected-to-tx_serial_clk>) // tx_serial_clk.clk
);
platform/altera/wr_arria10_e3p1_phy/wr_arria10_e3p1_cmu_pll/wr_arria10_e3p1_cmu_pll/wr_arria10_e3p1_cmu_pll_inst.vhd 0 → 100644
View file @ e5246fa3
component wr_arria10_e3p1_cmu_pll is
port (
pll_cal_busy : out std_logic; -- pll_cal_busy
pll_locked : out std_logic; -- pll_locked
pll_powerdown : in std_logic := 'X'; -- pll_powerdown
pll_refclk0 : in std_logic := 'X'; -- clk
tx_serial_clk : out std_logic -- clk
);
end component wr_arria10_e3p1_cmu_pll;
u0 : component wr_arria10_e3p1_cmu_pll
port map (
pll_cal_busy => CONNECTED_TO_pll_cal_busy, -- pll_cal_busy.pll_cal_busy
pll_locked => CONNECTED_TO_pll_locked, -- pll_locked.pll_locked
pll_powerdown => CONNECTED_TO_pll_powerdown, -- pll_powerdown.pll_powerdown
pll_refclk0 => CONNECTED_TO_pll_refclk0, -- pll_refclk0.clk
tx_serial_clk => CONNECTED_TO_tx_serial_clk -- tx_serial_clk.clk
);
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment