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Commit e70368e8 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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platform/xilinx: redesign of platform wrapper based on new approach (borrowed from platfrom/altera)

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platform/xilinx/Manifest.py
View file @ e70368e8
files = [ "wr_xilinx_pkg.vhd", "ext_pll_10_to_125m.vhd", "xwrc_platform_xilinx.vhd" ]
modules = {"local" : ["wr_gtp_phy", "chipscope"]}
\ No newline at end of file
files = [ "wr_xilinx_pkg.vhd", "xwrc_platform_xilinx.vhd" ]
modules = {"local" : ["wr_gtp_phy", "chipscope"]}
platform/xilinx/ext_pll_10_to_125m.vhd deleted 100644 → 0
View file @ 479c1ff2
-- file: ext_pll_10_to_125m.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1___125.000______0.000______50.0_____1014.602____150.000
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary__________10.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity ext_pll_10_to_125m is
port
(-- Clock in ports
clk_ext_i : in std_logic;
-- Clock out ports
clk_ext_mul_o : out std_logic;
-- Status and control signals
rst_a_i : in std_logic;
clk_in_stopped_o : out std_logic;
locked_o : out std_logic
);
end ext_pll_10_to_125m;
architecture xilinx of ext_pll_10_to_125m is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "ext_pll_10_to_125m,clk_wiz_v3_6,{component_name=ext_pll_10_to_125m,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=100.0,clkin2_period=100.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=true,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkfx : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
clkin1 <= clk_ext_i;
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 2,
CLKFX_MULTIPLY => 25,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 100.0,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => open,
CLKDV => open,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => rst_a_i,
-- Unused pin, tie low
DSSEN => '0');
clk_in_stopped_o <= status_internal(1);
locked_o <= locked_internal;
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfb,
I => clk0);
clkout1_buf : BUFG
port map
(O => clk_ext_mul_o,
I => clkfx);
end xilinx;
platform/xilinx/wr_xilinx_pkg.vhd
View file @ e70368e8
......@@ -2,93 +2,52 @@ library ieee;
use ieee.std_logic_1164.all;
library work;
use work.genram_pkg.all;
use work.wishbone_pkg.all;
use work.sysc_wbgen2_pkg.all;
use work.wr_fabric_pkg.all;
use work.endpoint_pkg.all;
package wr_xilinx_pkg is
-------------------------------------------------------------------------------------------
-- records used as interface between WRPC and platform-specific module xwrc_platform_xilinx
-------------------------------------------------------------------------------------------
type t_sfp_from_wrc is record
scl : std_logic;
sda : std_logic;
end record;
type t_sfp_to_wrc is record
scl : std_logic;
sda : std_logic;
det : std_logic;
end record;
type t_dacs_from_wrc is record
hpll_load_p1 : std_logic;
hpll_data : std_logic_vector(15 downto 0);
dpll_load_p1 : std_logic;
dpll_data : std_logic_vector(15 downto 0);
end record;
type t_extref_to_wrc is record
clk_10m_ref : std_logic;
clk_125m_ref : std_logic;
locked : std_logic;
stopped : std_logic;
pps : std_logic;
end record;
-------------------------------------------------------------------------------------------
component xwrc_platform_xilinx
generic
(
g_simulation : integer := 0;
g_family : string := "spartan6";
g_with_10m_refin : integer := 0
);
component xwrc_platform_xilinx is
generic (
g_fpga_family : string := "spartan6";
g_with_external_clock_input : boolean := FALSE;
g_use_default_plls : boolean := TRUE;
g_simulation : integer := 0);
port (
local_reset_n_i : in std_logic;
clk_20m_vcxo_i : in std_logic; -- 20MHz VCXO clock
clk_125m_pllref_p_i : in std_logic; -- 125 MHz PLL reference
clk_125m_pllref_n_i : in std_logic;
clk_125m_gtp_n_i : in std_logic; -- 125 MHz GTP reference
clk_125m_gtp_p_i : in std_logic; -- 125 MHz GTP reference
clk_10m_ref_p_i : in std_logic := '0'; -- 10MHz external reference
clk_10m_ref_n_i : in std_logic := '0'; -- 10MHz external reference
pps_ext_i : in std_logic := '0'; -- external 1-PPS from reference
dac_sclk_o : out std_logic; -- Serial Clock Line
dac_din_o : out std_logic; -- Serial Data Line
dac_cs1_n_o : out std_logic; -- Chip Select
dac_cs2_n_o : out std_logic; -- Chip Select
carrier_onewire_b : inout std_logic := '1'; -- read temperature sensor
sfp_txp_o : out std_logic;
sfp_txn_o : out std_logic;
sfp_rxp_i : in std_logic;
sfp_rxn_i : in std_logic;
sfp_mod_def0_i : in std_logic; -- sfp detect
sfp_mod_def1_b : inout std_logic; -- Config-I2C: Clk Line
sfp_mod_def2_b : inout std_logic; -- Config-I2C: Data Line
sfp_rate_select_b : inout std_logic;
sfp_tx_fault_i : in std_logic;
sfp_tx_disable_o : out std_logic;
sfp_los_i : in std_logic;
clk_62m5_sys_o : out std_logic;
clk_125m_pllref_o : out std_logic;
clk_62m5_dmtd_o : out std_logic;
dacs_i : in t_dacs_from_wrc;
phy8_o : out t_phy_8bits_to_wrc;
phy8_i : in t_phy_8bits_from_wrc := c_dummy_phy8_from_wrc;
phy16_o : out t_phy_16bits_to_wrc;
phy16_i : in t_phy_16bits_from_wrc := c_dummy_phy16_from_wrc;
owr_en_i : in std_logic_vector(1 downto 0);
owr_o : out std_logic_vector(1 downto 0);
sfp_config_o : out t_sfp_to_wrc;
sfp_config_i : in t_sfp_from_wrc;
ext_ref_o : out t_extref_to_wrc;
ext_ref_rst_i : in std_logic := '0'
);
end component;
areset_n_i : in std_logic := '1';
clk_10m_ext_i : in std_logic := '0';
clk_125m_gtp_p_i : in std_logic;
clk_125m_gtp_n_i : in std_logic;
clk_20m_vcxo_i : in std_logic := '0';
clk_125m_pllref_i : in std_logic := '0';
clk_62m5_dmtd_i : in std_logic := '0';
clk_dmtd_locked_i : in std_logic := '1';
clk_62m5_sys_i : in std_logic := '0';
clk_sys_locked_i : in std_logic := '1';
clk_125m_ref_i : in std_logic := '0';
clk_125m_ext_i : in std_logic := '0';
clk_ext_locked_i : in std_logic := '1';
clk_ext_stopped_i : in std_logic := '0';
clk_ext_rst_o : out std_logic;
sfp_txn_o : out std_logic;
sfp_txp_o : out std_logic;
sfp_rxn_i : in std_logic;
sfp_rxp_i : in std_logic;
sfp_tx_fault_i : in std_logic := '0';
sfp_los_i : in std_logic := '0';
sfp_tx_disable_o : out std_logic;
clk_62m5_sys_o : out std_logic;
clk_125m_ref_o : out std_logic;
clk_62m5_dmtd_o : out std_logic;
pll_locked_o : out std_logic;
phy8_o : out t_phy_8bits_to_wrc;
phy8_i : in t_phy_8bits_from_wrc := c_dummy_phy8_from_wrc;
phy16_o : out t_phy_16bits_to_wrc;
phy16_i : in t_phy_16bits_from_wrc := c_dummy_phy16_from_wrc;
ext_ref_mul_o : out std_logic;
ext_ref_mul_locked_o : out std_logic;
ext_ref_mul_stopped_o : out std_logic;
ext_ref_rst_i : in std_logic := '0');
end component xwrc_platform_xilinx;
component wr_gtp_phy_spartan6
generic (
......@@ -97,7 +56,7 @@ package wr_xilinx_pkg is
g_simulation : integer := 0);
port (
gtp_clk_i : in std_logic;
ch0_ref_clk_i : in std_logic := '0';
ch0_ref_clk_i : in std_logic := '0';
ch0_tx_data_i : in std_logic_vector(7 downto 0) := "00000000";
ch0_tx_k_i : in std_logic := '0';
ch0_tx_disparity_o : out std_logic;
......@@ -107,10 +66,10 @@ package wr_xilinx_pkg is
ch0_rx_k_o : out std_logic;
ch0_rx_enc_err_o : out std_logic;
ch0_rx_bitslide_o : out std_logic_vector(3 downto 0);
ch0_rst_i : in std_logic := '0';
ch0_loopen_i : in std_logic := '0';
ch0_loopen_vec_i : in std_logic_vector(2 downto 0) := (others=>'0');
ch0_tx_prbs_sel_i : in std_logic_vector(2 downto 0) := (others=>'0');
ch0_rst_i : in std_logic := '0';
ch0_loopen_i : in std_logic := '0';
ch0_loopen_vec_i : in std_logic_vector(2 downto 0) := (others => '0');
ch0_tx_prbs_sel_i : in std_logic_vector(2 downto 0) := (others => '0');
ch0_rdy_o : out std_logic;
ch1_ref_clk_i : in std_logic;
ch1_tx_data_i : in std_logic_vector(7 downto 0) := "00000000";
......@@ -124,8 +83,8 @@ package wr_xilinx_pkg is
ch1_rx_bitslide_o : out std_logic_vector(3 downto 0);
ch1_rst_i : in std_logic := '0';
ch1_loopen_i : in std_logic := '0';
ch1_loopen_vec_i : in std_logic_vector(2 downto 0) := (others=>'0');
ch1_tx_prbs_sel_i : in std_logic_vector(2 downto 0) := (others=>'0');
ch1_loopen_vec_i : in std_logic_vector(2 downto 0) := (others => '0');
ch1_tx_prbs_sel_i : in std_logic_vector(2 downto 0) := (others => '0');
ch1_rdy_o : out std_logic;
pad_txn0_o : out std_logic;
pad_txp0_o : out std_logic;
......@@ -162,13 +121,4 @@ package wr_xilinx_pkg is
pad_rxp_i : in std_logic := '0');
end component;
component ext_pll_10_to_125m
port (
clk_ext_i : in std_logic;
clk_ext_mul_o : out std_logic;
rst_a_i : in std_logic;
clk_in_stopped_o: out std_logic;
locked_o : out std_logic);
end component ext_pll_10_to_125m;
end wr_xilinx_pkg;
platform/xilinx/xwrc_platform_xilinx.vhd
View file @ e70368e8
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