altera phy: at some point tx_disparity_o timing changed => updated

The WR TX path in the endpoint reset disparity to minus. To do this, it needs the disparity from the transceiver. Previously the disparity had to be delayed a few cycles. At some point this must have changed. Now the core goes back to sending 0x17C = K28_5 minus as commas after packet boundaries.

altera phy: at some point tx_disparity_o timing changed => updated
The WR TX path in the endpoint reset disparity to minus. To do this, it needs the disparity from the transceiver. Previously the disparity had to be delayed a few cycles. At some point this must have changed. Now the core goes back to sending 0x17C = K28_5 minus as commas after packet boundaries.
ebc5758d · Wesley W. Terpstra · 9ca2585f · ebc5758d · ebc5758d
Commit ebc5758d authored Oct 04, 2013 by Wesley W. Terpstra
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wr_arria2_phy.vhd platform/altera/wr_arria2_phy/wr_arria2_phy.vhd +1 -12

wr_arria5_phy.vhd platform/altera/wr_arria5_phy/wr_arria5_phy.vhd +1 -12

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--- a/platform/altera/wr_arria2_phy/wr_arria2_phy.vhd
+++ b/platform/altera/wr_arria2_phy/wr_arria2_phy.vhd
@@ -182,7 +182,6 @@ architecture rtl of wr_arria2_phy is
  
  signal rx_dump_link                : std_logic_vector(6 downto 0); -- Long enough to kill ep_sync_detect
  signal rx_enc_err                  : std_logic;
-  signal tx_disp_pipe                : std_logic_vector (2 downto 0);
  signal rx_bitslipboundaryselectout : std_logic_vector (4 downto 0);
  
  signal rx_gxb_dataout              : std_logic_vector (9 downto 0); -- signal out of GXB
@@ -259,7 +258,7 @@ begin
      ctrl_i    => tx_k_i,
      in_8b_i   => tx_data_i,
      err_o     => tx_enc_err_o,
-      dispar_o  => tx_disp_pipe(0),
+      dispar_o  => tx_disparity_o,
      out_10b_o => tx_enc_datain);
  
  -- Decode the RX data
@@ -413,16 +412,6 @@ begin
    end if;
  end process;
  
-  -- The disparity should be delayed for WR
-  tx_disparity_o <= tx_disp_pipe(2);
-  p_delay_disp : process(tx_clk_i)
-  begin
-    if rising_edge(tx_clk_i) then
-      tx_disp_pipe(1) <= tx_disp_pipe(0);
-      tx_disp_pipe(2) <= tx_disp_pipe(1);
-    end if;
-  end process;
-  
  -- Cross clock domain from tx_clk_i to tx_clk
  -- These clocks must be phase aligned
  -- Registers tx_reg_datain and tx_gxb_datain must be logic locked

--- a/platform/altera/wr_arria5_phy/wr_arria5_phy.vhd
+++ b/platform/altera/wr_arria5_phy/wr_arria5_phy.vhd
@@ -157,7 +157,6 @@ architecture rtl of wr_arria5_phy is
  signal xcvr_to_reconfig : std_logic_vector(91 downto 0);
  signal reconfig_to_xcvr : std_logic_vector(139 downto 0);
  
-  signal tx_disp_pipe                : std_logic_vector (2 downto 0);
  signal rx_bitslipboundaryselectout : std_logic_vector (4 downto 0);
  signal rx_gxb_dataout              : std_logic_vector (9 downto 0); -- signal out of GXB
  signal rx_reg_dataout              : std_logic_vector (9 downto 0); -- regional clocked FPGA register (clk_rx)
@@ -228,7 +227,7 @@ begin
      ctrl_i    => tx_k_i,
      in_8b_i   => tx_data_i,
      err_o     => tx_enc_err_o,
-      dispar_o  => tx_disp_pipe(0),
+      dispar_o  => tx_disparity_o,
      out_10b_o => tx_enc_datain);
  
  -- Decode the RX data
@@ -261,16 +260,6 @@ begin
    end if;
  end process;
  
-  -- The disparity should be delayed for WR
-  tx_disparity_o <= tx_disp_pipe(2);
-  p_delay_disp : process(tx_clk_i)
-  begin
-    if rising_edge(tx_clk_i) then
-      tx_disp_pipe(1) <= tx_disp_pipe(0);
-      tx_disp_pipe(2) <= tx_disp_pipe(1);
-    end if;
-  end process;
-  
  -- Cross clock domain from tx_clk_i to clk_tx
  -- These clocks must be phase aligned
  -- Registers tx_reg_datain and tx_gxb_datain must be logic locked