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White Rabbit core collection
Commit ee81e1b4 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski Committed by Maciej Lipinski
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wr_streamers: testbench wip

parent 082002de
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modules/fabric/xwrf_loopback/build_wb.sh 100755 → 100644
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modules/wr_eca/sim.sh 100755 → 100644
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modules/wr_endpoint/build_wb.sh 100755 → 100644
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modules/wr_mini_nic/build_wb.sh 100755 → 100644
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modules/wr_pps_gen/build_wb.sh 100755 → 100644
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modules/wr_softpll_ng/build_wb.sh 100755 → 100644
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modules/wrc_core/build_wb.sh 100755 → 100644
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testbench/wr_streamers/streamers_multi_test/Manifest.py
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...@@ -3,13 +3,14 @@ target= "xilinx" ...@@ -3,13 +3,14 @@ target= "xilinx"
syn_device="xc6slx45t" syn_device="xc6slx45t"
sim_tool="modelsim" sim_tool="modelsim"
top_module="main" top_module="main"
sim_top="main"
fetchto="../../../ip_cores" fetchto="../../../ip_cores"
vlog_opt="+incdir+../../../sim" vlog_opt="+incdir+../../../sim"
modules = { "local" : ["../../..", modules = { "local" : ["../../..",
"../../../modules/wr_streamers", "../../../modules/wr_streamers",
"../../../ip_cores/general-cores"]} "../../../../general-cores"]}
files = ["main.sv"] files = ["main.sv"]
testbench/wr_streamers/streamers_multi_test/main.sv
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...@@ -171,7 +171,7 @@ module main; ...@@ -171,7 +171,7 @@ module main;
// -------------------------------------------------------------------------- // --------------------------------------------------------------------------
//Set counter values for time measurements //Set counter values for time measurements
always@(posedge clk_ref) tm_cycle_counter <= tm_cycle_counter + 1; always@(posedge clk) tm_cycle_counter <= tm_cycle_counter + 1;
always@(posedge clk) clk_cycle_counter <= clk_cycle_counter + 1; always@(posedge clk) clk_cycle_counter <= clk_cycle_counter + 1;
always@(posedge tx_streamer_last) clk_cycle_tmout_ctr_before = clk_cycle_counter; always@(posedge tx_streamer_last) clk_cycle_tmout_ctr_before = clk_cycle_counter;
always@(posedge rx_frame_received) clk_cycle_tmout_ctr_after = clk_cycle_counter; always@(posedge rx_frame_received) clk_cycle_tmout_ctr_after = clk_cycle_counter;
...@@ -188,7 +188,8 @@ module main; ...@@ -188,7 +188,8 @@ module main;
.g_tx_timeout (g_tx_tm_out), .g_tx_timeout (g_tx_tm_out),
.g_tx_max_words_per_frame (g_max_wrds_pr_frm), .g_tx_max_words_per_frame (g_max_wrds_pr_frm),
.g_simulation(1), .g_simulation(1),
.g_sim_startup_cnt(0) .g_sim_startup_cnt(0),
.g_clk_ref_rate(125000000)
) )
U_TX_Streamer U_TX_Streamer
( (
...@@ -205,7 +206,7 @@ module main; ...@@ -205,7 +206,7 @@ module main;
.src_err_i (mac.err), .src_err_i (mac.err),
.src_ack_i (tx_wb_ack), .src_ack_i (tx_wb_ack),
.clk_ref_i(clk_ref), // fake WR time .clk_ref_i(clk), // fake WR time
.tm_time_valid_i(1'b1), .tm_time_valid_i(1'b1),
.tm_cycles_i(tm_cycle_counter), .tm_cycles_i(tm_cycle_counter),
...@@ -226,7 +227,9 @@ module main; ...@@ -226,7 +227,9 @@ module main;
rx_streamer rx_streamer
#( #(
.g_data_width (g_word_width) .g_data_width (g_word_width),
.g_clk_ref_rate(125000000)
) )
U_RX_Streamer U_RX_Streamer
( (
...@@ -244,7 +247,7 @@ module main; ...@@ -244,7 +247,7 @@ module main;
.snk_err_o (mac.err), .snk_err_o (mac.err),
.snk_rty_o (mac.rty), .snk_rty_o (mac.rty),
.clk_ref_i(clk_ref), // fake WR time .clk_ref_i(clk), // fake WR time
.tm_time_valid_i(1'b1), .tm_time_valid_i(1'b1),
.tm_cycles_i(tm_cycle_counter), .tm_cycles_i(tm_cycle_counter),
...@@ -477,7 +480,7 @@ module main; ...@@ -477,7 +480,7 @@ module main;
flatency_test = 0; flatency_test = 0;
frm_drop_test = 0; frm_drop_test = 0;
`ifdef DISABLED
//Tx TEST 1: Check that when tx_flush_i is asserted, current frame is txed //Tx TEST 1: Check that when tx_flush_i is asserted, current frame is txed
//------------------------------------------------------------------------- //-------------------------------------------------------------------------
current_test = "Tx FLUSH"; current_test = "Tx FLUSH";
...@@ -589,6 +592,12 @@ module main; ...@@ -589,6 +592,12 @@ module main;
join join
test_num ++; test_num ++;
`endif
$display("Dupa?");
// Rx Test 5: Check the fixed latency is correct // Rx Test 5: Check the fixed latency is correct
//----------------------------------------------- //-----------------------------------------------
...@@ -611,14 +620,15 @@ module main; ...@@ -611,14 +620,15 @@ module main;
//fixed latency value is checked against range since i/o interface //fixed latency value is checked against range since i/o interface
//of streamers does not allow for exact latency measurement without //of streamers does not allow for exact latency measurement without
//probing an internal signal //probing an internal signal
$display ("Fixed latency set to %.3f us, Rx output valid @ %.3f us",
real'(fixed_latency) * 0.008, real'(clk_cycle_frm_valid-
clk_cycle_frm_txed) * 0.008);
if ((fixed_latency <= clk_cycle_frm_valid - clk_cycle_frm_txed+24) && if ((fixed_latency <= clk_cycle_frm_valid - clk_cycle_frm_txed+24) &&
(fixed_latency >= clk_cycle_frm_valid - clk_cycle_frm_txed-24) ) (fixed_latency >= clk_cycle_frm_valid - clk_cycle_frm_txed-24) )
begin begin
$display ("[%t ns]: PASSED - TEST %d - %s \n", $time, test_num, current_test ); $display ("[%t ns]: PASSED - TEST %d - %s \n", $time, test_num, current_test );
//$display ("Fixed latency set to %.3f us, Rx output valid @ %.3f us",
//real'(fixed_latency) * 0.008, real'(clk_cycle_frm_valid-
//clk_cycle_frm_txed) * 0.008);
flatency_test = 1; flatency_test = 1;
end end
else else
...@@ -683,13 +693,20 @@ module main; ...@@ -683,13 +693,20 @@ module main;
// wait (tx_frame_sent); // wait (tx_frame_sent);
// test_num ++; // test_num ++;
assert (flush_test == 1 && timeout_test == 1 && max_words_test == 1 && assert (/*flush_test == 1 && timeout_test == 1 && max_words_test == 1 &&
max_words_test == 1 && flatency_test == 1 && frm_drop_test == 1 && max_words_test == 1 && */ flatency_test == 1 && frm_drop_test == 1 &&
comparator_test == 1) comparator_test == 1)
else begin else begin
$error("Streamers implementation contains errors", $time); $error("Streamers implementation contains errors", $time);
$fatal; $error("Flush_test = %d", flush_test);
end $error("Timeout_test = %d", timeout_test);
$error("MaxWords_test = %d", max_words_test);
$error("FLatency_test = %d", flatency_test);
$error("FrmDrop_test = %d", frm_drop_test);
$error("Comparator_test = %d", comparator_test);
$stop;
end
...@@ -730,7 +747,7 @@ end ...@@ -730,7 +747,7 @@ end
if(tblk.words != rblk.words) if(tblk.words != rblk.words)
begin begin
$error("[%t ns]: >> FAILED - TEST - DATA MONITOR \n", $time ); $error("[%t ns]: >> FAILED - TEST - DATA MONITOR \n", $time );
//$display("Txed is %p, Rxed equals %p", tblk, rblk); $display("Txed is %p, Rxed equals %p", tblk, rblk);
comparator_test = 0; comparator_test = 0;
end end
else $display ("[%t ns]: PASSED - TEST - DATA MONITOR \n", $time ); else $display ("[%t ns]: PASSED - TEST - DATA MONITOR \n", $time );
......
testbench/wr_streamers/streamers_multi_test/run.do
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# make -f Makefile > /dev/null 2>&1 # make -f Makefile > /dev/null 2>&1
vsim -L unisim work.main -voptargs="+acc" -suppress 8684,8683 -sv_seed random vsim -t 1ps -L unisim work.main -novopt -suppress 8684,8683
#-sv_seed random
set NumericStdNoWarnings 1 set NumericStdNoWarnings 1
set StdArithNoWarnings 1 set StdArithNoWarnings 1
do wave.do do wave.do
run 10us run 50us
wave zoomfull wave zoomfull
radix -dec radix -dec
testbench/wr_streamers/streamers_multi_test/run_ci.do deleted 100644 → 0
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# Modelsim run script for continuous integration (with return code)
# execute: vsim -c -do "run_ci.do"
vsim -L unisim work.main -voptargs="+acc" -suppress 8684,8683 -sv_seed random
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
do wave.do
run 100ms
wave zoomfull
radix -hex
coverage save coverage.ucdb
quit -code [coverage attribute -name TESTSTATUS -concise]
testbench/wr_streamers/streamers_multi_test/wave.do
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onerror {resume} onerror {resume}
quietly WaveActivateNextPane {} 0 quietly WaveActivateNextPane {} 0
add wave -position end sim:/main/current_test add wave -noupdate -expand -group CH0 /main/DUT/clk_sys_i
add wave -noupdate /main/U_TX_Streamer/tx_valid_i add wave -noupdate -expand -group CH0 /main/DUT/rst_sys_n_i
add wave -noupdate /main/U_TX_Streamer/tx_data_i add wave -noupdate -expand -group CH0 /main/DUT/clk_tdc_i
add wave -noupdate /main/U_TX_Streamer/tx_last_p1_i add wave -noupdate -expand -group CH0 /main/DUT/rst_tdc_n_i
add wave -noupdate /main/U_TX_Streamer/tx_flush_p1_i add wave -noupdate -expand -group CH0 /main/DUT/clk_cal_i
add wave -position end sim:/main/U_TX_Streamer/U_Wrapped_Streamer/fab_src.sof add wave -noupdate -expand -group CH0 /main/DUT/coarse_i
add wave -position end sim:/main/U_TX_Streamer/U_Wrapped_Streamer/fab_src.eof add wave -noupdate -expand -group CH0 /main/DUT/signal_i
add wave -noupdate /main/U_TX_Streamer/tx_frame_p1_o add wave -noupdate -expand -group CH0 /main/DUT/slave_i
add wave -noupdate /main/U_TX_Streamer/tx_dreq_o add wave -noupdate -expand -group CH0 /main/DUT/slave_o
#add wave -noupdate /main/U_TX_Streamer/tx_reset_seq_i add wave -noupdate -expand -group CH0 /main/DUT/calib_sel_d
add wave -noupdate /main/U_RX_Streamer/rx_frame_p1_o add wave -noupdate -expand -group CH0 /main/DUT/muxed_signal
add wave -noupdate /main/U_RX_Streamer/rx_dreq_i add wave -noupdate -expand -group CH0 /main/DUT/tdc_inv_input_signal
add wave -noupdate /main/U_RX_Streamer/rx_valid_o add wave -noupdate -expand -group CH0 /main/DUT/taps
add wave -noupdate /main/U_RX_Streamer/rx_data_o add wave -noupdate -expand -group CH0 /main/DUT/taps_latched
add wave -noupdate /main/U_RX_Streamer/rx_first_p1_o add wave -noupdate -expand -group CH0 /main/DUT/ipolarity
add wave -noupdate /main/U_RX_Streamer/rx_last_p1_o add wave -noupdate -expand -group CH0 /main/DUT/polarity
add wave -noupdate /main/U_RX_Streamer/rx_lost_p1_o add wave -noupdate -expand -group CH0 /main/DUT/polarity_d1
add wave -position end sim:/main/drop_frm add wave -noupdate -expand -group CH0 /main/DUT/polarity_d2
add wave -position end sim:/main/rx_streamer_lost_frm add wave -noupdate -expand -group CH0 /main/DUT/detect_d1
add wave -position end sim:/main/rx_streamer_lost_frm_cnt add wave -noupdate -expand -group CH0 /main/DUT/raw
add wave -noupdate /main/U_RX_Streamer/rx_latency_o add wave -noupdate -expand -group CH0 /main/DUT/raw_d1
add wave -noupdate /main/U_RX_Streamer/rx_latency_valid_o add wave -noupdate -expand -group CH0 /main/DUT/raw_d2
add wave -position end sim:/main/rx_streamer_lost_blks add wave -noupdate -expand -group CH0 /main/DUT/lut_rvalue
add wave -position end sim:/main/fab_data_from_tx add wave -noupdate -expand -group CH0 /main/DUT/ro_en
add wave -position end sim:/main/fab_data_to_rx add wave -noupdate -expand -group CH0 /main/DUT/count
add wave -noupdate /main/mac/adr add wave -noupdate -expand -group CH0 /main/DUT/tdc_slave_out
#add wave -noupdate /main/mac/dat_o add wave -noupdate -expand -group CH0 /main/DUT/tdc_slave_in
#add wave -noupdate /main/mac/dat_i add wave -noupdate -expand -group CH0 /main/DUT/regs_in
#add wave -noupdate /main/mac/sel add wave -noupdate -expand -group CH0 /main/DUT/regs_out
#add wave -noupdate /main/mac/ack add wave -noupdate -expand -group CH0 /main/DUT/calib_next_sample
#add wave -noupdate /main/mac/stall add wave -noupdate -expand -group CH0 /main/DUT/calib_cur_sample
add wave -noupdate /main/mac/err add wave -noupdate -expand -group CH0 /main/DUT/calib_step_d
add wave -noupdate /main/mac/rty add wave -noupdate -expand -group CH0 /main/DUT/calib_offset_d
#add wave -noupdate /main/mac/cyc add wave -noupdate -expand -group CH0 /main/DUT/calib_p
#add wave -noupdate /main/mac/stb add wave -noupdate -expand -group CH0 /main/DUT/calib_rst_n
#add wave -noupdate /main/mac/we add wave -noupdate -expand -group CH0 /main/DUT/rst_tdc
add wave -position end sim:/main/delay_link add wave -noupdate -expand -group CH0 /main/DUT/ro_clk
add wave -position end sim:/main/tx_wb_cyc add wave -noupdate -expand -group CH0 /main/DUT/detect
add wave -position end sim:/main/rx_wb_cyc add wave -noupdate -expand -group CH0 /main/DUT/prev_taps_zero
add wave -position end sim:/main/tx_wb_ack add wave -noupdate -expand -group CH0 /main/DUT/taps_latched_ready
add wave -position end sim:/main/rx_wb_ack
add wave -position end sim:/main/rx_wb_stall
add wave -position end sim:/main/tx_wb_stall
add wave -position end sim:/main/tx_wb_stb
add wave -position end sim:/main/rx_wb_stb
TreeUpdate [SetDefaultTree] TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {867 ns} 0} WaveRestoreCursors {{Cursor 1} {11994963738 fs} 0}
configure wave -namecolwidth 150 configure wave -namecolwidth 150
configure wave -valuecolwidth 100 configure wave -valuecolwidth 100
configure wave -justifyvalue left configure wave -justifyvalue left
...@@ -61,4 +56,4 @@ configure wave -griddelta 40 ...@@ -61,4 +56,4 @@ configure wave -griddelta 40
configure wave -timeline 0 configure wave -timeline 0
configure wave -timelineunits ns configure wave -timelineunits ns
update update
WaveRestoreZoom {0 ns} {915 ns} WaveRestoreZoom {0 fs} {70811648 ps}
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