[wr_streamers] bugfix in WB-reg declaration

f2718f23 · Maciej Lipinski · 2433a795 · f2718f23 · f2718f23 · f2718f23
Commit f2718f23 authored Nov 24, 2016 by Maciej Lipinski
5 changed files
--- a/modules/wr_streamers/wr_transmission_wb.vhd
+++ b/modules/wr_streamers/wr_transmission_wb.vhd
@@ -3,7 +3,7 @@
 ---------------------------------------------------------------------------------------
 -- File           : wr_transmission_wb.vhd
 -- Author         : auto-generated by wbgen2 from wr_transmission_wb.wb
-- Created        : Thu Nov 24 17:03:04 2016
+-- Created        : Thu Nov 24 17:33:21 2016
 -- Standard       : VHDL'87
 ---------------------------------------------------------------------------------------
 -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_transmission_wb.wb
@@ -54,7 +54,7 @@ signal wr_transmission_rx_cfg1_mac_local_lsb_int : std_logic_vector(31 downto 0)
 signal wr_transmission_rx_cfg2_mac_local_msb_int : std_logic_vector(15 downto 0);
 signal wr_transmission_rx_cfg3_mac_remote_lsb_int : std_logic_vector(31 downto 0);
 signal wr_transmission_rx_cfg4_mac_remote_msb_int : std_logic_vector(15 downto 0);
-signal wr_transmission_rx_cfg5_fixed_latency_int : std_logic_vector(26 downto 0);
+signal wr_transmission_rx_cfg5_fixed_latency_int : std_logic_vector(27 downto 0);
 signal wr_transmission_cfg_tx_ena_int           : std_logic      ;
 signal wr_transmission_cfg_rx_ena_int           : std_logic      ;
 signal wr_transmission_dbg_ctrl_mux_int         : std_logic      ;
@@ -101,7 +101,7 @@ begin
      wr_transmission_rx_cfg2_mac_local_msb_int <= "0000000000000000";
      wr_transmission_rx_cfg3_mac_remote_lsb_int <= "00000000000000000000000000000000";
      wr_transmission_rx_cfg4_mac_remote_msb_int <= "0000000000000000";
-      wr_transmission_rx_cfg5_fixed_latency_int <= "000000000000000000000000000";
+      wr_transmission_rx_cfg5_fixed_latency_int <= "0000000000000000000000000000";
      wr_transmission_cfg_tx_ena_int <= '0';
      wr_transmission_cfg_rx_ena_int <= '0';
      wr_transmission_dbg_ctrl_mux_int <= '0';
@@ -371,10 +371,9 @@ begin
            ack_in_progress <= '1';
          when "10101" => 
            if (wb_we_i = '1') then
-              wr_transmission_rx_cfg5_fixed_latency_int <= wrdata_reg(26 downto 0);
+              wr_transmission_rx_cfg5_fixed_latency_int <= wrdata_reg(27 downto 0);
            end if;
-            rddata_reg(26 downto 0) <= wr_transmission_rx_cfg5_fixed_latency_int;
-            rddata_reg(27) <= 'X';
+            rddata_reg(27 downto 0) <= wr_transmission_rx_cfg5_fixed_latency_int;
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';

--- a/modules/wr_streamers/wr_transmission_wb.wb
+++ b/modules/wr_streamers/wr_transmission_wb.wb
@@ -354,7 +354,7 @@ peripheral {
      description = "This register allows to configure fixed-latency. If the value is other than zero, the instant of outputing the received data from the rx streamer to the user application is delayed, so that the time-difference between the transmission fo the data and the output to the user matches the provided value. If the configured latency value is smaller than the network latency, the data is provided to the user instantly. The configuration value is expressed in clock cycles (16ns) ";
      prefix = "fixed_latency";
      type = SLV;
-      size = 27;
+      size = 28;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
      };

--- a/modules/wr_streamers/wr_transmission_wbgen2_pkg.vhd
+++ b/modules/wr_streamers/wr_transmission_wbgen2_pkg.vhd
@@ -3,7 +3,7 @@
 ---------------------------------------------------------------------------------------
 -- File           : wr_transmission_wbgen2_pkg.vhd
 -- Author         : auto-generated by wbgen2 from wr_transmission_wb.wb
-- Created        : Thu Nov 24 17:03:04 2016
+-- Created        : Thu Nov 24 17:33:21 2016
 -- Standard       : VHDL'87
 ---------------------------------------------------------------------------------------
 -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_transmission_wb.wb
@@ -75,7 +75,7 @@ package wr_transmission_wbgen2_pkg is
      rx_cfg2_mac_local_msb_o                  : std_logic_vector(15 downto 0);
      rx_cfg3_mac_remote_lsb_o                 : std_logic_vector(31 downto 0);
      rx_cfg4_mac_remote_msb_o                 : std_logic_vector(15 downto 0);
-      rx_cfg5_fixed_latency_o                  : std_logic_vector(26 downto 0);
+      rx_cfg5_fixed_latency_o                  : std_logic_vector(27 downto 0);
      cfg_tx_ena_o                             : std_logic;
      cfg_rx_ena_o                             : std_logic;
      dbg_ctrl_mux_o                           : std_logic;

--- a/modules/wr_streamers/xwr_transmission.vhd
+++ b/modules/wr_streamers/xwr_transmission.vhd
@@ -503,6 +503,6 @@ begin
                                            rx_cfg_accept_broadcasts_i;
  rx_cfg_filter_remote           <= from_wb.rx_cfg0_filter_remote_o    when (from_wb.cfg_rx_ena_o='1') else
                                            rx_cfg_filter_remote_i;
-  rx_cfg_fixed_latency           <= from_wb.rx_cfg5_fixed_latency_o when (from_wb.cfg_rx_ena_o='1') else
+  rx_cfg_fixed_latency           <= from_wb.rx_cfg5_fixed_latency_o    when (from_wb.cfg_rx_ena_o='1') else
                                            rx_cfg_fixed_latency_i;
 end rtl;
\ No newline at end of file
--- a/sim/wr_transmission_wb.svh
+++ b/sim/wr_transmission_wb.svh
@@ -75,7 +75,7 @@
 `define WR_TRANSMISSION_RX_CFG4_MAC_REMOTE_MSB 32'h0000ffff
 `define ADDR_WR_TRANSMISSION_RX_CFG5   7'h54
 `define WR_TRANSMISSION_RX_CFG5_FIXED_LATENCY_OFFSET 0
-`define WR_TRANSMISSION_RX_CFG5_FIXED_LATENCY 32'h07ffffff
+`define WR_TRANSMISSION_RX_CFG5_FIXED_LATENCY 32'h0fffffff
 `define ADDR_WR_TRANSMISSION_CFG       7'h58
 `define WR_TRANSMISSION_CFG_TX_ENA_OFFSET 0
 `define WR_TRANSMISSION_CFG_TX_ENA 32'h00000001