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White Rabbit core collection
Commit f2d93c0c authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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wr_core: temporary version with new endpoint & minic

parent 19fdec39
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Showing with 211 additions and 313 deletions
modules/wrc_core/Manifest.py
View file @ f2d93c0c
......@@ -4,5 +4,6 @@ files = [ "wr_core.vhd",
"wrc_periph.vhd",
"wb_reset.vhd" ];
fetchto = "../../ip_cores"
modules = {"local" : "wb_conmax"};
#fetchto = "../../ip_cores"
modules/wrc_core/wr_core.vhd
View file @ f2d93c0c
This diff is collapsed.
modules/wrc_core/wrc_periph.vhd
View file @ f2d93c0c
......@@ -6,7 +6,7 @@
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-04-04
-- Last update: 2011-07-18
-- Last update: 2011-10-25
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -36,6 +36,7 @@ use ieee.std_logic_1164.all;
library work;
use work.wrcore_pkg.all;
use work.wishbone_pkg.all;
entity wrc_periph is
generic(
......@@ -70,22 +71,7 @@ end wrc_periph;
architecture struct of wrc_periph is
component wb_tics
generic (
g_period : integer);
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_addr_i : in std_logic_vector(1 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic);
end component;
component wb_reset
port (
clk_i : in std_logic;
......@@ -101,58 +87,7 @@ architecture struct of wrc_periph is
wb_ack_o : out std_logic);
end component;
component wb_simple_uart
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_addr_i : in std_logic_vector(1 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic);
end component;
component wb_virtual_uart
port(
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_addr_i : in std_logic_vector(2 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic
);
end component;
component wb_gpio_port
generic (
g_num_pins : natural;
g_with_builtin_tristates : boolean);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_sel_i : in std_logic;
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_adr_i : in std_logic_vector(5 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_ack_o : out std_logic;
gpio_out_o : out std_logic_vector(g_num_pins-1 downto 0);
gpio_in_i : in std_logic_vector(g_num_pins-1 downto 0);
gpio_oen_o : out std_logic_vector(g_num_pins-1 downto 0));
end component;
type t_wbdata is array(3 downto 0) of std_logic_vector(31 downto 0);
signal wb_cycs_i : std_logic_vector(3 downto 0);
......@@ -207,11 +142,11 @@ begin
rst_n_i => rst_n_i,
clk_sys_i => clk_sys_i,
wb_sel_i => wb_sel_i(0),
wb_sel_i => wb_sel_i,
wb_cyc_i => wb_cycs_i(0),
wb_stb_i => wb_stb_i,
wb_we_i => wb_we_i,
wb_adr_i => wb_addr_i(5 downto 0),
wb_adr_i => wb_addr_i(7 downto 0),
wb_dat_i => wb_data_i,
wb_dat_o => wb_dats_o(0),
wb_ack_o => wb_acks_o(0),
......@@ -221,42 +156,27 @@ begin
gpio_oen_o => gpio_dir_o
);
GEN_UART: if(g_virtual_uart = 0) generate
UART: wb_simple_uart
port map(
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
wb_addr_i => wb_addr_i(1 downto 0),
wb_data_i => wb_data_i,
wb_data_o => wb_dats_o(1),
wb_cyc_i => wb_cycs_i(1),
wb_sel_i => wb_sel_i,
wb_stb_i => wb_stb_i,
wb_we_i => wb_we_i,
wb_ack_o => wb_acks_o(1),
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o
);
end generate;
UART: wb_simple_uart
generic map (
g_with_virtual_uart => true,
g_with_physical_uart => true)
port map(
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
wb_adr_i => wb_addr_i(4 downto 0),
wb_dat_i => wb_data_i,
wb_dat_o => wb_dats_o(1),
wb_cyc_i => wb_cycs_i(1),
wb_sel_i => wb_sel_i,
wb_stb_i => wb_stb_i,
wb_we_i => wb_we_i,
wb_ack_o => wb_acks_o(1),
GEN_VIRTUART: if(g_virtual_uart = 1) generate
VIRTUAL_UART: wb_virtual_uart
port map(
rst_n_i => rst_n_i,
clk_sys_i => clk_sys_i,
wb_addr_i => wb_addr_i(2 downto 0),
wb_data_i => wb_data_i,
wb_data_o => wb_dats_o(1),
wb_cyc_i => wb_cycs_i(1),
wb_sel_i => wb_sel_i,
wb_stb_i => wb_stb_i,
wb_we_i => wb_we_i,
wb_ack_o => wb_acks_o(1)
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o
);
end generate;
TICS: wb_tics
generic map (
......@@ -265,9 +185,9 @@ begin
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
wb_addr_i => wb_addr_i(1 downto 0),
wb_data_i => wb_data_i,
wb_data_o => wb_dats_o(2),
wb_adr_i => wb_addr_i(3 downto 0),
wb_dat_i => wb_data_i,
wb_dat_o => wb_dats_o(2),
wb_cyc_i => wb_cycs_i(2),
wb_sel_i => wb_sel_i,
wb_stb_i => wb_stb_i,
......
modules/wrc_core/wrcore_pkg.vhd
View file @ f2d93c0c
......@@ -4,6 +4,9 @@ use ieee.std_logic_1164.all;
library work;
use work.genram_pkg.all;
use work.wbconmax_pkg.all;
use work.wishbone_pkg.all;
use work.wr_fabric_pkg.all;
package wrcore_pkg is
......@@ -298,6 +301,7 @@ package wrcore_pkg is
clk_ref_i : in std_logic;
clk_dmtd_i : in std_logic;
clk_rx_i : in std_logic;
clk_aux_i: in std_logic;
dac_hpll_data_o : out std_logic_vector(15 downto 0);
dac_hpll_load_o : out std_logic;
dac_dmpll_data_o : out std_logic_vector(15 downto 0);
......@@ -313,5 +317,31 @@ package wrcore_pkg is
wb_irq_o : out std_logic;
debug_o: out std_logic_vector(3 downto 0));
end component;
component xwr_mini_nic
generic (
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity;
g_memsize_log2 : integer;
g_buffer_little_endian : boolean);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
mem_data_o : out std_logic_vector(31 downto 0);
mem_addr_o : out std_logic_vector(g_memsize_log2-1 downto 0);
mem_data_i : in std_logic_vector(31 downto 0);
mem_wr_o : out std_logic;
src_o : out t_wrf_source_out;
src_i : in t_wrf_source_in;
snk_o : out t_wrf_sink_out;
snk_i : in t_wrf_sink_in;
txtsu_port_id_i : in std_logic_vector(4 downto 0);
txtsu_frame_id_i : in std_logic_vector(16 - 1 downto 0);
txtsu_tsval_i : in std_logic_vector(28 + 4 - 1 downto 0);
txtsu_valid_i : in std_logic;
txtsu_ack_o : out std_logic;
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out);
end component;
end wrcore_pkg;
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