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White Rabbit core collection
Commit fc95e76a authored by Maciej Lipinski's avatar Maciej Lipinski
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[wr_streamers] added granurality to the overriding of default/application config with WB-config

parent 578e7f17
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Showing with 195 additions and 54 deletions
modules/wr_streamers/build_wb.sh
View file @ fc95e76a
#!/bin/bash
mkdir -p doc
wbgen2 -D ./doc/wr_transmission_wb.html -p wr_transmission_wbgen2_pkg.vhd -H record -V wr_transmission_wb.vhd --cstyle defines --lang vhdl -K ../../sim/wr_transmission_wb.svh wr_transmission_wb.wb
\ No newline at end of file
wbgen2 -C ./doc/wr_transmission.h -D ./doc/wr_transmission_wb.html -p wr_transmission_wbgen2_pkg.vhd -H record -V wr_transmission_wb.vhd --cstyle defines --lang vhdl -K ../../sim/wr_transmission_wb.svh wr_transmission_wb.wb
\ No newline at end of file
modules/wr_streamers/wr_transmission_wb.vhd
View file @ fc95e76a
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : wr_transmission_wb.vhd
-- Author : auto-generated by wbgen2 from wr_transmission_wb.wb
-- Created : Thu Nov 24 17:33:21 2016
-- Created : Wed Nov 30 10:02:17 2016
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_transmission_wb.wb
......@@ -55,8 +55,15 @@ signal wr_transmission_rx_cfg2_mac_local_msb_int : std_logic_vector(15 downto 0)
signal wr_transmission_rx_cfg3_mac_remote_lsb_int : std_logic_vector(31 downto 0);
signal wr_transmission_rx_cfg4_mac_remote_msb_int : std_logic_vector(15 downto 0);
signal wr_transmission_rx_cfg5_fixed_latency_int : std_logic_vector(27 downto 0);
signal wr_transmission_cfg_tx_ena_int : std_logic ;
signal wr_transmission_cfg_rx_ena_int : std_logic ;
signal wr_transmission_cfg_or_tx_ethtype_int : std_logic ;
signal wr_transmission_cfg_or_tx_mac_loc_int : std_logic ;
signal wr_transmission_cfg_or_tx_mac_tar_int : std_logic ;
signal wr_transmission_cfg_or_rx_ethertype_int : std_logic ;
signal wr_transmission_cfg_or_rx_mac_loc_int : std_logic ;
signal wr_transmission_cfg_or_rx_mac_rem_int : std_logic ;
signal wr_transmission_cfg_or_rx_acc_broadcast_int : std_logic ;
signal wr_transmission_cfg_or_rx_ftr_remote_int : std_logic ;
signal wr_transmission_cfg_or_rx_fix_lat_int : std_logic ;
signal wr_transmission_dbg_ctrl_mux_int : std_logic ;
signal wr_transmission_dbg_ctrl_start_byte_int : std_logic_vector(7 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
......@@ -102,8 +109,15 @@ begin
wr_transmission_rx_cfg3_mac_remote_lsb_int <= "00000000000000000000000000000000";
wr_transmission_rx_cfg4_mac_remote_msb_int <= "0000000000000000";
wr_transmission_rx_cfg5_fixed_latency_int <= "0000000000000000000000000000";
wr_transmission_cfg_tx_ena_int <= '0';
wr_transmission_cfg_rx_ena_int <= '0';
wr_transmission_cfg_or_tx_ethtype_int <= '0';
wr_transmission_cfg_or_tx_mac_loc_int <= '0';
wr_transmission_cfg_or_tx_mac_tar_int <= '0';
wr_transmission_cfg_or_rx_ethertype_int <= '0';
wr_transmission_cfg_or_rx_mac_loc_int <= '0';
wr_transmission_cfg_or_rx_mac_rem_int <= '0';
wr_transmission_cfg_or_rx_acc_broadcast_int <= '0';
wr_transmission_cfg_or_rx_ftr_remote_int <= '0';
wr_transmission_cfg_or_rx_fix_lat_int <= '0';
wr_transmission_dbg_ctrl_mux_int <= '0';
wr_transmission_dbg_ctrl_start_byte_int <= "00000000";
elsif rising_edge(clk_sys_i) then
......@@ -382,12 +396,25 @@ begin
ack_in_progress <= '1';
when "10110" =>
if (wb_we_i = '1') then
wr_transmission_cfg_tx_ena_int <= wrdata_reg(0);
wr_transmission_cfg_rx_ena_int <= wrdata_reg(1);
wr_transmission_cfg_or_tx_ethtype_int <= wrdata_reg(0);
wr_transmission_cfg_or_tx_mac_loc_int <= wrdata_reg(1);
wr_transmission_cfg_or_tx_mac_tar_int <= wrdata_reg(2);
wr_transmission_cfg_or_rx_ethertype_int <= wrdata_reg(16);
wr_transmission_cfg_or_rx_mac_loc_int <= wrdata_reg(17);
wr_transmission_cfg_or_rx_mac_rem_int <= wrdata_reg(18);
wr_transmission_cfg_or_rx_acc_broadcast_int <= wrdata_reg(19);
wr_transmission_cfg_or_rx_ftr_remote_int <= wrdata_reg(20);
wr_transmission_cfg_or_rx_fix_lat_int <= wrdata_reg(21);
end if;
rddata_reg(0) <= wr_transmission_cfg_tx_ena_int;
rddata_reg(1) <= wr_transmission_cfg_rx_ena_int;
rddata_reg(2) <= 'X';
rddata_reg(0) <= wr_transmission_cfg_or_tx_ethtype_int;
rddata_reg(1) <= wr_transmission_cfg_or_tx_mac_loc_int;
rddata_reg(2) <= wr_transmission_cfg_or_tx_mac_tar_int;
rddata_reg(16) <= wr_transmission_cfg_or_rx_ethertype_int;
rddata_reg(17) <= wr_transmission_cfg_or_rx_mac_loc_int;
rddata_reg(18) <= wr_transmission_cfg_or_rx_mac_rem_int;
rddata_reg(19) <= wr_transmission_cfg_or_rx_acc_broadcast_int;
rddata_reg(20) <= wr_transmission_cfg_or_rx_ftr_remote_int;
rddata_reg(21) <= wr_transmission_cfg_or_rx_fix_lat_int;
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
......@@ -401,12 +428,6 @@ begin
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
......@@ -554,10 +575,24 @@ begin
regs_o.rx_cfg4_mac_remote_msb_o <= wr_transmission_rx_cfg4_mac_remote_msb_int;
-- Fixed Latency
regs_o.rx_cfg5_fixed_latency_o <= wr_transmission_rx_cfg5_fixed_latency_int;
-- Enable WB TX CONFIG
regs_o.cfg_tx_ena_o <= wr_transmission_cfg_tx_ena_int;
-- Enable WB RX CONFIG
regs_o.cfg_rx_ena_o <= wr_transmission_cfg_rx_ena_int;
-- Tx Ethertype
regs_o.cfg_or_tx_ethtype_o <= wr_transmission_cfg_or_tx_ethtype_int;
-- Tx MAC Local
regs_o.cfg_or_tx_mac_loc_o <= wr_transmission_cfg_or_tx_mac_loc_int;
-- Tx MAC Target
regs_o.cfg_or_tx_mac_tar_o <= wr_transmission_cfg_or_tx_mac_tar_int;
-- Rx Ethertype
regs_o.cfg_or_rx_ethertype_o <= wr_transmission_cfg_or_rx_ethertype_int;
-- Rx MAC Local
regs_o.cfg_or_rx_mac_loc_o <= wr_transmission_cfg_or_rx_mac_loc_int;
-- Rx MAC Remote
regs_o.cfg_or_rx_mac_rem_o <= wr_transmission_cfg_or_rx_mac_rem_int;
-- Rx Accept Broadcast
regs_o.cfg_or_rx_acc_broadcast_o <= wr_transmission_cfg_or_rx_acc_broadcast_int;
-- Rx Filter Remote
regs_o.cfg_or_rx_ftr_remote_o <= wr_transmission_cfg_or_rx_ftr_remote_int;
-- Rx Fixed Latency
regs_o.cfg_or_rx_fix_lat_o <= wr_transmission_cfg_or_rx_fix_lat_int;
-- Debug Tx (0) or Rx (1)
regs_o.dbg_ctrl_mux_o <= wr_transmission_dbg_ctrl_mux_int;
-- Debug Start byte
......
modules/wr_streamers/wr_transmission_wb.wb
View file @ fc95e76a
......@@ -360,28 +360,106 @@ peripheral {
};
};
reg {
name = "TxRx Config";
name = "TxRx Config Override";
prefix = "CFG";
field {
name = "Enable WB TX CONFIG";
description = "Decide whether the transmission configuration of streamers should be the one provided as an input to the xwr_transmission module (either default, or provided by application-specifici module) or it should be the one provided in the WB registers:\
0: TX config loaded from application or default; \
1: TX config loaded from wishbone registers";
prefix = "tx_ena";
name = "Tx Ethertype";
description = "Overrides default/application Tx Ethertype configuration with configuration in the proper register:\
0: Default/set by application; \
1: Value from WB register";
prefix = "or_tx_ethtype";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Enable WB RX CONFIG";
description = "Decide whether the reception configuration of streamers should be the one provided as an input to the xwr_transmission module (either default, or provided by application-specifici module) or it should be the one provided in the WB registers:\
0: RX config loaded from application or default; \
1: RX config loaded from wishbone registers";
prefix = "rx_ena";
name = "Tx MAC Local";
description = "Overrides default/application Tx local MAC configuration with configuration in the proper register:\
0: Default/set by application; \
1: Value from WB register";
prefix = "or_tx_mac_loc";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Tx MAC Target";
description = "Overrides default/application Tx target MAC configuration with configuration in the proper register:\
0: Default/set by application; \
1: Value from WB register";
prefix = "or_tx_mac_tar";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Rx Ethertype";
description = "Overrides default/application Rx Ethertype configuration with configuration in the proper register:\
0: Default/set by application; \
1: Value from WB register";
prefix = "or_rx_ethertype";
type = BIT;
align=16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Rx MAC Local";
description = "Overrides default/application Rx MAC Local configuration with configuration in the proper register:\
0: Default/set by application; \
1: Value from WB register";
prefix = "or_rx_mac_loc";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Rx MAC Remote";
description = "Overrides default/application Rx MAC Remote configuration with configuration in the proper register:\
0: Default/set by application; \
1: Value from WB register";
prefix = "or_rx_mac_rem";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Rx Accept Broadcast";
description = "Overrides default/application Rx Accept Broardcast configuration with configuration in the proper register:\
0: Default/set by application; \
1: Value from WB register";
prefix = "or_rx_acc_broadcast";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Rx Filter Remote";
description = "Overrides default/application Rx Filter Remote configuration with configuration in the proper register:\
0: Default/set by application; \
1: Value from WB register";
prefix = "or_rx_ftr_remote";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Rx Fixed Latency ";
description = "Overrides default/application Rx fixed latency configuration with configuration in the proper register:\
0: Default/set by application; \
1: Value from WB register";
prefix = "or_rx_fix_lat";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "DBG Control register";
......
modules/wr_streamers/wr_transmission_wbgen2_pkg.vhd
View file @ fc95e76a
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : wr_transmission_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from wr_transmission_wb.wb
-- Created : Thu Nov 24 17:33:21 2016
-- Created : Wed Nov 30 10:02:17 2016
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_transmission_wb.wb
......@@ -76,8 +76,15 @@ package wr_transmission_wbgen2_pkg is
rx_cfg3_mac_remote_lsb_o : std_logic_vector(31 downto 0);
rx_cfg4_mac_remote_msb_o : std_logic_vector(15 downto 0);
rx_cfg5_fixed_latency_o : std_logic_vector(27 downto 0);
cfg_tx_ena_o : std_logic;
cfg_rx_ena_o : std_logic;
cfg_or_tx_ethtype_o : std_logic;
cfg_or_tx_mac_loc_o : std_logic;
cfg_or_tx_mac_tar_o : std_logic;
cfg_or_rx_ethertype_o : std_logic;
cfg_or_rx_mac_loc_o : std_logic;
cfg_or_rx_mac_rem_o : std_logic;
cfg_or_rx_acc_broadcast_o : std_logic;
cfg_or_rx_ftr_remote_o : std_logic;
cfg_or_rx_fix_lat_o : std_logic;
dbg_ctrl_mux_o : std_logic;
dbg_ctrl_start_byte_o : std_logic_vector(7 downto 0);
end record;
......@@ -99,8 +106,15 @@ package wr_transmission_wbgen2_pkg is
rx_cfg3_mac_remote_lsb_o => (others => '0'),
rx_cfg4_mac_remote_msb_o => (others => '0'),
rx_cfg5_fixed_latency_o => (others => '0'),
cfg_tx_ena_o => '0',
cfg_rx_ena_o => '0',
cfg_or_tx_ethtype_o => '0',
cfg_or_tx_mac_loc_o => '0',
cfg_or_tx_mac_tar_o => '0',
cfg_or_rx_ethertype_o => '0',
cfg_or_rx_mac_loc_o => '0',
cfg_or_rx_mac_rem_o => '0',
cfg_or_rx_acc_broadcast_o => '0',
cfg_or_rx_ftr_remote_o => '0',
cfg_or_rx_fix_lat_o => '0',
dbg_ctrl_mux_o => '0',
dbg_ctrl_start_byte_o => (others => '0')
);
......
modules/wr_streamers/xwr_transmission.vhd
View file @ fc95e76a
......@@ -481,31 +481,31 @@ begin
to_wb.dbg_tx_bvalue_i <= dbg_tx_bfield;
to_wb.dummy_dummy_i <= x"DEADBEEF";
tx_cfg_ethertype <= from_wb.tx_cfg0_ethertype_o when (from_wb.cfg_tx_ena_o='1') else
tx_cfg_ethertype <= from_wb.tx_cfg0_ethertype_o when (from_wb.cfg_or_tx_ethtype_o='1') else
tx_cfg_ethertype_i;
tx_cfg_mac_local(31 downto 0) <= from_wb.tx_cfg1_mac_local_lsb_o when (from_wb.cfg_tx_ena_o='1') else
tx_cfg_mac_local(31 downto 0) <= from_wb.tx_cfg1_mac_local_lsb_o when (from_wb.cfg_or_tx_mac_loc_o='1') else
tx_cfg_mac_local_i(31 downto 0);
tx_cfg_mac_local(47 downto 32) <= from_wb.tx_cfg2_mac_local_msb_o when (from_wb.cfg_tx_ena_o='1') else
tx_cfg_mac_local(47 downto 32) <= from_wb.tx_cfg2_mac_local_msb_o when (from_wb.cfg_or_tx_mac_loc_o='1') else
tx_cfg_mac_local_i(47 downto 32);
tx_cfg_mac_target(31 downto 0) <= from_wb.tx_cfg3_mac_target_lsb_o when (from_wb.cfg_tx_ena_o='1') else
tx_cfg_mac_target(31 downto 0) <= from_wb.tx_cfg3_mac_target_lsb_o when (from_wb.cfg_or_tx_mac_tar_o='1') else
tx_cfg_mac_target_i(31 downto 0);
tx_cfg_mac_target(47 downto 32)<= from_wb.tx_cfg4_mac_target_msb_o when (from_wb.cfg_tx_ena_o='1') else
tx_cfg_mac_target(47 downto 32)<= from_wb.tx_cfg4_mac_target_msb_o when (from_wb.cfg_or_tx_mac_tar_o='1') else
tx_cfg_mac_target_i(47 downto 32);
rx_cfg_ethertype <= from_wb.rx_cfg0_ethertype_o when (from_wb.cfg_rx_ena_o='1') else
rx_cfg_ethertype <= from_wb.rx_cfg0_ethertype_o when (from_wb.cfg_or_rx_ethertype_o='1') else
rx_cfg_ethertype_i;
rx_cfg_mac_local(31 downto 0) <= from_wb.rx_cfg1_mac_local_lsb_o when (from_wb.cfg_rx_ena_o='1') else
rx_cfg_mac_local(31 downto 0) <= from_wb.rx_cfg1_mac_local_lsb_o when (from_wb.cfg_or_rx_mac_loc_o='1') else
rx_cfg_mac_local_i(31 downto 0);
rx_cfg_mac_local(47 downto 32) <= from_wb.rx_cfg2_mac_local_msb_o when (from_wb.cfg_rx_ena_o='1') else
rx_cfg_mac_local(47 downto 32) <= from_wb.rx_cfg2_mac_local_msb_o when (from_wb.cfg_or_rx_mac_loc_o='1') else
rx_cfg_mac_local_i(47 downto 32);
rx_cfg_mac_remote(31 downto 0) <= from_wb.rx_cfg3_mac_remote_lsb_o when (from_wb.cfg_rx_ena_o='1') else
rx_cfg_mac_remote(31 downto 0) <= from_wb.rx_cfg3_mac_remote_lsb_o when (from_wb.cfg_or_rx_mac_rem_o='1') else
rx_cfg_mac_remote_i(31 downto 0);
rx_cfg_mac_remote(47 downto 32)<= from_wb.rx_cfg4_mac_remote_msb_o when (from_wb.cfg_rx_ena_o='1') else
rx_cfg_mac_remote(47 downto 32)<= from_wb.rx_cfg4_mac_remote_msb_o when (from_wb.cfg_or_rx_mac_rem_o='1') else
rx_cfg_mac_remote_i(47 downto 32);
rx_cfg_accept_broadcasts <= from_wb.rx_cfg0_accept_broadcast_o when (from_wb.cfg_rx_ena_o='1') else
rx_cfg_accept_broadcasts <= from_wb.rx_cfg0_accept_broadcast_o when (from_wb.cfg_or_rx_acc_broadcast_o='1') else
rx_cfg_accept_broadcasts_i;
rx_cfg_filter_remote <= from_wb.rx_cfg0_filter_remote_o when (from_wb.cfg_rx_ena_o='1') else
rx_cfg_filter_remote <= from_wb.rx_cfg0_filter_remote_o when (from_wb.cfg_or_rx_ftr_remote_o='1') else
rx_cfg_filter_remote_i;
rx_cfg_fixed_latency <= from_wb.rx_cfg5_fixed_latency_o when (from_wb.cfg_rx_ena_o='1') else
rx_cfg_fixed_latency <= from_wb.rx_cfg5_fixed_latency_o when (from_wb.cfg_or_rx_fix_lat_o='1') else
rx_cfg_fixed_latency_i;
end rtl;
\ No newline at end of file
sim/wr_transmission_wb.svh
View file @ fc95e76a
......@@ -77,10 +77,24 @@
`define WR_TRANSMISSION_RX_CFG5_FIXED_LATENCY_OFFSET 0
`define WR_TRANSMISSION_RX_CFG5_FIXED_LATENCY 32'h0fffffff
`define ADDR_WR_TRANSMISSION_CFG 7'h58
`define WR_TRANSMISSION_CFG_TX_ENA_OFFSET 0
`define WR_TRANSMISSION_CFG_TX_ENA 32'h00000001
`define WR_TRANSMISSION_CFG_RX_ENA_OFFSET 1
`define WR_TRANSMISSION_CFG_RX_ENA 32'h00000002
`define WR_TRANSMISSION_CFG_OR_TX_ETHTYPE_OFFSET 0
`define WR_TRANSMISSION_CFG_OR_TX_ETHTYPE 32'h00000001
`define WR_TRANSMISSION_CFG_OR_TX_MAC_LOC_OFFSET 1
`define WR_TRANSMISSION_CFG_OR_TX_MAC_LOC 32'h00000002
`define WR_TRANSMISSION_CFG_OR_TX_MAC_TAR_OFFSET 2
`define WR_TRANSMISSION_CFG_OR_TX_MAC_TAR 32'h00000004
`define WR_TRANSMISSION_CFG_OR_RX_ETHERTYPE_OFFSET 16
`define WR_TRANSMISSION_CFG_OR_RX_ETHERTYPE 32'h00010000
`define WR_TRANSMISSION_CFG_OR_RX_MAC_LOC_OFFSET 17
`define WR_TRANSMISSION_CFG_OR_RX_MAC_LOC 32'h00020000
`define WR_TRANSMISSION_CFG_OR_RX_MAC_REM_OFFSET 18
`define WR_TRANSMISSION_CFG_OR_RX_MAC_REM 32'h00040000
`define WR_TRANSMISSION_CFG_OR_RX_ACC_BROADCAST_OFFSET 19
`define WR_TRANSMISSION_CFG_OR_RX_ACC_BROADCAST 32'h00080000
`define WR_TRANSMISSION_CFG_OR_RX_FTR_REMOTE_OFFSET 20
`define WR_TRANSMISSION_CFG_OR_RX_FTR_REMOTE 32'h00100000
`define WR_TRANSMISSION_CFG_OR_RX_FIX_LAT_OFFSET 21
`define WR_TRANSMISSION_CFG_OR_RX_FIX_LAT 32'h00200000
`define ADDR_WR_TRANSMISSION_DBG_CTRL 7'h5c
`define WR_TRANSMISSION_DBG_CTRL_MUX_OFFSET 0
`define WR_TRANSMISSION_DBG_CTRL_MUX 32'h00000001
......
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