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Commit fcbff05d authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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wr_softpll_ng: added choice between DDMTD or bang-bang phase detector on each output channel 

Conflicts:

	modules/wr_softpll_ng/spll_wb_slave.vhd
	modules/wr_softpll_ng/spll_wbgen2_pkg.vhd
parent 0de330ee
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Showing with 241 additions and 448 deletions
modules/wr_softpll_ng/Manifest.py
View file @ fcbff05d
......@@ -3,4 +3,5 @@ files = ["spll_period_detect.vhd",
"spll_wbgen2_pkg.vhd",
"wr_softpll_ng.vhd",
"xwr_softpll_ng.vhd",
"softpll_pkg.vhd",
"spll_wb_slave.vhd"]
modules/wr_softpll_ng/softpll_pkg.vhd 0 → 100644
View file @ fcbff05d
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package softpll_pkg is
type t_softpll_phase_detector_type is (CH_DDMTD, CH_BANGBANG, CH_DISABLED);
type t_softpll_channel_config is
record
-- type of the phase detector to be used:
-- - CH_DISABLED: channel is not used.
-- - CH_DDMTD: same frequency as WR reference (125 MHz), but with phase shift
-- control
-- - CH_BANGBANG: Accumulating Bang-Bang detector: allows for N:M frequency ratios, but
-- without fine phase control. BB lock frequency is equal to 125 MHz *
-- bb_div_ref / bb_div_fb * 2.
channel_mode : t_softpll_phase_detector_type;
-- Index of the reference input. Relevant only for BB detectors, usually
-- set to 0 (local WR clock)
ref_input : integer;
-- Reference divider.
bb_div_ref : integer;
-- Feedback divider.
bb_div_fb : integer;
-- BB detector gating period, determines the bandwidth of the PLL. Phase
-- error samples are passed to SoftPLL software every 2**g_log2_gating reference
-- clock cycles.
bb_log2_gating : integer;
end record;
type t_softpll_channel_config_array is array(0 to 7) of t_softpll_channel_config;
constant c_softpll_channel_ddmtd : t_softpll_channel_config :=
(channel_mode => CH_DDMTD, others => 0);
constant c_softpll_channel_disabled : t_softpll_channel_config :=
(channel_mode => CH_DISABLED, others => 0);
constant c_softpll_channel_aux_100mhz : t_softpll_channel_config :=
(channel_mode => CH_BANGBANG,
ref_input => 0,
bb_div_ref => 5,
bb_div_fb => 8,
bb_log2_gating => 15);
constant c_softpll_default_channel_config : t_softpll_channel_config_array :=
(0 => c_softpll_channel_ddmtd,
1 => c_softpll_channel_aux_100mhz,
others => c_softpll_channel_disabled);
-- External 10 MHz input divider parameters.
constant c_softpll_ext_div_ref : integer := 8;
constant c_softpll_ext_div_fb : integer := 50;
constant c_softpll_ext_log2_gating : integer := 13;
end package;
package body softpll_pkg is
end softpll_pkg;
modules/wr_softpll_ng/spll_wb_slave.vhd
View file @ fcbff05d
This diff is collapsed.
modules/wr_softpll_ng/spll_wb_slave.wb
View file @ fcbff05d
......@@ -10,16 +10,6 @@ peripheral {
prefix = "CSR";
field {
align = 8;
name = "Period detector reference select";
prefix = "PER_SEL";
size = 6;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
align = 8;
name = "Number of reference channels (max: 32)";
......@@ -41,11 +31,11 @@ peripheral {
};
field {
name = "Enable Period Measurement";
prefix = "PER_EN";
name = "Debug queue supported";
prefix = "DBG_SUPPORTED";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
......@@ -110,36 +100,6 @@ peripheral {
};
---------------------------------------------
-- DMTD gating/undersampling configuration
---------------------------------------------
reg {
name = "DMTD Clock Control Register";
prefix = "DCCR";
field {
name = "DMTD Clock Undersampling Divider";
prefix = "GATE_DIV";
size = 6;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Reference Channel Undersampling Enable Register";
prefix = "RCGER";
field {
name = "Reference Channel Undersampling Enable";
prefix = "GATE_SEL";
size = 32;
type = PASS_THROUGH;
};
};
reg {
name = "Output Channel Control Register";
prefix = "OCCR";
......@@ -162,10 +122,20 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Output Channel Phase Detector Type";
description = "Phase detector type used by corresponding output: 0 = DDMTD, 1 = BangBang";
prefix = "OUT_DET_TYPE";
type = SLV;
size = 8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Reference Channel Enable Register";
name = "Reference Channel Tagging Enable Register";
prefix = "RCER";
field {
......@@ -181,7 +151,7 @@ peripheral {
};
reg {
name = "Output Channel Enable Register";
name = "Output Channel Tagging Enable Register";
prefix = "OCER";
field {
......@@ -196,32 +166,7 @@ peripheral {
};
};
reg {
name = "HPLL Period Error";
prefix = "PER_HPLL";
field {
name = "Period error value";
prefix = "ERROR";
type = SLV;
size = 16;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
ack_read = "tag_hpll_rd_period_o";
};
field {
name = "Period Error Valid";
prefix = "VALID";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
reg {
name = "Helper DAC Output";
prefix = "DAC_HPLL";
......@@ -253,7 +198,7 @@ peripheral {
};
reg {
name = "Deglitcher threshold";
name = "DDMTD Deglitcher threshold";
prefix = "DEGLITCH_THR";
field {
......
modules/wr_softpll_ng/spll_wbgen2_pkg.vhd
View file @ fcbff05d
......@@ -23,14 +23,14 @@ package spll_wbgen2_pkg is
type t_spll_in_registers is record
csr_n_ref_i : std_logic_vector(5 downto 0);
csr_n_out_i : std_logic_vector(2 downto 0);
csr_dbg_supported_i : std_logic;
eccr_ext_supported_i : std_logic;
eccr_align_done_i : std_logic;
eccr_ext_ref_present_i : std_logic;
occr_out_en_i : std_logic_vector(7 downto 0);
occr_out_det_type_i : std_logic_vector(7 downto 0);
rcer_i : std_logic_vector(31 downto 0);
ocer_i : std_logic_vector(7 downto 0);
per_hpll_error_i : std_logic_vector(15 downto 0);
per_hpll_valid_i : std_logic;
crr_in_i : std_logic_vector(31 downto 0);
crr_out_i : std_logic_vector(15 downto 0);
dfr_host_wr_req_i : std_logic;
......@@ -45,14 +45,14 @@ package spll_wbgen2_pkg is
constant c_spll_in_registers_init_value: t_spll_in_registers := (
csr_n_ref_i => (others => '0'),
csr_n_out_i => (others => '0'),
csr_dbg_supported_i => '0',
eccr_ext_supported_i => '0',
eccr_align_done_i => '0',
eccr_ext_ref_present_i => '0',
occr_out_en_i => (others => '0'),
occr_out_det_type_i => (others => '0'),
rcer_i => (others => '0'),
ocer_i => (others => '0'),
per_hpll_error_i => (others => '0'),
per_hpll_valid_i => '0',
crr_in_i => (others => '0'),
crr_out_i => (others => '0'),
dfr_host_wr_req_i => '0',
......@@ -67,13 +67,8 @@ package spll_wbgen2_pkg is
-- Output registers (WB slave -> user design)
type t_spll_out_registers is record
csr_per_sel_o : std_logic_vector(5 downto 0);
csr_per_en_o : std_logic;
eccr_ext_en_o : std_logic;
eccr_align_en_o : std_logic;
dccr_gate_div_o : std_logic_vector(5 downto 0);
rcger_gate_sel_o : std_logic_vector(31 downto 0);
rcger_gate_sel_wr_o : std_logic;
occr_out_lock_o : std_logic_vector(7 downto 0);
rcer_o : std_logic_vector(31 downto 0);
rcer_load_o : std_logic;
......@@ -102,13 +97,8 @@ package spll_wbgen2_pkg is
end record;
constant c_spll_out_registers_init_value: t_spll_out_registers := (
csr_per_sel_o => (others => '0'),
csr_per_en_o => '0',
eccr_ext_en_o => '0',
eccr_align_en_o => '0',
dccr_gate_div_o => (others => '0'),
rcger_gate_sel_o => (others => '0'),
rcger_gate_sel_wr_o => '0',
occr_out_lock_o => (others => '0'),
rcer_o => (others => '0'),
rcer_load_o => '0',
......@@ -166,14 +156,14 @@ variable tmp: t_spll_in_registers;
begin
tmp.csr_n_ref_i := f_x_to_zero(left.csr_n_ref_i) or f_x_to_zero(right.csr_n_ref_i);
tmp.csr_n_out_i := f_x_to_zero(left.csr_n_out_i) or f_x_to_zero(right.csr_n_out_i);
tmp.csr_dbg_supported_i := f_x_to_zero(left.csr_dbg_supported_i) or f_x_to_zero(right.csr_dbg_supported_i);
tmp.eccr_ext_supported_i := f_x_to_zero(left.eccr_ext_supported_i) or f_x_to_zero(right.eccr_ext_supported_i);
tmp.eccr_align_done_i := f_x_to_zero(left.eccr_align_done_i) or f_x_to_zero(right.eccr_align_done_i);
tmp.eccr_ext_ref_present_i := f_x_to_zero(left.eccr_ext_ref_present_i) or f_x_to_zero(right.eccr_ext_ref_present_i);
tmp.occr_out_en_i := f_x_to_zero(left.occr_out_en_i) or f_x_to_zero(right.occr_out_en_i);
tmp.occr_out_det_type_i := f_x_to_zero(left.occr_out_det_type_i) or f_x_to_zero(right.occr_out_det_type_i);
tmp.rcer_i := f_x_to_zero(left.rcer_i) or f_x_to_zero(right.rcer_i);
tmp.ocer_i := f_x_to_zero(left.ocer_i) or f_x_to_zero(right.ocer_i);
tmp.per_hpll_error_i := f_x_to_zero(left.per_hpll_error_i) or f_x_to_zero(right.per_hpll_error_i);
tmp.per_hpll_valid_i := f_x_to_zero(left.per_hpll_valid_i) or f_x_to_zero(right.per_hpll_valid_i);
tmp.crr_in_i := f_x_to_zero(left.crr_in_i) or f_x_to_zero(right.crr_in_i);
tmp.crr_out_i := f_x_to_zero(left.crr_out_i) or f_x_to_zero(right.crr_out_i);
tmp.dfr_host_wr_req_i := f_x_to_zero(left.dfr_host_wr_req_i) or f_x_to_zero(right.dfr_host_wr_req_i);
......
modules/wr_softpll_ng/wr_softpll_ng.vhd
View file @ fcbff05d
This diff is collapsed.
modules/wr_softpll_ng/xwr_softpll_ng.vhd
View file @ fcbff05d
......@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2011-01-29
-- Last update: 2012-07-09
-- Last update: 2012-12-04
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -40,6 +40,7 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
use work.softpll_pkg.all;
entity xwr_softpll_ng is
generic(
......@@ -55,12 +56,6 @@ entity xwr_softpll_ng is
g_num_ref_inputs : integer := 1;
g_num_outputs : integer := 1;
-- When true, an additional period detector is provided, measuring the
-- frequency offset between the DDMTD clock and a chosen reference input clock.
-- The feature is not required by the current version of the SoftPLL servo
-- algorithm, but is kept for testing/debugging purposes.
g_with_period_detector : boolean := false;
-- When true, an additional FIFO is instantiated, providing a realtime record
-- of user-selectable SoftPLL parameters (e.g. tag values, phase error, DAC drive).
-- These values can be read by "spll_dbg_proxy" daemon for further analysis.
......@@ -71,12 +66,6 @@ entity xwr_softpll_ng is
-- (e.g. GPSDO/Cesium 10 MHz)
g_with_ext_clock_input : boolean := false;
-- When true, the SoftPLL can undersample measured signals by dividing the DMTD
-- clock by a progammable ratio, so that one can perform phase shift
-- measurements of clocks with frequencies different than the base rate of the
-- DMTD oscillator.
g_with_undersampling : boolean := false;
-- When true, DDMTD inputs are reverse (so that the DDMTD offset clocks is
-- being sampled by the measured clock). This is functionally equivalent to
-- "direct" operation, but may improve FPGA timing/routability.
......@@ -85,16 +74,10 @@ entity xwr_softpll_ng is
-- Divides the DDMTD clock inputs by 2, removing the "CLOCK_DEDICATED_ROUTE"
-- errors under ISE tools, at the cost of bandwidth reduction. Use with care.
g_divide_input_by_2 : boolean := false;
-- Bang Bang phase detector parameters:
-- reference divider
g_bb_ref_divider : integer := 1;
-- feedback divider
g_bb_feedback_divider : integer := 1;
-- phase error measurement gating
g_bb_log2_gating : integer := 10;
-- Configuration of all output channels (phase detector type & dividers). See
-- softpll_pkg.vhd for details.
g_channels_config : t_softpll_channel_config_array := c_softpll_default_channel_config;
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := BYTE
......@@ -144,22 +127,16 @@ end xwr_softpll_ng;
architecture wrapper of xwr_softpll_ng is
component wr_softpll_ng
generic (
g_tag_bits : integer;
g_num_ref_inputs : integer;
g_num_outputs : integer;
g_with_period_detector : boolean;
g_with_debug_fifo : boolean;
g_with_ext_clock_input : boolean;
g_with_undersampling : boolean;
g_reverse_dmtds : boolean;
g_divide_input_by_2 : boolean;
g_bb_ref_divider : integer;
g_bb_feedback_divider : integer;
g_bb_log2_gating : integer;
g_channels_config : t_softpll_channel_config_array;
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity);
port (
......@@ -201,14 +178,10 @@ begin -- behavioral
g_num_ref_inputs => g_num_ref_inputs,
g_num_outputs => g_num_outputs,
g_with_debug_fifo => g_with_debug_fifo,
g_with_period_detector => g_with_period_detector,
g_with_undersampling => g_with_undersampling,
g_with_ext_clock_input => g_with_ext_clock_input,
g_reverse_dmtds => g_reverse_dmtds,
g_divide_input_by_2 => g_divide_input_by_2,
g_bb_ref_divider => g_bb_ref_divider,
g_bb_feedback_divider => g_bb_feedback_divider,
g_bb_log2_gating => g_bb_log2_gating
g_channels_config => g_channels_config
)
port map (
clk_sys_i => clk_sys_i,
......
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