added knitex7 reference design files

fdc90d25 · Peter Jansweijer · Grzegorz Daniluk · dc1a2f63 · fdc90d25 · fdc90d25
Commit fdc90d25 authored Sep 14, 2015 by Peter Jansweijer Committed by Grzegorz Daniluk Sep 28, 2015
3 changed files
--- a/top/kintex7_ref_design/wr_core_demo/ext_pll_10_to_125m.vhd
+++ b/top/kintex7_ref_design/wr_core_demo/ext_pll_10_to_125m.vhd
+-- file: ext_pll_10_to_125m.vhd
+-- 
+-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
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+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
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+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
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+-- Applications"). Customer assumes the sole risk and
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+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+------------------------------------------------------------------------------
+-- User entered comments
+------------------------------------------------------------------------------
+-- None
+--
+------------------------------------------------------------------------------
+-- "Output    Output      Phase     Duty      Pk-to-Pk        Phase"
+-- "Clock    Freq (MHz) (degrees) Cycle (%) Jitter (ps)  Error (ps)"
+------------------------------------------------------------------------------
+-- CLK_OUT1___125.000______0.000______50.0_____1014.602____150.000
+--
+------------------------------------------------------------------------------
+-- "Input Clock   Freq (MHz)    Input Jitter (UI)"
+------------------------------------------------------------------------------
+-- __primary__________10.000____________0.010
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+use ieee.numeric_std.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity ext_pll_10_to_125m is
+port
+ (-- Clock in ports
+  clk_ext_i           : in     std_logic;
+  -- Clock out ports
+  clk_ext_mul_o          : out    std_logic;
+  -- Status and control signals
+  rst_a_i             : in     std_logic;
+  locked_o            : out    std_logic
+ );
+end ext_pll_10_to_125m;
+
+architecture xilinx of ext_pll_10_to_125m is
+  attribute CORE_GENERATION_INFO : string;
+  attribute CORE_GENERATION_INFO of xilinx : architecture is "ext_pll_10_to_125m,clk_wiz_v3_6,{component_name=ext_pll_10_to_125m,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=true,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=1,clkin1_period=100.000,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";
+	  -- Input clock buffering / unused connectors
+  signal clkin1            : std_logic;
+  -- Output clock buffering
+  signal clkfb             : std_logic;
+  signal clk0              : std_logic;
+  signal clkfbout          : std_logic;
+  signal locked_internal   : std_logic;
+  signal status_internal   : std_logic_vector(7 downto 0);
+begin
+
+
+  -- Input buffering
+  --------------------------------------
+  clkin1 <= clk_ext_i;
+
+
+  -- Clocking primitive
+  --------------------------------------
+ 
+  -- Instantiation of the MMCM primitive
+  --    * Unused inputs are tied off
+  --    * Unused outputs are labeled unused
+  mmcm_adv_inst : MMCME2_ADV
+  generic map
+   (BANDWIDTH            => "LOW",
+    CLKOUT4_CASCADE      => FALSE,
+    COMPENSATION         => "ZHOLD",
+    STARTUP_WAIT         => FALSE,
+    DIVCLK_DIVIDE        => 1,
+    CLKFBOUT_MULT_F      => 62.500,
+    CLKFBOUT_PHASE       => 0.000,
+    CLKFBOUT_USE_FINE_PS => FALSE,
+    CLKOUT0_DIVIDE_F     => 5.000,
+    CLKOUT0_PHASE        => 0.000,
+    CLKOUT0_DUTY_CYCLE   => 0.500,
+    CLKOUT0_USE_FINE_PS  => FALSE,
+    CLKIN1_PERIOD        => 100.000,
+    REF_JITTER1          => 0.005)
+  port map
+    -- Output clocks
+   (CLKFBOUT            => clkfb,
+    CLKFBOUTB           => open,
+    CLKOUT0             => clk0,
+    CLKOUT0B            => open,
+    CLKOUT1             => open,
+    CLKOUT1B            => open,
+    CLKOUT2             => open,
+    CLKOUT2B            => open,
+    CLKOUT3             => open,
+    CLKOUT3B            => open,
+    CLKOUT4             => open,
+    CLKOUT5             => open,
+    CLKOUT6             => open,
+    -- Input clock control
+    CLKFBIN             => clkfbout,
+    CLKIN1              => clkin1,
+    CLKIN2              => '0',
+    -- Tied to always select the primary input clock
+    CLKINSEL            => '1',
+    -- Ports for dynamic reconfiguration
+    DADDR               => (others => '0'),
+    DCLK                => '0',
+    DEN                 => '0',
+    DI                  => (others => '0'),
+    DO                  => open,
+    DRDY                => open,
+    DWE                 => '0',
+    -- Ports for dynamic phase shift
+    PSCLK               => '0',
+    PSEN                => '0',
+    PSINCDEC            => '0',
+    PSDONE              => open,
+    -- Other control and status signals
+    LOCKED              => locked_internal,
+    CLKINSTOPPED        => open,
+    CLKFBSTOPPED        => open,
+    PWRDWN              => '0',
+    RST                 => rst_a_i);
+
+
+
+  clkout1_buf : BUFG
+  port map
+   (O   => clk_ext_mul_o,
+    I   => clk0);
+
+
+
+end xilinx;
--- a/top/kintex7_ref_design/wr_core_demo/kintex7_top.vhd
+++ b/top/kintex7_ref_design/wr_core_demo/kintex7_top.vhd
--- a/top/kintex7_ref_design/wr_core_demo/spec_reset_gen.vhd
+++ b/top/kintex7_ref_design/wr_core_demo/spec_reset_gen.vhd
+library ieee;
+use ieee.STD_LOGIC_1164.all;
+use ieee.NUMERIC_STD.all;
+
+use work.gencores_pkg.all;
+
+entity spec_reset_gen is
+  
+  port (
+    clk_sys_i : in std_logic;
+
+    rst_pcie_n_a_i   : in std_logic;
+    rst_button_n_a_i : in std_logic;
+
+    rst_n_o : out std_logic
+    );
+
+end spec_reset_gen;
+
+architecture behavioral of spec_reset_gen is
+
+  signal powerup_cnt     : unsigned(7 downto 0) := x"00";
+  signal button_synced_n : std_logic;
+  signal pcie_synced_n   : std_logic;
+  signal powerup_n       : std_logic            := '0';
+
+begin  -- behavioral
+
+  U_EdgeDet_PCIe : gc_sync_ffs port map (
+    clk_i    => clk_sys_i,
+    rst_n_i  => '1',
+    data_i   => rst_pcie_n_a_i,
+    ppulse_o => pcie_synced_n);
+
+  U_Sync_Button : gc_sync_ffs port map (
+    clk_i    => clk_sys_i,
+    rst_n_i  => '1',
+    data_i   => rst_button_n_a_i,
+    synced_o => button_synced_n);
+
+  p_powerup_reset : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if(powerup_cnt /= x"ff") then
+        powerup_cnt <= powerup_cnt + 1;
+        powerup_n   <= '0';
+      else
+        powerup_n <= '1';
+      end if;
+    end if;
+  end process;
+
+  rst_n_o <= powerup_n and button_synced_n and (not pcie_synced_n);
+
+end behavioral;