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Commit fe8ab3dd authored by Tomasz Wlostowski's avatar Tomasz Wlostowski Committed by Grzegorz Daniluk
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wr_softpll_ng: initial version of DMTD-based external reference PLL 

Conflicts:

	ip_cores/etherbone-core
	ip_cores/general-cores
	ip_cores/gn4124-core
	modules/wrc_core/wrcore_pkg.vhd
	modules/wrc_core/xwr_core.vhd
	syn/spec_1_1/wr_core_demo/Manifest.py
	syn/spec_1_1/wr_core_demo/spec_top_wrc.xise
parent 3c10d567
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Showing with 1232 additions and 889 deletions
modules/timing/dmtd_with_deglitcher.vhd
View file @ fe8ab3dd
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski -- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT -- Company : CERN BE-Co-HT
-- Created : 2010-02-25 -- Created : 2010-02-25
-- Last update: 2013-07-29 -- Last update: 2014-07-15
-- Platform : FPGA-generic -- Platform : FPGA-generic
-- Standard : VHDL '93 -- Standard : VHDL '93
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -132,7 +132,6 @@ architecture rtl of dmtd_with_deglitcher is ...@@ -132,7 +132,6 @@ architecture rtl of dmtd_with_deglitcher is
signal stab_cntr : unsigned(15 downto 0); signal stab_cntr : unsigned(15 downto 0);
signal free_cntr : unsigned(g_counter_bits-1 downto 0); signal free_cntr : unsigned(g_counter_bits-1 downto 0);
signal in_d0, in_d1 : std_logic;
signal s_one : std_logic; signal s_one : std_logic;
signal clk_in : std_logic; signal clk_in : std_logic;
......
modules/wr_pps_gen/wr_pps_gen.vhd
View file @ fe8ab3dd
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski -- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT -- Company : CERN BE-Co-HT
-- Created : 2010-09-02 -- Created : 2010-09-02
-- Last update: 2013-08-05 -- Last update: 2014-07-15
-- Platform : FPGA-generics -- Platform : FPGA-generics
-- Standard : VHDL -- Standard : VHDL
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -180,49 +180,14 @@ architecture behavioral of wr_pps_gen is ...@@ -180,49 +180,14 @@ architecture behavioral of wr_pps_gen is
signal retime_counter : unsigned(4 downto 0); signal retime_counter : unsigned(4 downto 0);
signal pps_valid_int : std_logic; signal pps_valid_int : std_logic;
signal pps_out_int : std_logic; signal pps_out_int : std_logic;
signal pps_in_refclk : std_logic;
component chipscope_icon
port (
CONTROL0 : inout std_logic_vector(35 downto 0));
end component;
component chipscope_ila
port (
CONTROL : inout std_logic_vector(35 downto 0);
CLK : in std_logic;
TRIG0 : in std_logic_vector(31 downto 0);
TRIG1 : in std_logic_vector(31 downto 0);
TRIG2 : in std_logic_vector(31 downto 0);
TRIG3 : in std_logic_vector(31 downto 0));
end component;
signal control0 : std_logic_vector(35 downto 0);
signal trig0, trig1, trig2, trig3 : std_logic_vector(31 downto 0);
begin -- behavioral begin -- behavioral
--CS_ICON : chipscope_icon
-- port map (
-- CONTROL0 => CONTROL0);
--CS_ILA : chipscope_ila
-- port map (
-- CONTROL => CONTROL0,
-- CLK => clk_sys_i,
-- TRIG0 => TRIG0,
-- TRIG1 => TRIG1,
-- TRIG2 => TRIG2,
-- TRIG3 => TRIG3);
TRIG0(cntr_pps_ext'length-1 downto 0) <= std_logic_vector(cntr_pps_ext);
TRIG1(0) <= pps_ext_retimed;
TRIG1(1) <= pps_in_i;
TRIG1(6 downto 2) <= std_logic_vector(retime_counter);
TRIG1(7) <= pps_ext_d0;
resized_addr(4 downto 0) <= wb_adr_i; resized_addr(4 downto 0) <= wb_adr_i;
resized_addr(c_wishbone_address_width-1 downto 5) <= (others => '0'); resized_addr(c_wishbone_address_width-1 downto 5) <= (others => '0');
...@@ -250,7 +215,7 @@ begin -- behavioral ...@@ -250,7 +215,7 @@ begin -- behavioral
sl_stall_o => wb_stall_o); sl_stall_o => wb_stall_o);
sync_reset_refclk : gc_sync_ffs U_Sync_reset_refclk : gc_sync_ffs
generic map ( generic map (
g_sync_edge => "positive") g_sync_edge => "positive")
port map ( port map (
...@@ -261,6 +226,15 @@ begin -- behavioral ...@@ -261,6 +226,15 @@ begin -- behavioral
npulse_o => open, npulse_o => open,
ppulse_o => open); ppulse_o => open);
U_Sync_pps_refclk : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => clk_ref_i,
rst_n_i => '1',
data_i => pps_in_i,
ppulse_o => pps_in_refclk);
ppsg_cntr_nsec <= std_logic_vector(cntr_nsec); ppsg_cntr_nsec <= std_logic_vector(cntr_nsec);
ppsg_cntr_utclo <= std_logic_vector(cntr_utc(31 downto 0)); ppsg_cntr_utclo <= std_logic_vector(cntr_utc(31 downto 0));
...@@ -290,80 +264,36 @@ begin -- behavioral ...@@ -290,80 +264,36 @@ begin -- behavioral
end if; end if;
end process; end process;
gen_with_external_clock_input : if(g_with_ext_clock_input) generate gen_without_external_clock_input : if(not g_with_ext_clock_input) generate
ext_sync_p <= '0';
-- retime the external PPS pulse. The output (pps_ext_retimed) is: end generate gen_without_external_clock_input;
-- single clk_ext_i cycle-wide
-- produced one cycle in advance with respect to the original PPS
p_retime_external_pps : process(clk_ext_i)
begin
if rising_edge(clk_ext_i) then
if rst_n_i = '0' then
cntr_pps_ext <= (others => '0');
pps_ext_d0 <= '0';
pps_ext_retimed <= '0';
else
pps_ext_d0 <= pps_in_i;
if(cntr_pps_ext = g_ext_clock_rate-1) then
pps_ext_retimed <= '1';
else
pps_ext_retimed <= '0';
end if;
if(pps_in_i = '1' and pps_ext_d0 = '0') then
cntr_pps_ext <= to_unsigned(1, cntr_pps_ext'length);
elsif(cntr_pps_ext /= g_ext_clock_rate) then
cntr_pps_ext <= cntr_pps_ext + 1;
end if;
end if;
end if;
end process;
p_retime_counter : process(clk_ref_i)
begin
if falling_edge(clk_ref_i) then
if rst_synced_refclk = '0' or sync_in_progress = '0' or pps_ext_retimed = '0' then
retime_counter <= (others => '0');
else
retime_counter <= retime_counter + 1;
end if;
end if;
end process;
gen_with_external_clock_input : if(g_with_ext_clock_input) generate
-- Warning! this state machine inputs pps_ext_retimed signal,
-- which is produced in different clock domain than clk_ref_i.
-- Run only when EXT channel of the SoftPLL is LOCKED!
p_external_sync : process(clk_ref_i) p_external_sync : process(clk_ref_i)
begin begin
if falling_edge(clk_ref_i) then if falling_edge(clk_ref_i) then
if(rst_synced_refclk = '0') then if(rst_synced_refclk = '0') then
ext_sync_p <= '0';
sync_in_progress <= '0'; sync_in_progress <= '0';
ppsg_escr_sync_in <= '0'; ppsg_escr_sync_in <= '0';
else else
if(ppsg_escr_sync_load = '1') then if(ppsg_escr_sync_load = '1') then
sync_in_progress <= ppsg_escr_sync_out; sync_in_progress <= ppsg_escr_sync_out;
ppsg_escr_sync_in <= '0'; ppsg_escr_sync_in <= '0';
end if;
-- retime counter == last faster clock edge inside the retimed PPS
-- pulse -> we should sync ourselves
if(sync_in_progress = '1' and pps_ext_retimed = '1' and retime_counter = (g_ref_clock_rate / g_ext_clock_rate - 1)) then
ext_sync_p <= '1';
sync_in_progress <= '0';
ppsg_escr_sync_in <= '1';
else else
ext_sync_p <= '0'; if(sync_in_progress = '1' and pps_in_refclk = '1')
then
ext_sync_p <= '1';
sync_in_progress <= '0';
ppsg_escr_sync_in <= '1';
else
ext_sync_p <= '0';
end if;
end if; end if;
end if; end if;
end if; end if;
end process; end process;
end generate gen_with_external_clock_input; end generate gen_with_external_clock_input;
-- Nanosecond counter. Counts from 0 to c_PERIOD-1 every clk_ref_i cycle. -- Nanosecond counter. Counts from 0 to c_PERIOD-1 every clk_ref_i cycle.
......
modules/wr_softpll_ng/Manifest.py
View file @ fe8ab3dd
files = ["spll_period_detect.vhd", files = ["spll_period_detect.vhd",
"spll_bangbang_pd.vhd", # "spll_bangbang_pd.vhd",
"spll_wbgen2_pkg.vhd", "spll_wbgen2_pkg.vhd",
"spll_aligner.vhd",
"wr_softpll_ng.vhd", "wr_softpll_ng.vhd",
"xwr_softpll_ng.vhd", "xwr_softpll_ng.vhd",
"softpll_pkg.vhd", "softpll_pkg.vhd",
......
modules/wr_softpll_ng/softpll_pkg.vhd
View file @ fe8ab3dd
...@@ -6,18 +6,24 @@ use ieee.numeric_std.all; ...@@ -6,18 +6,24 @@ use ieee.numeric_std.all;
package softpll_pkg is package softpll_pkg is
constant c_softpll_max_aux_clocks : integer := 8; constant c_softpll_max_aux_clocks : integer := 8;
type t_softpll_phase_detector_type is (CH_DDMTD, CH_BANGBANG); type t_softpll_phase_detector_type is (CH_DDMTD, CH_BANGBANG);
type t_softpll_channel_config_array is array(0 to c_softpll_max_aux_clocks-1) of t_softpll_phase_detector_type; type t_softpll_channel_config_array is array(0 to c_softpll_max_aux_clocks-1) of t_softpll_phase_detector_type;
constant c_softpll_default_channel_config : t_softpll_channel_config_array := (others => CH_DDMTD); constant c_softpll_default_channel_config : t_softpll_channel_config_array := (others => CH_DDMTD);
-- External 10 MHz input divider parameters. -- External 10 MHz input divider parameters.
constant c_softpll_ext_div_ref : integer := 8; constant c_softpll_ext_div_ref : integer := 8;
constant c_softpll_ext_div_fb : integer := 50; constant c_softpll_ext_div_fb : integer := 50;
constant c_softpll_ext_log2_gating : integer := 13; constant c_softpll_ext_log2_gating : integer := 13;
constant c_softpll_out_status_off : std_logic_vector(3 downto 0) := "0000";
constant c_softpll_out_status_locking : std_logic_vector(3 downto 0) := "0001";
constant c_softpll_out_status_locked : std_logic_vector(3 downto 0) := "0010";
constant c_softpll_out_status_aligning : std_logic_vector(3 downto 0) := "0011";
constant c_softpll_out_status_holdover : std_logic_vector(3 downto 0) := "0100";
end package; end package;
package body softpll_pkg is package body softpll_pkg is
......
modules/wr_softpll_ng/spll_aligner.vhd 0 → 100644
View file @ fe8ab3dd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gencores_pkg.all;
entity spll_aligner is
generic (
g_counter_width : integer := 28;
g_ref_clock_rate : integer := 125000000;
g_in_clock_rate : integer := 10000000;
g_sample_rate : integer := 100
);
port (
clk_sys_i : in std_logic;
clk_in_i : in std_logic;
clk_ref_i : in std_logic;
rst_n_sys_i : in std_logic;
pps_ext_a_i : in std_logic;
pps_csync_p1_i : in std_logic;
sample_cref_o : out std_logic_vector(g_counter_width-1 downto 0);
sample_cin_o : out std_logic_vector(g_counter_width-1 downto 0);
sample_pps_o : out std_logic;
sample_valid_o : out std_logic;
sample_ack_i : in std_logic
);
end spll_aligner;
architecture rtl of spll_aligner is
constant c_div_ticks : integer := g_ref_clock_rate / g_sample_rate;
signal cnt_ref_bin, cnt_in_bin, cnt_in_bin_x : unsigned(g_counter_width-1 downto 0);
signal cnt_in_gray, cnt_in_gray_x, cnt_in_gray_xd : std_logic_vector(g_counter_width-1 downto 0);
signal cnt_ref_div : unsigned(g_counter_width-1 downto 0);
signal pps_ext_p, pps_ext_d0 : std_logic;
signal rst_n_in, rst_n_ref : std_logic;
signal ref_div_p : std_logic;
signal sample_ready_p : std_logic;
begin
U_Reset_IN : gc_sync_ffs
port map (
clk_i => clk_in_i,
rst_n_i => '1',
data_i => rst_n_sys_i,
synced_o => rst_n_in);
U_Reset_REF : gc_sync_ffs
port map (
clk_i => clk_ref_i,
rst_n_i => '1',
data_i => rst_n_sys_i,
synced_o => rst_n_ref);
p_ref_counter : process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
if pps_csync_p1_i = '1' or rst_n_ref = '0' then
cnt_ref_bin <= to_unsigned(0, g_counter_width);
elsif(cnt_ref_bin = g_ref_clock_rate - 1) then
cnt_ref_bin <= (others => '0');
else
cnt_ref_bin <= cnt_ref_bin + 1;
end if;
end if;
end process;
p_samplerate_divider : process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
if pps_csync_p1_i = '1' or rst_n_ref = '0' then
ref_div_p <= '0';
cnt_ref_div <= to_unsigned(0, g_counter_width);
elsif (cnt_ref_div = c_div_ticks - 2) then
ref_div_p <= '1';
cnt_ref_div <= cnt_ref_div + 1;
elsif (cnt_ref_div = c_div_ticks - 1) then
ref_div_p <= '0';
cnt_ref_div <= (others => '0');
else
ref_div_p <= '0';
cnt_ref_div <= cnt_ref_div + 1;
end if;
end if;
end process;
p_delay_ext_pps : process(clk_in_i)
begin
if rising_edge(clk_in_i) then
pps_ext_d0 <= pps_ext_a_i;
end if;
end process;
pps_ext_p <= not pps_ext_d0 and pps_ext_a_i;
p_in_counter : process(clk_in_i)
begin
if rising_edge(clk_in_i) then
if pps_ext_p = '1' or rst_n_in = '0' then
cnt_in_bin <= to_unsigned(2, g_counter_width);
elsif(cnt_in_bin = g_in_clock_rate - 1) then
cnt_in_bin <= (others => '0');
else
cnt_in_bin <= cnt_in_bin + 1;
end if;
end if;
end process;
p_in_bin2gray : process (clk_in_i)
begin
if rising_edge(clk_in_i) then
cnt_in_gray <= f_gray_encode (std_logic_vector(cnt_in_bin));
end if;
end process;
p_sample_difference : process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
cnt_in_gray_x <= cnt_in_gray;
cnt_in_gray_xd <= cnt_in_gray_x;
if(ref_div_p = '1') then
sample_cin_o <= f_gray_decode(cnt_in_gray_xd, 1);
sample_cref_o <= std_logic_vector (cnt_ref_bin);
end if;
end if;
end process;
U_sync_sampling : gc_pulse_synchronizer2
port map (
clk_in_i => clk_ref_i,
rst_in_n_i => rst_n_ref,
clk_out_i => clk_sys_i,
rst_out_n_i => rst_n_sys_i,
d_p_i => ref_div_p,
q_p_o => sample_ready_p);
p_gen_sample_valid : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_sys_i = '0' then
sample_valid_o <= '0';
else
if sample_ready_p = '1' then
sample_valid_o <= '1';
elsif sample_ack_i = '1' then
sample_valid_o <= '0';
end if;
end if;
end if;
end process;
end rtl;
modules/wr_softpll_ng/spll_wb_slave.vhd
View file @ fe8ab3dd
This diff is collapsed.
modules/wr_softpll_ng/spll_wb_slave.wb
View file @ fe8ab3dd
...@@ -54,17 +54,15 @@ peripheral { ...@@ -54,17 +54,15 @@ peripheral {
reg { reg {
name = "External Clock Control Register"; name = "External Clock Control Register";
prefix = "ECCR"; prefix = "ECCR";
field { field {
name = "Enable External Clock BB Detector"; name = "Enable External Clock PLL";
prefix = "EXT_EN"; prefix = "EXT_EN";
type = BIT; type = BIT;
access_bus = READ_WRITE; access_bus = READ_WRITE;
access_dev = READ_ONLY; access_dev = READ_ONLY;
}; };
field { field {
name = "External Clock Input Available"; name = "External Clock Input Available";
description = "1: This instance of wr_softpll_ng supports external 10MHz clock input\ description = "1: This instance of wr_softpll_ng supports external 10MHz clock input\
...@@ -75,28 +73,6 @@ peripheral { ...@@ -75,28 +73,6 @@ peripheral {
access_dev = WRITE_ONLY; access_dev = WRITE_ONLY;
}; };
field {
name = "Enable PPS/phase alignment";
description = "write 1: starts aligning the external and local oscillator clock edges to be in phase\
right after the pulse on SYNC (PPS) input.\
write 0: no effect.";
prefix = "ALIGN_EN";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "PPS/phase alignment done";
description = "1: phase alignment triggered by writing to ALIGN_EN done.\
0: phase alignment in progress.";
prefix = "ALIGN_DONE";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field { field {
name = "External Clock Reference Present"; name = "External Clock Reference Present";
description = "1: Reference clock present on the input\ description = "1: Reference clock present on the input\
...@@ -106,54 +82,121 @@ peripheral { ...@@ -106,54 +82,121 @@ peripheral {
access_bus = READ_ONLY; access_bus = READ_ONLY;
access_dev = WRITE_ONLY; access_dev = WRITE_ONLY;
}; };
};
reg {
name = "Aligner Control Register";
prefix = "AL_CR";
field {
name = "Aligner sample valid/select on channel";
prefix = "VALID";
type = SLV;
size = 9;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "Aligner required on channel";
prefix = "REQUIRED";
type = SLV;
size = 9;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Aligner Counter REF register";
prefix = "AL_CREF";
field {
name = "Aligner reference counter";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Aligner Counter IN register";
prefix = "AL_CIN";
field {
name = "Aligner reference counter";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
}; };
reg { reg {
align = 4; name = "DMTD VCO Frequency";
name = "Output Channel Control Register"; prefix = "F_DMTD";
prefix = "OCCR";
field { field {
align = 8; name = "FREQ";
name = "Output Channel HW enable flag"; prefix = "FREQ";
prefix = "OUT_EN";
type = SLV; type = SLV;
size = 8; size = 28;
access_bus = READ_ONLY; access_bus = READ_ONLY;
access_dev = WRITE_ONLY; access_dev = WRITE_ONLY;
}; };
field { field {
name = "Output Channel locked flag"; name = "VALID";
prefix = "OUT_LOCK"; prefix = "VALID";
type = SLV; type = BIT;
size = 8;
access_bus = READ_WRITE; access_bus = READ_WRITE;
access_dev = READ_ONLY; access_dev = READ_WRITE;
load = LOAD_EXT;
}; };
};
field { reg {
name = "Output Channel Phase Detector Type"; name = "REF VCO Frequency";
description = "Phase detector type used by corresponding output: 0 = DDMTD, 1 = BangBang"; prefix = "F_REF";
prefix = "OUT_DET_TYPE";
field {
name = "FREQ";
prefix = "FREQ";
type = SLV; type = SLV;
size = 8; size = 28;
access_bus = READ_ONLY; access_bus = READ_ONLY;
access_dev = WRITE_ONLY; access_dev = WRITE_ONLY;
}; };
field {
name = "VALID";
prefix = "VALID";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
}; };
reg { reg {
name = "Reference Channel Tagging Enable Register"; name = "EXT VCO Frequency";
prefix = "RCER"; prefix = "F_EXT";
field { field {
name = "Reference Channel Enable"; name = "FREQ";
description = "write 1: enables tag generation on the input channel corresponding to the written bit\ prefix = "FREQ";
write 0: disables tag generation";
type = SLV; type = SLV;
size = 32; size = 28;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "VALID";
prefix = "VALID";
type = BIT;
access_bus = READ_WRITE; access_bus = READ_WRITE;
access_dev = READ_WRITE; access_dev = READ_WRITE;
load = LOAD_EXT; load = LOAD_EXT;
...@@ -161,21 +204,62 @@ peripheral { ...@@ -161,21 +204,62 @@ peripheral {
}; };
reg { reg {
name = "Output Channel Tagging Enable Register"; align = 4;
prefix = "OCER"; name = "Output Channel Control Register";
prefix = "OCCR";
field { field {
name = "Output Channel Enable"; align = 8;
description = "write 1: enables tag generation on the output channel corresponding to the written bit\ name = "Output Channel HW enable flag";
write 0: disables tag generation"; prefix = "OUT_EN";
type = SLV;
size = 8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Output Channel locked flag";
prefix = "OUT_LOCK";
type = SLV; type = SLV;
size = 8; size = 8;
access_bus = READ_WRITE; access_bus = READ_WRITE;
access_dev = READ_WRITE; access_dev = READ_ONLY;
load = LOAD_EXT;
}; };
}; };
reg {
name = "Reference Channel Tagging Enable Register";
prefix = "RCER";
field {
name = "Reference Channel Enable";
description = "write 1: enables tag generation on the input channel corresponding to the written bit\
write 0: disables tag generation";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "Output Channel Tagging Enable Register";
prefix = "OCER";
field {
name = "Output Channel Enable";
description = "write 1: enables tag generation on the output channel corresponding to the written bit\
write 0: disables tag generation";
type = SLV;
size = 8;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg { reg {
align = 8; align = 8;
name = "Helper DAC Output"; name = "Helper DAC Output";
...@@ -240,41 +324,8 @@ peripheral { ...@@ -240,41 +324,8 @@ peripheral {
}; };
}; };
reg {
name = "Counter Resync Register - input channels";
prefix = "CRR_IN";
field {
name = "Counter Resync";
description = "write 1: triggers resynchronization of this channel's DDMTD free-running counter with Out Clock 0\
write 0: no effect\
read 1: resync in progress\
read 0: resync done";
size = 32;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "Counter Resync Register - output channels";
prefix = "CRR_OUT";
field {
name = "Counter Resync";
description = "write 1: triggers resynchronization of this channel's DDMTD free-running counter with Out Clock 0\
write 0: no effect";
size = 16;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
fifo_reg { fifo_reg {
name = "Debug FIFO Register - Host side"; name = "Debug FIFO Register - Host side";
prefix = "DFR_HOST"; prefix = "DFR_HOST";
direction = CORE_TO_BUS; direction = CORE_TO_BUS;
...@@ -331,43 +382,6 @@ peripheral { ...@@ -331,43 +382,6 @@ peripheral {
}; };
}; };
reg {
name = "Aux clock configuration register";
prefix = "AUX_CR";
field {
name = "Aux output select";
prefix = "AUX_SEL";
size = 3;
type = PASS_THROUGH;
};
field {
name = "BB reference divider";
description = "Reference clock division factor. Applicable only for aux channels with BB phase detector.";
prefix = "DIV_REF";
size = 6;
type = PASS_THROUGH;
};
field {
name = "BB feedback divider";
description = "Reference clock division factor. Applicable only for aux channels with BB phase detector.";
prefix = "DIV_FB";
size = 6;
type = PASS_THROUGH;
};
field {
name = "BB gating frequency select";
description = "BB detector output gating frequency. GATE = log2(period in clk_ref cycles).";
prefix = "GATE";
size = 4;
type = PASS_THROUGH;
};
};
irq { irq {
name = "Got a tag"; name = "Got a tag";
......
modules/wr_softpll_ng/spll_wbgen2_pkg.vhd
View file @ fe8ab3dd
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- File : spll_wbgen2_pkg.vhd -- File : spll_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from spll_wb_slave.wb -- Author : auto-generated by wbgen2 from spll_wb_slave.wb
-- Created : Thu Jul 25 11:14:53 2013 -- Created : Tue Jul 15 17:31:20 2014
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE spll_wb_slave.wb -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE spll_wb_slave.wb
...@@ -25,14 +25,20 @@ package spll_wbgen2_pkg is ...@@ -25,14 +25,20 @@ package spll_wbgen2_pkg is
csr_n_out_i : std_logic_vector(2 downto 0); csr_n_out_i : std_logic_vector(2 downto 0);
csr_dbg_supported_i : std_logic; csr_dbg_supported_i : std_logic;
eccr_ext_supported_i : std_logic; eccr_ext_supported_i : std_logic;
eccr_align_done_i : std_logic;
eccr_ext_ref_present_i : std_logic; eccr_ext_ref_present_i : std_logic;
al_cr_valid_i : std_logic_vector(8 downto 0);
al_cr_required_i : std_logic_vector(8 downto 0);
al_cref_i : std_logic_vector(31 downto 0);
al_cin_i : std_logic_vector(31 downto 0);
f_dmtd_freq_i : std_logic_vector(27 downto 0);
f_dmtd_valid_i : std_logic;
f_ref_freq_i : std_logic_vector(27 downto 0);
f_ref_valid_i : std_logic;
f_ext_freq_i : std_logic_vector(27 downto 0);
f_ext_valid_i : std_logic;
occr_out_en_i : std_logic_vector(7 downto 0); occr_out_en_i : std_logic_vector(7 downto 0);
occr_out_det_type_i : std_logic_vector(7 downto 0);
rcer_i : std_logic_vector(31 downto 0); rcer_i : std_logic_vector(31 downto 0);
ocer_i : std_logic_vector(7 downto 0); ocer_i : std_logic_vector(7 downto 0);
crr_in_i : std_logic_vector(31 downto 0);
crr_out_i : std_logic_vector(15 downto 0);
dfr_host_wr_req_i : std_logic; dfr_host_wr_req_i : std_logic;
dfr_host_value_i : std_logic_vector(31 downto 0); dfr_host_value_i : std_logic_vector(31 downto 0);
dfr_host_seq_id_i : std_logic_vector(15 downto 0); dfr_host_seq_id_i : std_logic_vector(15 downto 0);
...@@ -47,14 +53,20 @@ package spll_wbgen2_pkg is ...@@ -47,14 +53,20 @@ package spll_wbgen2_pkg is
csr_n_out_i => (others => '0'), csr_n_out_i => (others => '0'),
csr_dbg_supported_i => '0', csr_dbg_supported_i => '0',
eccr_ext_supported_i => '0', eccr_ext_supported_i => '0',
eccr_align_done_i => '0',
eccr_ext_ref_present_i => '0', eccr_ext_ref_present_i => '0',
al_cr_valid_i => (others => '0'),
al_cr_required_i => (others => '0'),
al_cref_i => (others => '0'),
al_cin_i => (others => '0'),
f_dmtd_freq_i => (others => '0'),
f_dmtd_valid_i => '0',
f_ref_freq_i => (others => '0'),
f_ref_valid_i => '0',
f_ext_freq_i => (others => '0'),
f_ext_valid_i => '0',
occr_out_en_i => (others => '0'), occr_out_en_i => (others => '0'),
occr_out_det_type_i => (others => '0'),
rcer_i => (others => '0'), rcer_i => (others => '0'),
ocer_i => (others => '0'), ocer_i => (others => '0'),
crr_in_i => (others => '0'),
crr_out_i => (others => '0'),
dfr_host_wr_req_i => '0', dfr_host_wr_req_i => '0',
dfr_host_value_i => (others => '0'), dfr_host_value_i => (others => '0'),
dfr_host_seq_id_i => (others => '0'), dfr_host_seq_id_i => (others => '0'),
...@@ -68,7 +80,14 @@ package spll_wbgen2_pkg is ...@@ -68,7 +80,14 @@ package spll_wbgen2_pkg is
type t_spll_out_registers is record type t_spll_out_registers is record
eccr_ext_en_o : std_logic; eccr_ext_en_o : std_logic;
eccr_align_en_o : std_logic; al_cr_valid_o : std_logic_vector(8 downto 0);
al_cr_valid_load_o : std_logic;
f_dmtd_valid_o : std_logic;
f_dmtd_valid_load_o : std_logic;
f_ref_valid_o : std_logic;
f_ref_valid_load_o : std_logic;
f_ext_valid_o : std_logic;
f_ext_valid_load_o : std_logic;
occr_out_lock_o : std_logic_vector(7 downto 0); occr_out_lock_o : std_logic_vector(7 downto 0);
rcer_o : std_logic_vector(31 downto 0); rcer_o : std_logic_vector(31 downto 0);
rcer_load_o : std_logic; rcer_load_o : std_logic;
...@@ -85,28 +104,23 @@ package spll_wbgen2_pkg is ...@@ -85,28 +104,23 @@ package spll_wbgen2_pkg is
dfr_spll_value_wr_o : std_logic; dfr_spll_value_wr_o : std_logic;
dfr_spll_eos_o : std_logic; dfr_spll_eos_o : std_logic;
dfr_spll_eos_wr_o : std_logic; dfr_spll_eos_wr_o : std_logic;
crr_in_o : std_logic_vector(31 downto 0);
crr_in_load_o : std_logic;
crr_out_o : std_logic_vector(15 downto 0);
crr_out_load_o : std_logic;
dfr_host_wr_full_o : std_logic; dfr_host_wr_full_o : std_logic;
dfr_host_wr_empty_o : std_logic; dfr_host_wr_empty_o : std_logic;
dfr_host_wr_usedw_o : std_logic_vector(12 downto 0); dfr_host_wr_usedw_o : std_logic_vector(12 downto 0);
trr_wr_full_o : std_logic; trr_wr_full_o : std_logic;
trr_wr_empty_o : std_logic; trr_wr_empty_o : std_logic;
aux_cr_aux_sel_o : std_logic_vector(2 downto 0);
aux_cr_aux_sel_wr_o : std_logic;
aux_cr_div_ref_o : std_logic_vector(5 downto 0);
aux_cr_div_ref_wr_o : std_logic;
aux_cr_div_fb_o : std_logic_vector(5 downto 0);
aux_cr_div_fb_wr_o : std_logic;
aux_cr_gate_o : std_logic_vector(3 downto 0);
aux_cr_gate_wr_o : std_logic;
end record; end record;
constant c_spll_out_registers_init_value: t_spll_out_registers := ( constant c_spll_out_registers_init_value: t_spll_out_registers := (
eccr_ext_en_o => '0', eccr_ext_en_o => '0',
eccr_align_en_o => '0', al_cr_valid_o => (others => '0'),
al_cr_valid_load_o => '0',
f_dmtd_valid_o => '0',
f_dmtd_valid_load_o => '0',
f_ref_valid_o => '0',
f_ref_valid_load_o => '0',
f_ext_valid_o => '0',
f_ext_valid_load_o => '0',
occr_out_lock_o => (others => '0'), occr_out_lock_o => (others => '0'),
rcer_o => (others => '0'), rcer_o => (others => '0'),
rcer_load_o => '0', rcer_load_o => '0',
...@@ -123,23 +137,11 @@ package spll_wbgen2_pkg is ...@@ -123,23 +137,11 @@ package spll_wbgen2_pkg is
dfr_spll_value_wr_o => '0', dfr_spll_value_wr_o => '0',
dfr_spll_eos_o => '0', dfr_spll_eos_o => '0',
dfr_spll_eos_wr_o => '0', dfr_spll_eos_wr_o => '0',
crr_in_o => (others => '0'),
crr_in_load_o => '0',
crr_out_o => (others => '0'),
crr_out_load_o => '0',
dfr_host_wr_full_o => '0', dfr_host_wr_full_o => '0',
dfr_host_wr_empty_o => '0', dfr_host_wr_empty_o => '0',
dfr_host_wr_usedw_o => (others => '0'), dfr_host_wr_usedw_o => (others => '0'),
trr_wr_full_o => '0', trr_wr_full_o => '0',
trr_wr_empty_o => '0', trr_wr_empty_o => '0'
aux_cr_aux_sel_o => (others => '0'),
aux_cr_aux_sel_wr_o => '0',
aux_cr_div_ref_o => (others => '0'),
aux_cr_div_ref_wr_o => '0',
aux_cr_div_fb_o => (others => '0'),
aux_cr_div_fb_wr_o => '0',
aux_cr_gate_o => (others => '0'),
aux_cr_gate_wr_o => '0'
); );
function "or" (left, right: t_spll_in_registers) return t_spll_in_registers; function "or" (left, right: t_spll_in_registers) return t_spll_in_registers;
function f_x_to_zero (x:std_logic) return std_logic; function f_x_to_zero (x:std_logic) return std_logic;
...@@ -149,11 +151,11 @@ end package; ...@@ -149,11 +151,11 @@ end package;
package body spll_wbgen2_pkg is package body spll_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is function f_x_to_zero (x:std_logic) return std_logic is
begin begin
if(x = 'X' or x = 'U') then if x = '1' then
return '0'; return '1';
else else
return x; return '0';
end if; end if;
end function; end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0); variable tmp: std_logic_vector(x'length-1 downto 0);
...@@ -174,14 +176,20 @@ tmp.csr_n_ref_i := f_x_to_zero(left.csr_n_ref_i) or f_x_to_zero(right.csr_n_ref_ ...@@ -174,14 +176,20 @@ tmp.csr_n_ref_i := f_x_to_zero(left.csr_n_ref_i) or f_x_to_zero(right.csr_n_ref_
tmp.csr_n_out_i := f_x_to_zero(left.csr_n_out_i) or f_x_to_zero(right.csr_n_out_i); tmp.csr_n_out_i := f_x_to_zero(left.csr_n_out_i) or f_x_to_zero(right.csr_n_out_i);
tmp.csr_dbg_supported_i := f_x_to_zero(left.csr_dbg_supported_i) or f_x_to_zero(right.csr_dbg_supported_i); tmp.csr_dbg_supported_i := f_x_to_zero(left.csr_dbg_supported_i) or f_x_to_zero(right.csr_dbg_supported_i);
tmp.eccr_ext_supported_i := f_x_to_zero(left.eccr_ext_supported_i) or f_x_to_zero(right.eccr_ext_supported_i); tmp.eccr_ext_supported_i := f_x_to_zero(left.eccr_ext_supported_i) or f_x_to_zero(right.eccr_ext_supported_i);
tmp.eccr_align_done_i := f_x_to_zero(left.eccr_align_done_i) or f_x_to_zero(right.eccr_align_done_i);
tmp.eccr_ext_ref_present_i := f_x_to_zero(left.eccr_ext_ref_present_i) or f_x_to_zero(right.eccr_ext_ref_present_i); tmp.eccr_ext_ref_present_i := f_x_to_zero(left.eccr_ext_ref_present_i) or f_x_to_zero(right.eccr_ext_ref_present_i);
tmp.al_cr_valid_i := f_x_to_zero(left.al_cr_valid_i) or f_x_to_zero(right.al_cr_valid_i);
tmp.al_cr_required_i := f_x_to_zero(left.al_cr_required_i) or f_x_to_zero(right.al_cr_required_i);
tmp.al_cref_i := f_x_to_zero(left.al_cref_i) or f_x_to_zero(right.al_cref_i);
tmp.al_cin_i := f_x_to_zero(left.al_cin_i) or f_x_to_zero(right.al_cin_i);
tmp.f_dmtd_freq_i := f_x_to_zero(left.f_dmtd_freq_i) or f_x_to_zero(right.f_dmtd_freq_i);
tmp.f_dmtd_valid_i := f_x_to_zero(left.f_dmtd_valid_i) or f_x_to_zero(right.f_dmtd_valid_i);
tmp.f_ref_freq_i := f_x_to_zero(left.f_ref_freq_i) or f_x_to_zero(right.f_ref_freq_i);
tmp.f_ref_valid_i := f_x_to_zero(left.f_ref_valid_i) or f_x_to_zero(right.f_ref_valid_i);
tmp.f_ext_freq_i := f_x_to_zero(left.f_ext_freq_i) or f_x_to_zero(right.f_ext_freq_i);
tmp.f_ext_valid_i := f_x_to_zero(left.f_ext_valid_i) or f_x_to_zero(right.f_ext_valid_i);
tmp.occr_out_en_i := f_x_to_zero(left.occr_out_en_i) or f_x_to_zero(right.occr_out_en_i); tmp.occr_out_en_i := f_x_to_zero(left.occr_out_en_i) or f_x_to_zero(right.occr_out_en_i);
tmp.occr_out_det_type_i := f_x_to_zero(left.occr_out_det_type_i) or f_x_to_zero(right.occr_out_det_type_i);
tmp.rcer_i := f_x_to_zero(left.rcer_i) or f_x_to_zero(right.rcer_i); tmp.rcer_i := f_x_to_zero(left.rcer_i) or f_x_to_zero(right.rcer_i);
tmp.ocer_i := f_x_to_zero(left.ocer_i) or f_x_to_zero(right.ocer_i); tmp.ocer_i := f_x_to_zero(left.ocer_i) or f_x_to_zero(right.ocer_i);
tmp.crr_in_i := f_x_to_zero(left.crr_in_i) or f_x_to_zero(right.crr_in_i);
tmp.crr_out_i := f_x_to_zero(left.crr_out_i) or f_x_to_zero(right.crr_out_i);
tmp.dfr_host_wr_req_i := f_x_to_zero(left.dfr_host_wr_req_i) or f_x_to_zero(right.dfr_host_wr_req_i); tmp.dfr_host_wr_req_i := f_x_to_zero(left.dfr_host_wr_req_i) or f_x_to_zero(right.dfr_host_wr_req_i);
tmp.dfr_host_value_i := f_x_to_zero(left.dfr_host_value_i) or f_x_to_zero(right.dfr_host_value_i); tmp.dfr_host_value_i := f_x_to_zero(left.dfr_host_value_i) or f_x_to_zero(right.dfr_host_value_i);
tmp.dfr_host_seq_id_i := f_x_to_zero(left.dfr_host_seq_id_i) or f_x_to_zero(right.dfr_host_seq_id_i); tmp.dfr_host_seq_id_i := f_x_to_zero(left.dfr_host_seq_id_i) or f_x_to_zero(right.dfr_host_seq_id_i);
......
modules/wr_softpll_ng/wr_softpll_ng.vhd
View file @ fe8ab3dd
This diff is collapsed.
modules/wr_softpll_ng/xwr_softpll_ng.vhd
View file @ fe8ab3dd
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski -- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT -- Company : CERN BE-CO-HT
-- Created : 2011-01-29 -- Created : 2011-01-29
-- Last update: 2013-07-25 -- Last update: 2014-07-15
-- Platform : FPGA-generic -- Platform : FPGA-generic
-- Standard : VHDL'93 -- Standard : VHDL'93
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -74,10 +74,9 @@ entity xwr_softpll_ng is ...@@ -74,10 +74,9 @@ entity xwr_softpll_ng is
-- Divides the DDMTD clock inputs by 2, removing the "CLOCK_DEDICATED_ROUTE" -- Divides the DDMTD clock inputs by 2, removing the "CLOCK_DEDICATED_ROUTE"
-- errors under ISE tools, at the cost of bandwidth reduction. Use with care. -- errors under ISE tools, at the cost of bandwidth reduction. Use with care.
g_divide_input_by_2 : boolean := false; g_divide_input_by_2 : boolean := false;
-- Configuration of all output channels (phase detector type & dividers). See g_ref_clock_rate : integer := 125000000;
-- softpll_pkg.vhd for details. g_ext_clock_rate : integer := 10000000;
g_channels_config : t_softpll_channel_config_array := c_softpll_default_channel_config;
g_interface_mode : t_wishbone_interface_mode := PIPELINED; g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := BYTE g_address_granularity : t_wishbone_address_granularity := BYTE
...@@ -99,9 +98,14 @@ entity xwr_softpll_ng is ...@@ -99,9 +98,14 @@ entity xwr_softpll_ng is
-- g_with_ext_clock_input == true -- g_with_ext_clock_input == true
clk_ext_i : in std_logic; clk_ext_i : in std_logic;
-- External clock, multiplied to 125 MHz using the FPGA's PLL
clk_ext_mul_i : in std_logic;
-- External clock sync/alignment singnal. SoftPLL will clk_ext_i/clk_fb_i(0) -- External clock sync/alignment singnal. SoftPLL will clk_ext_i/clk_fb_i(0)
-- to match the edges immediately following the rising edge in sync_p_i. -- to match the edges immediately following the rising edge in sync_p_i.
sync_p_i : in std_logic; pps_csync_p1_i : in std_logic;
pps_ext_a_i : in std_logic;
-- DMTD oscillator drive -- DMTD oscillator drive
dac_dmtd_data_o : out std_logic_vector(15 downto 0); dac_dmtd_data_o : out std_logic_vector(15 downto 0);
...@@ -115,6 +119,7 @@ entity xwr_softpll_ng is ...@@ -115,6 +119,7 @@ entity xwr_softpll_ng is
out_enable_i : in std_logic_vector(g_num_outputs-1 downto 0); out_enable_i : in std_logic_vector(g_num_outputs-1 downto 0);
out_locked_o : out std_logic_vector(g_num_outputs-1 downto 0); out_locked_o : out std_logic_vector(g_num_outputs-1 downto 0);
out_status_o : out std_logic_vector(4*g_num_outputs-1 downto 0);
slave_i : in t_wishbone_slave_in; slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out; slave_o : out t_wishbone_slave_out;
...@@ -126,7 +131,6 @@ entity xwr_softpll_ng is ...@@ -126,7 +131,6 @@ entity xwr_softpll_ng is
end xwr_softpll_ng; end xwr_softpll_ng;
architecture wrapper of xwr_softpll_ng is architecture wrapper of xwr_softpll_ng is
component wr_softpll_ng component wr_softpll_ng
generic ( generic (
g_tag_bits : integer; g_tag_bits : integer;
...@@ -136,7 +140,8 @@ architecture wrapper of xwr_softpll_ng is ...@@ -136,7 +140,8 @@ architecture wrapper of xwr_softpll_ng is
g_with_ext_clock_input : boolean; g_with_ext_clock_input : boolean;
g_reverse_dmtds : boolean; g_reverse_dmtds : boolean;
g_divide_input_by_2 : boolean; g_divide_input_by_2 : boolean;
g_channels_config : t_softpll_channel_config_array; g_ref_clock_rate : integer;
g_ext_clock_rate : integer;
g_interface_mode : t_wishbone_interface_mode; g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity); g_address_granularity : t_wishbone_address_granularity);
port ( port (
...@@ -146,7 +151,9 @@ architecture wrapper of xwr_softpll_ng is ...@@ -146,7 +151,9 @@ architecture wrapper of xwr_softpll_ng is
clk_fb_i : in std_logic_vector(g_num_outputs-1 downto 0); clk_fb_i : in std_logic_vector(g_num_outputs-1 downto 0);
clk_dmtd_i : in std_logic; clk_dmtd_i : in std_logic;
clk_ext_i : in std_logic; clk_ext_i : in std_logic;
sync_p_i : in std_logic; clk_ext_mul_i : in std_logic;
pps_csync_p1_i : in std_logic;
pps_ext_a_i : in std_logic;
dac_dmtd_data_o : out std_logic_vector(15 downto 0); dac_dmtd_data_o : out std_logic_vector(15 downto 0);
dac_dmtd_load_o : out std_logic; dac_dmtd_load_o : out std_logic;
dac_out_data_o : out std_logic_vector(15 downto 0); dac_out_data_o : out std_logic_vector(15 downto 0);
...@@ -154,11 +161,13 @@ architecture wrapper of xwr_softpll_ng is ...@@ -154,11 +161,13 @@ architecture wrapper of xwr_softpll_ng is
dac_out_load_o : out std_logic; dac_out_load_o : out std_logic;
out_enable_i : in std_logic_vector(g_num_outputs-1 downto 0); out_enable_i : in std_logic_vector(g_num_outputs-1 downto 0);
out_locked_o : out std_logic_vector(g_num_outputs-1 downto 0); out_locked_o : out std_logic_vector(g_num_outputs-1 downto 0);
wb_adr_i : in std_logic_vector(6 downto 0); out_status_o : out std_logic_vector(4*g_num_outputs-1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0); wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0);
wb_cyc_i : in std_logic; wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_sel_i : in std_logic_vector(3 downto 0); wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
wb_stb_i : in std_logic; wb_stb_i : in std_logic;
wb_we_i : in std_logic; wb_we_i : in std_logic;
wb_ack_o : out std_logic; wb_ack_o : out std_logic;
...@@ -181,7 +190,8 @@ begin -- behavioral ...@@ -181,7 +190,8 @@ begin -- behavioral
g_with_ext_clock_input => g_with_ext_clock_input, g_with_ext_clock_input => g_with_ext_clock_input,
g_reverse_dmtds => g_reverse_dmtds, g_reverse_dmtds => g_reverse_dmtds,
g_divide_input_by_2 => g_divide_input_by_2, g_divide_input_by_2 => g_divide_input_by_2,
g_channels_config => g_channels_config g_ref_clock_rate => g_ref_clock_rate,
g_ext_clock_rate => g_ext_clock_rate
) )
port map ( port map (
clk_sys_i => clk_sys_i, clk_sys_i => clk_sys_i,
...@@ -190,7 +200,9 @@ begin -- behavioral ...@@ -190,7 +200,9 @@ begin -- behavioral
clk_fb_i => clk_fb_i, clk_fb_i => clk_fb_i,
clk_dmtd_i => clk_dmtd_i, clk_dmtd_i => clk_dmtd_i,
clk_ext_i => clk_ext_i, clk_ext_i => clk_ext_i,
sync_p_i => sync_p_i, clk_ext_mul_i => clk_ext_mul_i,
pps_csync_p1_i => pps_csync_p1_i,
pps_ext_a_i => pps_ext_a_i,
dac_dmtd_data_o => dac_dmtd_data_o, dac_dmtd_data_o => dac_dmtd_data_o,
dac_dmtd_load_o => dac_dmtd_load_o, dac_dmtd_load_o => dac_dmtd_load_o,
dac_out_data_o => dac_out_data_o, dac_out_data_o => dac_out_data_o,
...@@ -198,7 +210,7 @@ begin -- behavioral ...@@ -198,7 +210,7 @@ begin -- behavioral
dac_out_load_o => dac_out_load_o, dac_out_load_o => dac_out_load_o,
out_enable_i => out_enable_i, out_enable_i => out_enable_i,
out_locked_o => out_locked_o, out_locked_o => out_locked_o,
wb_adr_i => slave_i.adr(6 downto 0), wb_adr_i => slave_i.adr,
wb_dat_i => slave_i.dat, wb_dat_i => slave_i.dat,
wb_dat_o => slave_o.dat, wb_dat_o => slave_o.dat,
wb_cyc_i => slave_i.cyc, wb_cyc_i => slave_i.cyc,
......
modules/wrc_core/wr_core.vhd
View file @ fe8ab3dd
...@@ -5,7 +5,7 @@ ...@@ -5,7 +5,7 @@
-- Author : Grzegorz Daniluk -- Author : Grzegorz Daniluk
-- Company : Elproma -- Company : Elproma
-- Created : 2011-02-02 -- Created : 2011-02-02
-- Last update: 2013-03-20 -- Last update: 2014-07-15
-- Platform : FPGA-generics -- Platform : FPGA-generics
-- Standard : VHDL -- Standard : VHDL
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -113,6 +113,8 @@ entity wr_core is ...@@ -113,6 +113,8 @@ entity wr_core is
-- Aux clocks (i.e. the FMC clock), which can be disciplined by the WR Core -- Aux clocks (i.e. the FMC clock), which can be disciplined by the WR Core
clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0'); clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
clk_ext_mul_i : in std_logic := '0';
-- External 10 MHz reference (cesium, GPSDO, etc.), used in Grandmaster mode -- External 10 MHz reference (cesium, GPSDO, etc.), used in Grandmaster mode
clk_ext_i : in std_logic := '0'; clk_ext_i : in std_logic := '0';
...@@ -508,7 +510,8 @@ begin ...@@ -508,7 +510,8 @@ begin
g_address_granularity => BYTE, g_address_granularity => BYTE,
g_num_ref_inputs => 1, g_num_ref_inputs => 1,
g_num_outputs => 1 + g_aux_clks, g_num_outputs => 1 + g_aux_clks,
g_channels_config => g_softpll_channels_config) g_ref_clock_rate => 125000000,
g_ext_clock_rate => 10000000)
port map( port map(
clk_sys_i => clk_sys_i, clk_sys_i => clk_sys_i,
rst_n_i => rst_net_n, rst_n_i => rst_net_n,
...@@ -520,8 +523,11 @@ begin ...@@ -520,8 +523,11 @@ begin
-- DMTD Offset clock -- DMTD Offset clock
clk_dmtd_i => clk_dmtd_i, clk_dmtd_i => clk_dmtd_i,
clk_ext_i => clk_ext_i, clk_ext_i => clk_ext_i,
sync_p_i => pps_ext_i, clk_ext_mul_i => clk_ext_mul_i,
pps_csync_p1_i => s_pps_csync,
pps_ext_a_i => pps_ext_i,
-- DMTD oscillator drive -- DMTD oscillator drive
dac_dmtd_data_o => dac_hpll_data_o, dac_dmtd_data_o => dac_hpll_data_o,
......
modules/wrc_core/wrcore_pkg.vhd
View file @ fe8ab3dd
...@@ -242,18 +242,20 @@ package wrcore_pkg is ...@@ -242,18 +242,20 @@ package wrcore_pkg is
version => x"00000002", version => x"00000002",
date => x"20120305", date => x"20120305",
name => "WR-Soft-PLL "))); name => "WR-Soft-PLL ")));
component xwr_softpll_ng component xwr_softpll_ng
generic ( generic (
g_tag_bits : integer; g_tag_bits : integer;
g_num_ref_inputs : integer; g_num_ref_inputs : integer;
g_num_outputs : integer; g_num_outputs : integer;
g_with_debug_fifo : boolean := false; g_with_debug_fifo : boolean;
g_with_ext_clock_input : boolean := false; g_with_ext_clock_input : boolean;
g_reverse_dmtds : boolean := false; g_reverse_dmtds : boolean;
g_divide_input_by_2 : boolean := false; g_divide_input_by_2 : boolean;
g_ref_clock_rate : integer;
g_ext_clock_rate : integer;
g_interface_mode : t_wishbone_interface_mode; g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity; g_address_granularity : t_wishbone_address_granularity);
g_channels_config : t_softpll_channel_config_array := c_softpll_default_channel_config);
port ( port (
clk_sys_i : in std_logic; clk_sys_i : in std_logic;
rst_n_i : in std_logic; rst_n_i : in std_logic;
...@@ -261,7 +263,9 @@ package wrcore_pkg is ...@@ -261,7 +263,9 @@ package wrcore_pkg is
clk_fb_i : in std_logic_vector(g_num_outputs-1 downto 0); clk_fb_i : in std_logic_vector(g_num_outputs-1 downto 0);
clk_dmtd_i : in std_logic; clk_dmtd_i : in std_logic;
clk_ext_i : in std_logic; clk_ext_i : in std_logic;
sync_p_i : in std_logic; clk_ext_mul_i : in std_logic;
pps_csync_p1_i : in std_logic;
pps_ext_a_i : in std_logic;
dac_dmtd_data_o : out std_logic_vector(15 downto 0); dac_dmtd_data_o : out std_logic_vector(15 downto 0);
dac_dmtd_load_o : out std_logic; dac_dmtd_load_o : out std_logic;
dac_out_data_o : out std_logic_vector(15 downto 0); dac_out_data_o : out std_logic_vector(15 downto 0);
...@@ -269,12 +273,13 @@ package wrcore_pkg is ...@@ -269,12 +273,13 @@ package wrcore_pkg is
dac_out_load_o : out std_logic; dac_out_load_o : out std_logic;
out_enable_i : in std_logic_vector(g_num_outputs-1 downto 0); out_enable_i : in std_logic_vector(g_num_outputs-1 downto 0);
out_locked_o : out std_logic_vector(g_num_outputs-1 downto 0); out_locked_o : out std_logic_vector(g_num_outputs-1 downto 0);
out_status_o : out std_logic_vector(4*g_num_outputs-1 downto 0);
slave_i : in t_wishbone_slave_in; slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out; slave_o : out t_wishbone_slave_out;
debug_o : out std_logic_vector(3 downto 0); debug_o : out std_logic_vector(3 downto 0);
dbg_fifo_irq_o : out std_logic); dbg_fifo_irq_o : out std_logic);
end component; end component;
constant cc_unused_master_in : t_wishbone_master_in := constant cc_unused_master_in : t_wishbone_master_in :=
('1', '0', '0', '0', '0', cc_dummy_data); ('1', '0', '0', '0', '0', cc_dummy_data);
...@@ -295,14 +300,15 @@ package wrcore_pkg is ...@@ -295,14 +300,15 @@ package wrcore_pkg is
g_interface_mode : t_wishbone_interface_mode := PIPELINED; g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := BYTE; g_address_granularity : t_wishbone_address_granularity := BYTE;
g_aux_sdb : t_sdb_device := c_wrc_periph3_sdb; g_aux_sdb : t_sdb_device := c_wrc_periph3_sdb;
g_softpll_channels_config : t_softpll_channel_config_array := c_softpll_default_channel_config; g_softpll_enable_debugger : boolean := false;
g_softpll_enable_debugger : boolean := false g_vuart_fifo_size : integer := 1024
); );
port( port(
clk_sys_i : in std_logic; clk_sys_i : in std_logic;
clk_dmtd_i : in std_logic := '0'; clk_dmtd_i : in std_logic := '0';
clk_ref_i : in std_logic; clk_ref_i : in std_logic;
clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0'); clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
clk_ext_mul_i: in std_logic := '0';
clk_ext_i : in std_logic := '0'; clk_ext_i : in std_logic := '0';
pps_ext_i : in std_logic := '0'; pps_ext_i : in std_logic := '0';
rst_n_i : in std_logic; rst_n_i : in std_logic;
...@@ -394,8 +400,8 @@ package wrcore_pkg is ...@@ -394,8 +400,8 @@ package wrcore_pkg is
g_interface_mode : t_wishbone_interface_mode := PIPELINED; g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := WORD; g_address_granularity : t_wishbone_address_granularity := WORD;
g_aux_sdb : t_sdb_device := c_wrc_periph3_sdb; g_aux_sdb : t_sdb_device := c_wrc_periph3_sdb;
g_softpll_channels_config : t_softpll_channel_config_array := c_softpll_default_channel_config; g_softpll_enable_debugger : boolean := false;
g_softpll_enable_debugger : boolean := false g_vuart_fifo_size : integer := 1024
); );
port( port(
--------------------------------------------------------------------------- ---------------------------------------------------------------------------
...@@ -417,6 +423,8 @@ package wrcore_pkg is ...@@ -417,6 +423,8 @@ package wrcore_pkg is
-- External 10 MHz reference (cesium, GPSDO, etc.), used in Grandmaster mode -- External 10 MHz reference (cesium, GPSDO, etc.), used in Grandmaster mode
clk_ext_i : in std_logic := '0'; clk_ext_i : in std_logic := '0';
clk_ext_mul_i : in std_logic;
-- External PPS input (cesium, GPSDO, etc.), used in Grandmaster mode -- External PPS input (cesium, GPSDO, etc.), used in Grandmaster mode
pps_ext_i : in std_logic := '0'; pps_ext_i : in std_logic := '0';
......
modules/wrc_core/xwr_core.vhd
View file @ fe8ab3dd
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
-- Author : Grzegorz Daniluk -- Author : Grzegorz Daniluk
-- Company : Elproma -- Company : Elproma
-- Created : 2011-02-02 -- Created : 2011-02-02
-- Last update: 2013-02-08 -- Last update: 2014-07-15
-- Platform : FPGA-generics -- Platform : FPGA-generics
-- Standard : VHDL -- Standard : VHDL
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -78,8 +78,8 @@ entity xwr_core is ...@@ -78,8 +78,8 @@ entity xwr_core is
g_interface_mode : t_wishbone_interface_mode := PIPELINED; g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := WORD; g_address_granularity : t_wishbone_address_granularity := WORD;
g_aux_sdb : t_sdb_device := c_wrc_periph3_sdb; g_aux_sdb : t_sdb_device := c_wrc_periph3_sdb;
g_softpll_channels_config : t_softpll_channel_config_array := c_softpll_default_channel_config; g_softpll_enable_debugger : boolean := false;
g_softpll_enable_debugger : boolean := false g_vuart_fifo_size : integer := 1024
); );
port( port(
--------------------------------------------------------------------------- ---------------------------------------------------------------------------
...@@ -101,6 +101,8 @@ entity xwr_core is ...@@ -101,6 +101,8 @@ entity xwr_core is
-- External 10 MHz reference (cesium, GPSDO, etc.), used in Grandmaster mode -- External 10 MHz reference (cesium, GPSDO, etc.), used in Grandmaster mode
clk_ext_i : in std_logic := '0'; clk_ext_i : in std_logic := '0';
clk_ext_mul_i : in std_logic := '0';
-- External PPS input (cesium, GPSDO, etc.), used in Grandmaster mode -- External PPS input (cesium, GPSDO, etc.), used in Grandmaster mode
pps_ext_i : in std_logic := '0'; pps_ext_i : in std_logic := '0';
...@@ -228,16 +230,17 @@ begin ...@@ -228,16 +230,17 @@ begin
g_interface_mode => g_interface_mode, g_interface_mode => g_interface_mode,
g_address_granularity => g_address_granularity, g_address_granularity => g_address_granularity,
g_aux_sdb => g_aux_sdb, g_aux_sdb => g_aux_sdb,
g_softpll_channels_config => g_softpll_channels_config, g_softpll_enable_debugger => g_softpll_enable_debugger,
g_softpll_enable_debugger => g_softpll_enable_debugger) g_vuart_fifo_size => g_vuart_fifo_size)
port map( port map(
clk_sys_i => clk_sys_i, clk_sys_i => clk_sys_i,
clk_dmtd_i => clk_dmtd_i, clk_dmtd_i => clk_dmtd_i,
clk_ref_i => clk_ref_i, clk_ref_i => clk_ref_i,
clk_aux_i => clk_aux_i, clk_aux_i => clk_aux_i,
clk_ext_i => clk_ext_i, clk_ext_i => clk_ext_i,
pps_ext_i => pps_ext_i, clk_ext_mul_i => clk_ext_mul_i,
rst_n_i => rst_n_i, pps_ext_i => pps_ext_i,
rst_n_i => rst_n_i,
dac_hpll_load_p1_o => dac_hpll_load_p1_o, dac_hpll_load_p1_o => dac_hpll_load_p1_o,
dac_hpll_data_o => dac_hpll_data_o, dac_hpll_data_o => dac_hpll_data_o,
......
platform/xilinx/Manifest.py
View file @ fe8ab3dd
files = [ "wr_xilinx_pkg.vhd" ] files = [ "wr_xilinx_pkg.vhd", "ext_pll_10_to_125m.vhd" ]
modules = {"local" : ["wr_gtp_phy"]} modules = {"local" : ["wr_gtp_phy"]}
\ No newline at end of file
platform/xilinx/ext_pll_10_to_125m.vhd 0 → 100644
View file @ fe8ab3dd
-- file: ext_pll_10_to_125m.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1___125.000______0.000______50.0_____1014.602____150.000
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary__________10.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity ext_pll_10_to_125m is
port
(-- Clock in ports
clk_ext_i : in std_logic;
-- Clock out ports
clk_ext_mul_o : out std_logic;
-- Status and control signals
rst_a_i : in std_logic
);
end ext_pll_10_to_125m;
architecture xilinx of ext_pll_10_to_125m is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "ext_pll_10_to_125m,clk_wiz_v3_6,{component_name=ext_pll_10_to_125m,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=100.0,clkin2_period=100.0,use_power_down=false,use_reset=true,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkfx : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 2,
CLKFX_MULTIPLY => 25,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 100.0,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clk_ext_i,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => open,
CLKDV => open,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => rst_a_i,
-- Unused pin, tie low
DSSEN => '0');
-- Output buffering
-------------------------------------
-- no phase alignment active, connect to ground
clkfb <= '0';
clkout1_buf : BUFG
port map
(O => clk_ext_mul_o,
I => clkfx);
end xilinx;
sim/if_wb_master.svh
View file @ fe8ab3dd
...@@ -406,7 +406,7 @@ endclass // CIWBMasterAccessor ...@@ -406,7 +406,7 @@ endclass // CIWBMasterAccessor
if(request_queue.size() > 0) if(request_queue.size() > 0)
begin begin
wb_cycle_t c; wb_cycle_t c;
wb_cycle_result_t res; wb_cycle_result_t res;
...@@ -416,6 +416,7 @@ endclass // CIWBMasterAccessor ...@@ -416,6 +416,7 @@ endclass // CIWBMasterAccessor
case(c.ctype) case(c.ctype)
PIPELINED: PIPELINED:
begin begin
pipelined_cycle(c.data, c.rw, c.data.size(), res); pipelined_cycle(c.data, c.rw, c.data.size(), res);
c.result =res; c.result =res;
end end
......
sim/softpll_regs_ng.vh
View file @ fe8ab3dd
`define ADDR_SPLL_CSR 7'h0 `define ADDR_SPLL_CSR 8'h0
`define SPLL_CSR_PER_SEL_OFFSET 0 `define SPLL_CSR_UNUSED0_OFFSET 8
`define SPLL_CSR_PER_SEL 32'h0000003f `define SPLL_CSR_UNUSED0 32'h00003f00
`define SPLL_CSR_N_REF_OFFSET 8 `define SPLL_CSR_N_REF_OFFSET 16
`define SPLL_CSR_N_REF 32'h00003f00 `define SPLL_CSR_N_REF 32'h003f0000
`define SPLL_CSR_N_OUT_OFFSET 16 `define SPLL_CSR_N_OUT_OFFSET 24
`define SPLL_CSR_N_OUT 32'h00070000 `define SPLL_CSR_N_OUT 32'h07000000
`define SPLL_CSR_PER_EN_OFFSET 19 `define SPLL_CSR_DBG_SUPPORTED_OFFSET 27
`define SPLL_CSR_PER_EN 32'h00080000 `define SPLL_CSR_DBG_SUPPORTED 32'h08000000
`define ADDR_SPLL_ECCR 7'h4 `define ADDR_SPLL_ECCR 8'h4
`define SPLL_ECCR_EXT_EN_OFFSET 0 `define SPLL_ECCR_EXT_EN_OFFSET 0
`define SPLL_ECCR_EXT_EN 32'h00000001 `define SPLL_ECCR_EXT_EN 32'h00000001
`define SPLL_ECCR_EXT_SUPPORTED_OFFSET 1 `define SPLL_ECCR_EXT_SUPPORTED_OFFSET 1
`define SPLL_ECCR_EXT_SUPPORTED 32'h00000002 `define SPLL_ECCR_EXT_SUPPORTED 32'h00000002
`define SPLL_ECCR_ALIGN_EN_OFFSET 2 `define SPLL_ECCR_EXT_REF_PRESENT_OFFSET 2
`define SPLL_ECCR_ALIGN_EN 32'h00000004 `define SPLL_ECCR_EXT_REF_PRESENT 32'h00000004
`define SPLL_ECCR_ALIGN_DONE_OFFSET 3 `define ADDR_SPLL_AL_CR 8'h8
`define SPLL_ECCR_ALIGN_DONE 32'h00000008 `define SPLL_AL_CR_VALID_OFFSET 0
`define SPLL_ECCR_EXT_REF_PRESENT_OFFSET 4 `define SPLL_AL_CR_VALID 32'h000001ff
`define SPLL_ECCR_EXT_REF_PRESENT 32'h00000010 `define SPLL_AL_CR_REQUIRED_OFFSET 9
`define ADDR_SPLL_DCCR 7'h8 `define SPLL_AL_CR_REQUIRED 32'h0003fe00
`define SPLL_DCCR_GATE_DIV_OFFSET 0 `define ADDR_SPLL_AL_CREF 8'hc
`define SPLL_DCCR_GATE_DIV 32'h0000003f `define ADDR_SPLL_AL_CIN 8'h10
`define ADDR_SPLL_RCGER 7'hc `define ADDR_SPLL_F_DMTD 8'h14
`define SPLL_RCGER_GATE_SEL_OFFSET 0 `define SPLL_F_DMTD_FREQ_OFFSET 0
`define SPLL_RCGER_GATE_SEL 32'hffffffff `define SPLL_F_DMTD_FREQ 32'h0fffffff
`define ADDR_SPLL_OCCR 7'h10 `define SPLL_F_DMTD_VALID_OFFSET 28
`define SPLL_OCCR_OUT_EN_OFFSET 0 `define SPLL_F_DMTD_VALID 32'h10000000
`define SPLL_OCCR_OUT_EN 32'h000000ff `define ADDR_SPLL_F_REF 8'h18
`define SPLL_OCCR_OUT_LOCK_OFFSET 8 `define SPLL_F_REF_FREQ_OFFSET 0
`define SPLL_OCCR_OUT_LOCK 32'h0000ff00 `define SPLL_F_REF_FREQ 32'h0fffffff
`define ADDR_SPLL_RCER 7'h14 `define SPLL_F_REF_VALID_OFFSET 28
`define ADDR_SPLL_OCER 7'h18 `define SPLL_F_REF_VALID 32'h10000000
`define ADDR_SPLL_PER_HPLL 7'h1c `define ADDR_SPLL_F_EXT 8'h1c
`define SPLL_PER_HPLL_ERROR_OFFSET 0 `define SPLL_F_EXT_FREQ_OFFSET 0
`define SPLL_PER_HPLL_ERROR 32'h0000ffff `define SPLL_F_EXT_FREQ 32'h0fffffff
`define SPLL_PER_HPLL_VALID_OFFSET 16 `define SPLL_F_EXT_VALID_OFFSET 28
`define SPLL_PER_HPLL_VALID 32'h00010000 `define SPLL_F_EXT_VALID 32'h10000000
`define ADDR_SPLL_DAC_HPLL 7'h20 `define ADDR_SPLL_OCCR 8'h20
`define ADDR_SPLL_DAC_MAIN 7'h24 `define SPLL_OCCR_OUT_EN_OFFSET 8
`define SPLL_OCCR_OUT_EN 32'h0000ff00
`define SPLL_OCCR_OUT_LOCK_OFFSET 16
`define SPLL_OCCR_OUT_LOCK 32'h00ff0000
`define ADDR_SPLL_RCER 8'h24
`define ADDR_SPLL_OCER 8'h28
`define ADDR_SPLL_DAC_HPLL 8'h40
`define ADDR_SPLL_DAC_MAIN 8'h44
`define SPLL_DAC_MAIN_VALUE_OFFSET 0 `define SPLL_DAC_MAIN_VALUE_OFFSET 0
`define SPLL_DAC_MAIN_VALUE 32'h0000ffff `define SPLL_DAC_MAIN_VALUE 32'h0000ffff
`define SPLL_DAC_MAIN_DAC_SEL_OFFSET 16 `define SPLL_DAC_MAIN_DAC_SEL_OFFSET 16
`define SPLL_DAC_MAIN_DAC_SEL 32'h000f0000 `define SPLL_DAC_MAIN_DAC_SEL 32'h000f0000
`define ADDR_SPLL_DEGLITCH_THR 7'h28 `define ADDR_SPLL_DEGLITCH_THR 8'h48
`define ADDR_SPLL_DFR_SPLL 7'h2c `define ADDR_SPLL_DFR_SPLL 8'h4c
`define SPLL_DFR_SPLL_VALUE_OFFSET 0 `define SPLL_DFR_SPLL_VALUE_OFFSET 0
`define SPLL_DFR_SPLL_VALUE 32'h7fffffff `define SPLL_DFR_SPLL_VALUE 32'h7fffffff
`define SPLL_DFR_SPLL_EOS_OFFSET 31 `define SPLL_DFR_SPLL_EOS_OFFSET 31
`define SPLL_DFR_SPLL_EOS 32'h80000000 `define SPLL_DFR_SPLL_EOS 32'h80000000
`define ADDR_SPLL_CRR_IN 7'h30 `define ADDR_SPLL_EIC_IDR 8'h60
`define ADDR_SPLL_CRR_OUT 7'h34
`define ADDR_SPLL_EIC_IDR 7'h40
`define SPLL_EIC_IDR_TAG_OFFSET 0 `define SPLL_EIC_IDR_TAG_OFFSET 0
`define SPLL_EIC_IDR_TAG 32'h00000001 `define SPLL_EIC_IDR_TAG 32'h00000001
`define ADDR_SPLL_EIC_IER 7'h44 `define ADDR_SPLL_EIC_IER 8'h64
`define SPLL_EIC_IER_TAG_OFFSET 0 `define SPLL_EIC_IER_TAG_OFFSET 0
`define SPLL_EIC_IER_TAG 32'h00000001 `define SPLL_EIC_IER_TAG 32'h00000001
`define ADDR_SPLL_EIC_IMR 7'h48 `define ADDR_SPLL_EIC_IMR 8'h68
`define SPLL_EIC_IMR_TAG_OFFSET 0 `define SPLL_EIC_IMR_TAG_OFFSET 0
`define SPLL_EIC_IMR_TAG 32'h00000001 `define SPLL_EIC_IMR_TAG 32'h00000001
`define ADDR_SPLL_EIC_ISR 7'h4c `define ADDR_SPLL_EIC_ISR 8'h6c
`define SPLL_EIC_ISR_TAG_OFFSET 0 `define SPLL_EIC_ISR_TAG_OFFSET 0
`define SPLL_EIC_ISR_TAG 32'h00000001 `define SPLL_EIC_ISR_TAG 32'h00000001
`define ADDR_SPLL_DFR_HOST_R0 7'h50 `define ADDR_SPLL_DFR_HOST_R0 8'h70
`define SPLL_DFR_HOST_R0_VALUE_OFFSET 0 `define SPLL_DFR_HOST_R0_VALUE_OFFSET 0
`define SPLL_DFR_HOST_R0_VALUE 32'hffffffff `define SPLL_DFR_HOST_R0_VALUE 32'hffffffff
`define ADDR_SPLL_DFR_HOST_R1 7'h54 `define ADDR_SPLL_DFR_HOST_R1 8'h74
`define SPLL_DFR_HOST_R1_SEQ_ID_OFFSET 0 `define SPLL_DFR_HOST_R1_SEQ_ID_OFFSET 0
`define SPLL_DFR_HOST_R1_SEQ_ID 32'h0000ffff `define SPLL_DFR_HOST_R1_SEQ_ID 32'h0000ffff
`define ADDR_SPLL_DFR_HOST_CSR 7'h58 `define ADDR_SPLL_DFR_HOST_CSR 8'h78
`define SPLL_DFR_HOST_CSR_FULL_OFFSET 16 `define SPLL_DFR_HOST_CSR_FULL_OFFSET 16
`define SPLL_DFR_HOST_CSR_FULL 32'h00010000 `define SPLL_DFR_HOST_CSR_FULL 32'h00010000
`define SPLL_DFR_HOST_CSR_EMPTY_OFFSET 17 `define SPLL_DFR_HOST_CSR_EMPTY_OFFSET 17
`define SPLL_DFR_HOST_CSR_EMPTY 32'h00020000 `define SPLL_DFR_HOST_CSR_EMPTY 32'h00020000
`define SPLL_DFR_HOST_CSR_USEDW_OFFSET 0 `define SPLL_DFR_HOST_CSR_USEDW_OFFSET 0
`define SPLL_DFR_HOST_CSR_USEDW 32'h00001fff `define SPLL_DFR_HOST_CSR_USEDW 32'h00001fff
`define ADDR_SPLL_TRR_R0 7'h5c `define ADDR_SPLL_TRR_R0 8'h7c
`define SPLL_TRR_R0_VALUE_OFFSET 0 `define SPLL_TRR_R0_VALUE_OFFSET 0
`define SPLL_TRR_R0_VALUE 32'h00ffffff `define SPLL_TRR_R0_VALUE 32'h00ffffff
`define SPLL_TRR_R0_CHAN_ID_OFFSET 24 `define SPLL_TRR_R0_CHAN_ID_OFFSET 24
`define SPLL_TRR_R0_CHAN_ID 32'h7f000000 `define SPLL_TRR_R0_CHAN_ID 32'h7f000000
`define SPLL_TRR_R0_DISC_OFFSET 31 `define SPLL_TRR_R0_DISC_OFFSET 31
`define SPLL_TRR_R0_DISC 32'h80000000 `define SPLL_TRR_R0_DISC 32'h80000000
`define ADDR_SPLL_TRR_CSR 7'h60 `define ADDR_SPLL_TRR_CSR 8'h80
`define SPLL_TRR_CSR_EMPTY_OFFSET 17 `define SPLL_TRR_CSR_EMPTY_OFFSET 17
`define SPLL_TRR_CSR_EMPTY 32'h00020000 `define SPLL_TRR_CSR_EMPTY 32'h00020000
syn/spec_1_1/wr_core_demo/Manifest.py
View file @ fe8ab3dd
...@@ -3,6 +3,7 @@ action = "synthesis" ...@@ -3,6 +3,7 @@ action = "synthesis"
fetchto = "../../../ip_cores" fetchto = "../../../ip_cores"
#top_module = "spec_top"
syn_device = "xc6slx45t" syn_device = "xc6slx45t"
syn_grade = "-3" syn_grade = "-3"
syn_package = "fgg484" syn_package = "fgg484"
...@@ -11,8 +12,8 @@ syn_project = "spec_top_wrc.xise" ...@@ -11,8 +12,8 @@ syn_project = "spec_top_wrc.xise"
modules = { "local" : modules = { "local" :
[ "../../../top/spec_1_1/wr_core_demo", [ "../../../top/spec_1_1/wr_core_demo",
"../../../platform", "../../../platform" ],
"../../../ip_cores/general-cores", "git" :
"../../../ip_cores/etherbone-core", [ "git://ohwr.org/hdl-core-lib/general-cores.git",
"../../../ip_cores/gn4124-core"] "git://ohwr.org/hdl-core-lib/gn4124-core.git",
} "git://ohwr.org/hdl-core-lib/etherbone-core.git" ] };
testbench/top_level/Manifest.py
View file @ fe8ab3dd
...@@ -5,5 +5,5 @@ vlog_opt="+incdir+../../sim +incdir+gn4124_bfm" ...@@ -5,5 +5,5 @@ vlog_opt="+incdir+../../sim +incdir+gn4124_bfm"
files = [ "main.sv" ] files = [ "main.sv" ]
modules = { "local" : [ "../..", "../../top/spec_1_1/wr_core_demo", "gn4124_bfm"] } modules = { "local" : [ "../..", "../../top/spec_1_1/wr_core_demo", "../../../general-cores", "../../../gn4124-core", "../../../etherbone-core", "gn4124_bfm"] }
testbench/top_level/NullFile
View file @ fe8ab3dd
-- GN412X_BFMBAR set to: BAR=0, BASE=0xFF00000000000000, MASK=0xF8000000, VC=0, TC=0x7, S=0 -- GN412X_BFMBAR set to: BAR=0, BASE=0xFF00000000000000, MASK=0xF8000000, VC=0, TC=0x7, S=0
-- GN412X_BFMBFM BAR set to: BAR=0, BASE=0x0000000040000000, MASK=0xE0000000 -- GN412X_BFMBFM BAR set to: BAR=0, BASE=0x0000000040000000, MASK=0xE0000000
-- GN412X_BFMBFM BAR set to: BAR=1, BASE=0x0000000020000000, MASK=0xE0000000 -- GN412X_BFMBFM BAR set to: BAR=1, BASE=0x0000000020000000, MASK=0xE0000000
--<<<< P2L Header: (P2L Target Write), FBE=0xF, LBE=0xF, V=0, LENGTH=0x001--<<<< Address: 0x00000000000A021C @ 2217 ns
testbench/top_level/main.sv
View file @ fe8ab3dd
...@@ -7,7 +7,10 @@ const uint64_t BASE_WRPC = 'h0080000; ...@@ -7,7 +7,10 @@ const uint64_t BASE_WRPC = 'h0080000;
module main; module main;
reg clk_125m_pllref = 0; reg clk_125m_pllref = 0;
reg clk_20m_vcxo = 0; reg clk_20m_vcxo = 0;
reg clk_ext = 0;
always #50ns clk_ext <= ~clk_ext;
always #4ns clk_125m_pllref <= ~clk_125m_pllref; always #4ns clk_125m_pllref <= ~clk_125m_pllref;
always #20ns clk_20m_vcxo <= ~clk_20m_vcxo; always #20ns clk_20m_vcxo <= ~clk_20m_vcxo;
...@@ -44,7 +47,7 @@ module main; ...@@ -44,7 +47,7 @@ module main;
//$display("dupa1"); //$display("dupa1");
//acc.write('ha0400, 'h0deadbee); //acc.write('ha0400, 'h0deadbee);
//$display("dupa2"); //$display("dupa2");
acc.write('ha021c, 'hfafa); //acc.write('ha021c, 'hfafa);
$display("dupa3"); $display("dupa3");
......
testbench/top_level/wave.do
View file @ fe8ab3dd
onerror {resume} onerror {resume}
quietly WaveActivateNextPane {} 0 quietly WaveActivateNextPane {} 0
#add wave -noupdate /main/DUT/U_VIC/g_interface_mode add wave -noupdate /main/DUT/clk_20m_vcxo_i
#add wave -noupdate /main/DUT/U_VIC/g_address_granularity add wave -noupdate /main/DUT/clk_125m_pllref_p_i
#add wave -noupdate /main/DUT/U_VIC/g_num_interrupts add wave -noupdate /main/DUT/clk_125m_pllref_n_i
#add wave -noupdate /main/DUT/U_VIC/clk_sys_i add wave -noupdate /main/DUT/fpga_pll_ref_clk_101_p_i
#add wave -noupdate /main/DUT/U_VIC/rst_n_i add wave -noupdate /main/DUT/fpga_pll_ref_clk_101_n_i
#add wave -noupdate /main/DUT/U_VIC/slave_i add wave -noupdate /main/DUT/L_CLKp
#add wave -noupdate /main/DUT/U_VIC/slave_o add wave -noupdate /main/DUT/L_CLKn
#add wave -noupdate /main/DUT/U_VIC/irqs_i
#add wave -noupdate /main/DUT/U_VIC/irq_master_o
add wave -noupdate /main/clk_125m_pllref
add wave -noupdate /main/clk_20m_vcxo
add wave -noupdate /main/DUT/L_RST_N add wave -noupdate /main/DUT/L_RST_N
add wave -noupdate /main/DUT/GPIO
add wave -noupdate /main/I_Gennum/ready add wave -noupdate /main/DUT/P2L_RDY
add wave -noupdate /main/I_Gennum/p2l_data add wave -noupdate /main/DUT/P2L_CLKn
add wave -noupdate /main/I_Gennum/p2l_valid add wave -noupdate /main/DUT/P2L_CLKp
add wave -noupdate /main/DUT/P2L_DATA
add wave -noupdate /main/DUT/cmp_gn4124_core/p2l_data_i add wave -noupdate /main/DUT/P2L_DFRAME
add wave -noupdate /main/DUT/cmp_gn4124_core/p2l_valid_i add wave -noupdate /main/DUT/P2L_VALID
add wave -noupdate /main/DUT/cmp_gn4124_core/csr_adr_o add wave -noupdate /main/DUT/P_WR_REQ
add wave -noupdate /main/DUT/cmp_gn4124_core/csr_dat_o add wave -noupdate /main/DUT/P_WR_RDY
add wave -noupdate /main/DUT/cmp_gn4124_core/dma_adr_o add wave -noupdate /main/DUT/RX_ERROR
add wave -noupdate /main/DUT/cmp_gn4124_core/dma_dat_o add wave -noupdate /main/DUT/L2P_DATA
add wave -noupdate /main/DUT/L2P_DFRAME
add wave -noupdate /main/DUT/dac_hpll_data add wave -noupdate /main/DUT/L2P_VALID
add wave -noupdate /main/DUT/dac_hpll_load_p1 add wave -noupdate /main/DUT/L2P_CLKn
add wave -noupdate /main/DUT/dac_cs1_n_o add wave -noupdate /main/DUT/L2P_CLKp
add wave -noupdate /main/DUT/dac_cs2_n_o add wave -noupdate /main/DUT/L2P_EDB
add wave -noupdate /main/DUT/dac_clr_n_o add wave -noupdate /main/DUT/L2P_RDY
add wave -noupdate /main/DUT/L_WR_RDY
add wave -noupdate /main/DUT/P_RD_D_RDY
add wave -noupdate /main/DUT/TX_ERROR
add wave -noupdate /main/DUT/VC_RDY
add wave -noupdate /main/DUT/LED_RED
add wave -noupdate /main/DUT/LED_GREEN
add wave -noupdate /main/DUT/dac_sclk_o add wave -noupdate /main/DUT/dac_sclk_o
add wave -noupdate /main/DUT/dac_din_o add wave -noupdate /main/DUT/dac_din_o
add wave -noupdate /main/DUT/dac_clr_n_o
add wave -noupdate /main/DUT/wrc_slave_i.cyc add wave -noupdate /main/DUT/dac_cs1_n_o
add wave -noupdate /main/DUT/wrc_slave_i.stb add wave -noupdate /main/DUT/dac_cs2_n_o
add wave -noupdate /main/DUT/wrc_slave_i.adr add wave -noupdate /main/DUT/fpga_scl_b
add wave -noupdate /main/DUT/wrc_slave_i.dat add wave -noupdate /main/DUT/fpga_sda_b
add wave -noupdate /main/DUT/button1_i
add wave -noupdate /main/DUT/button2_i
add wave -noupdate /main/DUT/thermo_id
add wave -noupdate /main/DUT/sfp_txp_o
add wave -noupdate /main/DUT/sfp_txn_o
add wave -noupdate /main/DUT/sfp_rxp_i
add wave -noupdate /main/DUT/sfp_rxn_i
add wave -noupdate /main/DUT/sfp_mod_def0_b
add wave -noupdate /main/DUT/sfp_mod_def1_b
add wave -noupdate /main/DUT/sfp_mod_def2_b
add wave -noupdate /main/DUT/sfp_rate_select_b
add wave -noupdate /main/DUT/sfp_tx_fault_i
add wave -noupdate /main/DUT/sfp_tx_disable_o
add wave -noupdate /main/DUT/sfp_los_i
add wave -noupdate /main/DUT/dio_clk_p_i
add wave -noupdate /main/DUT/dio_clk_n_i
add wave -noupdate /main/DUT/dio_n_i
add wave -noupdate /main/DUT/dio_p_i
add wave -noupdate /main/DUT/dio_n_o
add wave -noupdate /main/DUT/dio_p_o
add wave -noupdate /main/DUT/dio_oe_n_o
add wave -noupdate /main/DUT/dio_term_en_o
add wave -noupdate /main/DUT/dio_onewire_b
add wave -noupdate /main/DUT/dio_sdn_n_o
add wave -noupdate /main/DUT/dio_sdn_ck_n_o
add wave -noupdate /main/DUT/dio_led_top_o
add wave -noupdate /main/DUT/dio_led_bot_o
add wave -noupdate /main/DUT/uart_rxd_i
add wave -noupdate /main/DUT/uart_txd_o
add wave -noupdate /main/DUT/l_clk
add wave -noupdate /main/DUT/gtp_dedicated_clk
add wave -noupdate /main/DUT/p2l_pll_locked
add wave -noupdate /main/DUT/rst_a
add wave -noupdate /main/DUT/rst
add wave -noupdate /main/DUT/ram_we
add wave -noupdate /main/DUT/ddr_dma_adr
add wave -noupdate /main/DUT/irq_to_gn4124
add wave -noupdate /main/DUT/spi_slave_select
add wave -noupdate /main/DUT/pllout_clk_sys
add wave -noupdate /main/DUT/pllout_clk_dmtd
add wave -noupdate /main/DUT/pllout_clk_fb_pllref
add wave -noupdate /main/DUT/pllout_clk_fb_dmtd
add wave -noupdate /main/DUT/clk_20m_vcxo_buf
add wave -noupdate /main/DUT/clk_125m_pllref
add wave -noupdate /main/DUT/clk_sys
add wave -noupdate /main/DUT/clk_dmtd
add wave -noupdate /main/DUT/dac_rst_n
add wave -noupdate /main/DUT/led_divider
add wave -noupdate /main/DUT/wrc_scl_o
add wave -noupdate /main/DUT/wrc_scl_i
add wave -noupdate /main/DUT/wrc_sda_o
add wave -noupdate /main/DUT/wrc_sda_i
add wave -noupdate /main/DUT/sfp_scl_o
add wave -noupdate /main/DUT/sfp_scl_i
add wave -noupdate /main/DUT/sfp_sda_o
add wave -noupdate /main/DUT/sfp_sda_i
add wave -noupdate /main/DUT/dio
add wave -noupdate /main/DUT/dac_hpll_load_p1
add wave -noupdate /main/DUT/dac_dpll_load_p1
add wave -noupdate /main/DUT/dac_hpll_data
add wave -noupdate /main/DUT/dac_dpll_data
add wave -noupdate /main/DUT/pps
add wave -noupdate /main/DUT/pps_led
add wave -noupdate /main/DUT/phy_tx_data
add wave -noupdate /main/DUT/phy_tx_k
add wave -noupdate /main/DUT/phy_tx_disparity
add wave -noupdate /main/DUT/phy_tx_enc_err
add wave -noupdate /main/DUT/phy_rx_data
add wave -noupdate /main/DUT/phy_rx_rbclk
add wave -noupdate /main/DUT/phy_rx_k
add wave -noupdate /main/DUT/phy_rx_enc_err
add wave -noupdate /main/DUT/phy_rx_bitslide
add wave -noupdate /main/DUT/phy_rst
add wave -noupdate /main/DUT/phy_loopen
add wave -noupdate /main/DUT/dio_in
add wave -noupdate /main/DUT/dio_out
add wave -noupdate /main/DUT/dio_clk
add wave -noupdate /main/DUT/local_reset_n
add wave -noupdate /main/DUT/button1_synced
add wave -noupdate /main/DUT/genum_wb_out
add wave -noupdate /main/DUT/genum_wb_in
add wave -noupdate /main/DUT/genum_csr_ack_i
add wave -noupdate /main/DUT/wrc_slave_i
add wave -noupdate /main/DUT/wrc_slave_o
add wave -noupdate /main/DUT/owr_en
add wave -noupdate /main/DUT/owr_i
add wave -noupdate /main/DUT/wb_adr
add wave -noupdate /main/DUT/etherbone_rst_n
add wave -noupdate /main/DUT/etherbone_src_out
add wave -noupdate /main/DUT/etherbone_src_in
add wave -noupdate /main/DUT/etherbone_snk_out
add wave -noupdate /main/DUT/etherbone_snk_in
add wave -noupdate /main/DUT/etherbone_wb_out
add wave -noupdate /main/DUT/etherbone_wb_in
add wave -noupdate /main/DUT/etherbone_cfg_in
add wave -noupdate /main/DUT/etherbone_cfg_out
add wave -noupdate /main/DUT/local_reset
add wave -noupdate /main/DUT/ext_pll_reset
add wave -noupdate /main/DUT/clk_ext
add wave -noupdate /main/DUT/clk_ext_mul
TreeUpdate [SetDefaultTree] TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {2367015 ps} 0} WaveRestoreCursors {{Cursor 1} {2367015 ps} 0}
configure wave -namecolwidth 150 configure wave -namecolwidth 150
...@@ -55,4 +154,4 @@ configure wave -griddelta 40 ...@@ -55,4 +154,4 @@ configure wave -griddelta 40
configure wave -timeline 0 configure wave -timeline 0
configure wave -timelineunits ns configure wave -timelineunits ns
update update
WaveRestoreZoom {0 ps} {26250 ns} WaveRestoreZoom {0 ps} {31500 ns}
top/spec_1_1/wr_core_demo/spec_top.vhd
View file @ fe8ab3dd
...@@ -240,6 +240,13 @@ architecture rtl of spec_top is ...@@ -240,6 +240,13 @@ architecture rtl of spec_top is
rst_n_o : out std_logic); rst_n_o : out std_logic);
end component; end component;
component ext_pll_10_to_125m
port (
clk_ext_i : in std_logic;
clk_ext_mul_o : out std_logic;
rst_a_i : in std_logic);
end component;
--component chipscope_ila --component chipscope_ila
-- port ( -- port (
-- CONTROL : inout std_logic_vector(35 downto 0); -- CONTROL : inout std_logic_vector(35 downto 0);
...@@ -376,9 +383,30 @@ architecture rtl of spec_top is ...@@ -376,9 +383,30 @@ architecture rtl of spec_top is
signal etherbone_wb_in : t_wishbone_master_in; signal etherbone_wb_in : t_wishbone_master_in;
signal etherbone_cfg_in : t_wishbone_slave_in; signal etherbone_cfg_in : t_wishbone_slave_in;
signal etherbone_cfg_out : t_wishbone_slave_out; signal etherbone_cfg_out : t_wishbone_slave_out;
signal local_reset, ext_pll_reset : std_logic;
signal clk_ext, clk_ext_mul : std_logic;
signal clk_ref_div2 : std_logic;
begin begin
local_reset <= not local_reset_n;
U_Ext_PLL : ext_pll_10_to_125m
port map (
clk_ext_i => clk_ext,
clk_ext_mul_o => clk_ext_mul,
rst_a_i => ext_pll_reset);
U_Extend_EXT_Reset : gc_extend_pulse
generic map (
g_width => 1000)
port map (
clk_i => clk_sys,
rst_n_i => local_reset_n,
pulse_i => local_reset,
extended_o => ext_pll_reset);
cmp_sys_clk_pll : PLL_BASE cmp_sys_clk_pll : PLL_BASE
generic map ( generic map (
BANDWIDTH => "OPTIMIZED", BANDWIDTH => "OPTIMIZED",
...@@ -623,20 +651,21 @@ begin ...@@ -623,20 +651,21 @@ begin
-- --
g_phys_uart => true, g_phys_uart => true,
g_virtual_uart => true, g_virtual_uart => true,
g_aux_clks => 1, g_aux_clks => 0,
g_ep_rxbuf_size => 1024, g_ep_rxbuf_size => 1024,
g_dpram_initf => "wrc.ram", g_dpram_initf => "", --wrc.ram",
g_dpram_size => 90112/4, --16384, g_dpram_size => 90112/4, --16384,
g_interface_mode => PIPELINED, g_interface_mode => PIPELINED,
g_address_granularity => BYTE) g_address_granularity => BYTE)
port map ( port map (
clk_sys_i => clk_sys, clk_sys_i => clk_sys,
clk_dmtd_i => clk_dmtd, clk_dmtd_i => clk_dmtd,
clk_ref_i => clk_125m_pllref, clk_ref_i => clk_125m_pllref,
clk_aux_i => (others => '0'), clk_aux_i => (others => '0'),
clk_ext_i => dio_clk, clk_ext_i => clk_ext,
pps_ext_i => dio_in(3), clk_ext_mul_i => clk_ext_mul,
rst_n_i => local_reset_n, pps_ext_i => dio_in(3),
rst_n_i => local_reset_n,
dac_hpll_load_p1_o => dac_hpll_load_p1, dac_hpll_load_p1_o => dac_hpll_load_p1,
dac_hpll_data_o => dac_hpll_data, dac_hpll_data_o => dac_hpll_data,
...@@ -656,19 +685,19 @@ begin ...@@ -656,19 +685,19 @@ begin
phy_rst_o => phy_rst, phy_rst_o => phy_rst,
phy_loopen_o => phy_loopen, phy_loopen_o => phy_loopen,
led_act_o => LED_RED, led_act_o => LED_RED,
led_link_o => LED_GREEN, led_link_o => LED_GREEN,
scl_o => wrc_scl_o, scl_o => wrc_scl_o,
scl_i => wrc_scl_i, scl_i => wrc_scl_i,
sda_o => wrc_sda_o, sda_o => wrc_sda_o,
sda_i => wrc_sda_i, sda_i => wrc_sda_i,
sfp_scl_o => sfp_scl_o, sfp_scl_o => sfp_scl_o,
sfp_scl_i => sfp_scl_i, sfp_scl_i => sfp_scl_i,
sfp_sda_o => sfp_sda_o, sfp_sda_o => sfp_sda_o,
sfp_sda_i => sfp_sda_i, sfp_sda_i => sfp_sda_i,
sfp_det_i => sfp_mod_def0_b, sfp_det_i => sfp_mod_def0_b,
btn1_i => button1_i, btn1_i => button1_i,
btn2_i => button2_i, btn2_i => button2_i,
uart_rxd_i => uart_rxd_i, uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o, uart_txd_o => uart_txd_o,
...@@ -689,7 +718,7 @@ begin ...@@ -689,7 +718,7 @@ begin
tm_dac_value_o => open, tm_dac_value_o => open,
tm_dac_wr_o => open, tm_dac_wr_o => open,
tm_clk_aux_lock_en_i => (others=>'0'), tm_clk_aux_lock_en_i => (others => '0'),
tm_clk_aux_locked_o => open, tm_clk_aux_locked_o => open,
tm_time_valid_o => open, tm_time_valid_o => open,
tm_tai_o => open, tm_tai_o => open,
...@@ -697,7 +726,7 @@ begin ...@@ -697,7 +726,7 @@ begin
pps_p_o => pps, pps_p_o => pps,
pps_led_o => pps_led, pps_led_o => pps_led,
dio_o => dio_out(4 downto 1), -- dio_o => dio_out(4 downto 1),
rst_aux_n_o => etherbone_rst_n rst_aux_n_o => etherbone_rst_n
); );
...@@ -830,18 +859,28 @@ begin ...@@ -830,18 +859,28 @@ begin
OB => dio_n_o(i) OB => dio_n_o(i)
); );
end generate gen_dio_iobufs; end generate gen_dio_iobufs;
U_input_buffer : IBUFDS
U_input_buffer : IBUFGDS
generic map ( generic map (
DIFF_TERM => true) DIFF_TERM => true)
port map ( port map (
O => dio_clk, O => clk_ext,
I => dio_clk_p_i, I => dio_clk_p_i,
IB => dio_clk_n_i IB => dio_clk_n_i
); );
dio_led_bot_o <= '0'; dio_led_bot_o <= '0';
dio_out(0) <= pps; process(clk_125m_pllref)
begin
if rising_edge(clk_125m_pllref) then
clk_ref_div2 <= not clk_ref_div2;
end if;
end process;
dio_out(0) <= pps;
dio_out(1) <= clk_ref_div2;
dio_oe_n_o(0) <= '0'; dio_oe_n_o(0) <= '0';
dio_oe_n_o(2 downto 1) <= (others => '0'); dio_oe_n_o(2 downto 1) <= (others => '0');
dio_oe_n_o(3) <= '1'; -- for external 1-PPS dio_oe_n_o(3) <= '1'; -- for external 1-PPS
......
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