TAI time is sampled from clk_ref to clk_sys domain.
Apparently, such sampling sometimes takes more than
the configured 20 periods. Likely, this is not a problem,
but the updated gc_synchronizer2 now complains. So, I
increased the sampling time to 30 periods.

When g_num_exts=0, the input of xwr_softpll_ng
clk_ext_mul_i        : in std_logic_vector(g_num_exts-1 downto 0);
was of wrong range, i.e. std_logic_vector(-1 to 0).

Function f_nonzero_vector() was added to generate
std_logic_vector(0 to 0) in the case when g_num_exts=0.

Compilation and synthesis run at any new push. Simulation run according
to CI schedule configured on OHWR.

upgrade clbv3_ref_design to VIVADO clbv3_ref_design: add valid xdc and bmm file; use generic g_direct_dmtd

add wrpc/wrc_phy16_direct_dmtd.bram (spll KP parameters times 5 due to VCXOs range 20 ppm, incremented mode master lock timeout)
wrc_phy16_direct_dmtd.bram build with:
wrpc-sw.git peter_direct_dmtd SHA 50f1c0e
ppsi.git peter_direct_dmtd SHA bf5f6de

- Add generic parameter for the SDB info of the auxiliary interface of the WRPC.
- Export pps_csync and pps_valid ports from the WRPC.

wr_nic_wrapper: Fix copyright issues.

Fix a place & route error related to the OBUF used for PPS output signal.

It's used only locally in dmtd sampler. We don't have enough global
clock nets in Virtex6 for 18-port version of WRS.