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Tomasz Wlostowski authored
Explanation: - the busy flag is asserted whenever the TX state machine is not idle (e.g not in TX_IDLE or TX_COMMA state) or if the TX FIFO is not empty - since the TX FSM works in different clock domain than the system clock, where the busy flag is outputted, there is a synchronizer - The Heisenbug appeared in designs where TX clock is phase locked to the system clock (e.g. SPEC/SVEC). It was caused by a cross-clock domain setup time violation between the output of the LUT generating the tx_busy signal and the first flip flop of the synchronizer, which under certain conditions could permanently sample incorrect output of the LUT, resulting with the pcs_busy_o signal being stuck at 1 forever. - registering the TX clock domain busy signal removes glitches and fixes the problem.
598a2f6c
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fabric | ||
timing | ||
wr_dacs | ||
wr_eca | ||
wr_endpoint | ||
wr_mini_nic | ||
wr_pps_gen | ||
wr_si57x_interface | ||
wr_softpll_ng | ||
wr_tbi_phy | ||
wr_tlu | ||
wrc_core |