When using a 1GHz WR-synchronous sample clock to drive LVDS, the
phase between the clock enable and VCO should be -1.5 periods.

There was a bug in the project whereby the altera_phase core was
misconfigured to move the WR ref in relation to the TX clock, while
forgetting to move the LVDS VCO and enable clocks. Now that this
phase shift is applied equally to all PLL outputs, the work around
discovered in commit 34d0a504 is not necessary.