White Rabbit PTP Core (WRPC)
The White Rabbit PTP Core is an Ethernet MAC implementation capable of providing precise timing. It can be used for sending and receiving regular Ethernet frames between user-defined HDL modules and a physical medium. It also implements the White Rabbit protocol to provide sub-nanosecond time synchronization.
The White Rabbit PTP Core can operate in one of the following modes:
- GrandMaster: WR Master synchronized to an external 1-PPS and 10 MHz clock signal, propagates precise timing to other WR-compliant devices
- Master: WR Master with free-running oscillator, propagates precise timing to other WR-compliant devices
- Slave: synchronizes its internal oscillator to another WR Master device
Boards and FPGA platforms supported by the WRPC
Platform | Boards |
Xilinx Spartan6 | SPEC, SVEC, SPEXI, .... |
Xilinx Kintex-7 | NIKHEF, Seven Solutions |
Not supported (uses a different Serdes than Kintex, requires a new wrapper with bitslide, and making sure the Serdes is deterministic). Contact us | |
Xilinx Virtex-7 using GTH | NIKHEF |
Xilinx Zynq | Seven Solutions |
Altera Arria II | GSI |
Altera Arria V | VFC-HD, GSI |
Fig.1: WR PTP Core external interfaces
Fig.2: WR PTP Core block diagram
Releases
Documentation
- White Rabbit PTP Core User's Manual describes how to build and run the Core.
- White Rabbit PTP Core HDL specification describes all input, output ports and VHDL generic parameters of the Core.
- Default calibration values for the WR PTP Core and the WR Switch
- White Rabbit PTP Core Hands-on Training materials
Other documents
- Frequently Asked Questions about the White Rabbit PTP Core
- HDL memory map
- List of all WRPC Shell commands
- Running simple SPEC-to-SPEC White Rabbit demo
- White Rabbit Node Reference Design
- List of supported SFP transceivers
Roadmap for WR PTP Core releases
v3.0 | v.4.0 | |
Release date | 16/12/2015 | 15/03/2017 |
fixes for timing under non-PTP traffic [905], [1200], [1203] |
x | |
fixes to withstand heavy traffic [1206], [1209] |
x | |
lock helper PLL below the ref frequency | x | |
LM32 RAM size increased to 128kB | x | |
Kintex-7 support | x | |
Flash support for storage | x | |
SDBFS for storage | x | |
TX pause support | x | |
TX runt frames padding | x | |
FIFO-based simplified Mini-NIC | x | |
Improved synthesis time | x | |
Improved inferred RAM description for Xilinx | x | |
Platform and board support packages | x | |
Fixed generic-dependent clock arrays [1224], [1225] |
x | |
SNMP for remote diagnostics | x | |
Syslog for remote diagnostics | x | |
VLAN support | x | |
Optional PTP P2P mode | x | |
Fixed synchronization issues [1530], [1540], [1550] |
x | |
Fixed 64-bit values printing for long WR links | x | |
Added wrpc-dump tool | x | |
Expanded user doc, now also with HDL documentation | x |
Contacts
- Grzegorz Daniluk - CERN
- Tomasz Włostowski - CERN
Project Status
Date | Event |
11-08-2012 | v2.0 Release |
20-12-2013 | v2.1 Release |
10-02-2015 | New release should be made soon. Will have support for Kintex7 and FLASH-stored calibration parameters. |
16-12-2015 | v3.0 Release |
15-03-2017 | v4.0 Release |
15 March 2017