Added missing ports for gn4124 component declaration.

500edebb · Projects · e65f57f1 · 500edebb
Commit 500edebb authored May 26, 2016 by Projects
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wr_nic_dio_top.vhd top/specdio/wr_nic_dio_top.vhd +7 -1

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--- a/top/specdio/wr_nic_dio_top.vhd
+++ b/top/specdio/wr_nic_dio_top.vhd
@@ -296,6 +296,9 @@ architecture rtl of wr_nic_dio_top is
      csr_dat_i   : in  std_logic_vector(31 downto 0);
      csr_ack_i   : in  std_logic;
      csr_stall_i : in  std_logic;
+      csr_err_i   : in  std_logic := '0';
+      csr_rty_i   : in  std_logic := '0';
+      csr_int_i   : in  std_logic := '0';

      ---------------------------------------------------------
      -- DMA wishbone interface (master pipelined)
@@ -308,7 +311,10 @@ architecture rtl of wr_nic_dio_top is
      dma_cyc_o   : out std_logic;
      dma_dat_i   : in  std_logic_vector(31 downto 0) := x"00000000";
      dma_ack_i   : in  std_logic                     := '0';
-      dma_stall_i : in  std_logic                     := '0'
+      dma_stall_i : in  std_logic                     := '0';
+      dma_err_i   : in  std_logic                     := '0';
+      dma_rty_i   : in  std_logic                     := '0';
+      dma_int_i   : in  std_logic                     := '0'
      );
  end component;  --  gn4124_core