Skip to content

W
White Rabbit Network Interface Card
Commit 66d9ed56 authored by Miguel Jimenez Lopez's avatar Miguel Jimenez Lopez
Browse files
Options

Fix identation.

parent d81acd5e
Hide whitespace changes
Inline Side-by-side
Showing with 159 additions and 159 deletions
wr-cores @ 4e5e3dfc
Subproject commit f0519a1f5f7f2261b861e6a6d4562e2bec875fb4
Subproject commit 4e5e3dfc01e395a81d9403bd1e150560972685f7
hdl/top/nic/nic_top.vhd
View file @ 66d9ed56
......@@ -7,7 +7,7 @@
-- Author(s) : Miguel Jimenez-Lopez
-- Company : Seven Solutions
-- Created : 2019-03-28
-- Last update: 2019-03-28
-- Last update: 2019-08-27
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level file for the reference design of the WR-NIC in the
......@@ -58,66 +58,66 @@ use unisim.vcomponents.all;
entity nic_top is
generic (
g_DPRAM_INITF : string := "../../ip_cores/wr-cores/bin/wrpc/wrc_phy8.bram";
g_DPRAM_INITF : string := "../../ip_cores/wr-cores/bin/wrpc/wrc_phy8.bram";
-- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
-- changed to non-zero in the instantiation of the top level DUT in the testbench.
-- Its purpose is to reduce some internal counters/timeouts to speed up simulations.
g_SIMULATION : integer := 0
);
g_SIMULATION : integer := 0
);
port (
---------------------------------------------------------------------------
-- Clocks/resets
---------------------------------------------------------------------------
-- Local oscillators
clk_20m_vcxo_i : in std_logic; -- 20MHz VCXO clock
clk_20m_vcxo_i : in std_logic; -- 20MHz VCXO clock
clk_125m_pllref_p_i : in std_logic; -- 125 MHz PLL reference
clk_125m_pllref_p_i : in std_logic; -- 125 MHz PLL reference
clk_125m_pllref_n_i : in std_logic;
clk_125m_gtp_n_i : in std_logic; -- 125 MHz GTP reference
clk_125m_gtp_n_i : in std_logic; -- 125 MHz GTP reference
clk_125m_gtp_p_i : in std_logic;
---------------------------------------------------------------------------
-- GN4124 PCIe bridge signals
---------------------------------------------------------------------------
-- From GN4124 Local bus
gn_rst_n : in std_logic; -- Reset from GN4124 (RSTOUT18_N)
gn_rst_n : in std_logic; -- Reset from GN4124 (RSTOUT18_N)
-- PCIe to Local [Inbound Data] - RX
gn_p2l_clk_n : in std_logic; -- Receiver Source Synchronous Clock-
gn_p2l_clk_p : in std_logic; -- Receiver Source Synchronous Clock+
gn_p2l_rdy : out std_logic; -- Rx Buffer Full Flag
gn_p2l_dframe : in std_logic; -- Receive Frame
gn_p2l_valid : in std_logic; -- Receive Data Valid
gn_p2l_data : in std_logic_vector(15 downto 0); -- Parallel receive data
gn_p2l_clk_n : in std_logic; -- Receiver Source Synchronous Clock-
gn_p2l_clk_p : in std_logic; -- Receiver Source Synchronous Clock+
gn_p2l_rdy : out std_logic; -- Rx Buffer Full Flag
gn_p2l_dframe : in std_logic; -- Receive Frame
gn_p2l_valid : in std_logic; -- Receive Data Valid
gn_p2l_data : in std_logic_vector(15 downto 0); -- Parallel receive data
-- Inbound Buffer Request/Status
gn_p_wr_req : in std_logic_vector(1 downto 0); -- PCIe Write Request
gn_p_wr_rdy : out std_logic_vector(1 downto 0); -- PCIe Write Ready
gn_rx_error : out std_logic; -- Receive Error
gn_p_wr_req : in std_logic_vector(1 downto 0); -- PCIe Write Request
gn_p_wr_rdy : out std_logic_vector(1 downto 0); -- PCIe Write Ready
gn_rx_error : out std_logic; -- Receive Error
-- Local to Parallel [Outbound Data] - TX
gn_l2p_clkn : out std_logic; -- Transmitter Source Synchronous Clock-
gn_l2p_clkp : out std_logic; -- Transmitter Source Synchronous Clock+
gn_l2p_dframe : out std_logic; -- Transmit Data Frame
gn_l2p_valid : out std_logic; -- Transmit Data Valid
gn_l2p_edb : out std_logic; -- Packet termination and discard
gn_l2p_data : out std_logic_vector(15 downto 0); -- Parallel transmit data
gn_l2p_clkn : out std_logic; -- Transmitter Source Synchronous Clock-
gn_l2p_clkp : out std_logic; -- Transmitter Source Synchronous Clock+
gn_l2p_dframe : out std_logic; -- Transmit Data Frame
gn_l2p_valid : out std_logic; -- Transmit Data Valid
gn_l2p_edb : out std_logic; -- Packet termination and discard
gn_l2p_data : out std_logic_vector(15 downto 0); -- Parallel transmit data
-- Outbound Buffer Status
gn_l2p_rdy : in std_logic; -- Tx Buffer Full Flag
gn_l_wr_rdy : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
gn_p_rd_d_rdy : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
gn_tx_error : in std_logic; -- Transmit Error
gn_vc_rdy : in std_logic_vector(1 downto 0); -- Channel ready
gn_l2p_rdy : in std_logic; -- Tx Buffer Full Flag
gn_l_wr_rdy : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
gn_p_rd_d_rdy : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
gn_tx_error : in std_logic; -- Transmit Error
gn_vc_rdy : in std_logic_vector(1 downto 0); -- Channel ready
-- General Purpose Interface
gn_gpio : inout std_logic_vector(1 downto 0); -- gn_gpio[0] -> GN4124 GPIO8
-- gn_gpio[1] -> GN4124 GPIO9
gn_gpio : inout std_logic_vector(1 downto 0); -- gn_gpio[0] -> GN4124 GPIO8
-- gn_gpio[1] -> GN4124 GPIO9
---------------------------------------------------------------------------
-- SPI interface to DACs
---------------------------------------------------------------------------
plldac_sclk_o : out std_logic;
plldac_din_o : out std_logic;
pll25dac_cs_n_o : out std_logic; --cs1
pll20dac_cs_n_o : out std_logic; --cs2
plldac_sclk_o : out std_logic;
plldac_din_o : out std_logic;
pll25dac_cs_n_o : out std_logic; --cs1
pll20dac_cs_n_o : out std_logic; --cs2
---------------------------------------------------------------------------
-- SFP I/O for transceiver
......@@ -127,9 +127,9 @@ entity nic_top is
sfp_txn_o : out std_logic;
sfp_rxp_i : in std_logic;
sfp_rxn_i : in std_logic;
sfp_mod_def0_i : in std_logic; -- sfp detect
sfp_mod_def1_b : inout std_logic; -- scl
sfp_mod_def2_b : inout std_logic; -- sda
sfp_mod_def0_i : in std_logic; -- sfp detect
sfp_mod_def1_b : inout std_logic; -- scl
sfp_mod_def2_b : inout std_logic; -- sda
sfp_rate_select_o : out std_logic;
sfp_tx_fault_i : in std_logic;
sfp_tx_disable_o : out std_logic;
......@@ -162,11 +162,11 @@ entity nic_top is
---------------------------------------------------------------------------
-- Red LED next to the SFP: blinking indicates that packets are being
-- transferred.
led_act_o : out std_logic;
led_act_o : out std_logic;
-- Green LED next to the SFP: indicates if the link is up.
led_link_o : out std_logic;
button1_i : in std_logic;
button1_i : in std_logic;
---------------------------------------------------------------------------
-- Digital I/O FMC Pins
......@@ -192,7 +192,7 @@ entity nic_top is
-- Output enable. When dio_oe_n_o(N) is 0, connector (N+1) on the front
-- panel is configured as an output.
dio_oe_n_o : out std_logic_vector(4 downto 0);
dio_oe_n_o : out std_logic_vector(4 downto 0);
-- Termination enable. When dio_term_en_o(N) is 1, connector (N+1) on the front
-- panel is 50-ohm terminated
......@@ -208,7 +208,7 @@ entity nic_top is
dio_scl_b : inout std_logic;
dio_sda_b : inout std_logic
);
);
end entity nic_top;
architecture top of nic_top is
......@@ -224,7 +224,7 @@ architecture top of nic_top is
constant c_NUM_WB_SLAVES : integer := 2;
-- Primary Wishbone master(s) offsets
constant c_WB_MASTER_PCIE : integer := 0;
constant c_WB_MASTER_PCIE : integer := 0;
-- Primary Wishbone slave(s) offsets
constant c_WB_SLAVE_WRC : integer := 0;
......@@ -242,8 +242,8 @@ architecture top of nic_top is
-- Primary wishbone crossbar layout
constant c_WB_LAYOUT : t_sdb_record_array(c_NUM_WB_SLAVES - 1 downto 0) := (
c_WB_SLAVE_WRC => f_sdb_embed_bridge(c_WRC_BRIDGE_SDB, x"00000000"),
c_WB_SLAVE_NIC => f_sdb_embed_bridge(c_NIC_BRIDGE_SDB, x"00040000"));
c_WB_SLAVE_WRC => f_sdb_embed_bridge(c_WRC_BRIDGE_SDB, x"00000000"),
c_WB_SLAVE_NIC => f_sdb_embed_bridge(c_NIC_BRIDGE_SDB, x"00040000"));
-----------------------------------------------------------------------------
-- Signals
......@@ -285,34 +285,34 @@ architecture top of nic_top is
signal onewire_oe : std_logic;
-- LEDs and GPIO
signal wrc_abscal_txts_out : std_logic;
signal wrc_abscal_rxts_out : std_logic;
signal wrc_pps_out : std_logic;
signal wrc_pps_csync_out : std_logic;
signal wrc_pps_csync_out_ext : std_logic;
signal wrc_abscal_txts_out : std_logic;
signal wrc_abscal_rxts_out : std_logic;
signal wrc_pps_out : std_logic;
signal wrc_pps_csync_out : std_logic;
signal wrc_pps_csync_out_ext : std_logic;
signal wrc_pps_csync_out_ext_int : std_logic;
signal wrc_pps_valid_out : std_logic;
signal wrc_pps_valid_out_ext : std_logic;
signal wrc_pps_valid_out : std_logic;
signal wrc_pps_valid_out_ext : std_logic;
signal wrc_pps_valid_out_ext_int : std_logic;
signal wrc_pps_led : std_logic;
signal wrc_pps_in : std_logic;
signal svec_led : std_logic_vector(15 downto 0);
signal wrc_pps_led : std_logic;
signal wrc_pps_in : std_logic;
signal svec_led : std_logic_vector(15 downto 0);
-- DIO Mezzanine
signal dio_in : std_logic_vector(4 downto 0);
signal dio_out : std_logic_vector(4 downto 0);
signal vic_irq : std_logic;
signal vic_irq : std_logic;
-- WR Fabric I/F
signal wrc_wrf_src_out : t_wrf_source_out;
signal wrc_wrf_src_in : t_wrf_source_in;
signal wrc_wrf_snk_out : t_wrf_sink_out;
signal wrc_wrf_snk_in : t_wrf_sink_in;
-- Tx Timestamp
signal wrc_timestamps_out : t_txtsu_timestamp;
signal wrc_timestamps_ack_in : std_logic := '1';
signal wrc_timestamps_out : t_txtsu_timestamp;
signal wrc_timestamps_ack_in : std_logic := '1';
begin -- architecture top
......@@ -324,8 +324,8 @@ begin -- architecture top
generic map (
g_num_masters => c_NUM_WB_MASTERS,
g_num_slaves => c_NUM_WB_SLAVES,
g_registered => TRUE,
g_wraparound => TRUE,
g_registered => true,
g_wraparound => true,
g_layout => c_WB_LAYOUT,
g_sdb_addr => c_SDB_ADDRESS)
port map (
......@@ -387,9 +387,9 @@ begin -- architecture top
---------------------------------------------------------
-- DMA registers wishbone interface (slave classic)
dma_reg_clk_i => clk_sys_62m5,
dma_reg_adr_i => (others=>'0'),
dma_reg_dat_i => (others=>'0'),
dma_reg_sel_i => (others=>'0'),
dma_reg_adr_i => (others => '0'),
dma_reg_dat_i => (others => '0'),
dma_reg_sel_i => (others => '0'),
dma_reg_stb_i => '0',
dma_reg_we_i => '0',
dma_reg_cyc_i => '0',
......@@ -412,7 +412,7 @@ begin -- architecture top
---------------------------------------------------------
-- L2P DMA Interface (Pipelined Wishbone master)
dma_clk_i => clk_sys_62m5,
dma_dat_i => (others=>'0'),
dma_dat_i => (others => '0'),
dma_ack_i => '1',
dma_stall_i => '0',
dma_err_i => '0',
......@@ -430,7 +430,7 @@ begin -- architecture top
cmp_xwrc_board_spec : xwrc_board_spec
generic map (
g_simulation => g_simulation,
g_with_external_clock_input => TRUE,
g_with_external_clock_input => true,
g_dpram_initf => g_dpram_initf,
g_fabric_iface => PLAIN)
port map (
......@@ -447,75 +447,75 @@ begin -- architecture top
rst_sys_62m5_n_o => rst_sys_62m5_n,
rst_ref_125m_n_o => rst_ref_125m_n,
plldac_sclk_o => plldac_sclk_o,
plldac_din_o => plldac_din_o,
pll25dac_cs_n_o => pll25dac_cs_n_o,
pll20dac_cs_n_o => pll20dac_cs_n_o,
sfp_txp_o => sfp_txp_o,
sfp_txn_o => sfp_txn_o,
sfp_rxp_i => sfp_rxp_i,
sfp_rxn_i => sfp_rxn_i,
sfp_det_i => sfp_mod_def0_i,
sfp_sda_i => sfp_sda_in,
sfp_sda_o => sfp_sda_out,
sfp_scl_i => sfp_scl_in,
sfp_scl_o => sfp_scl_out,
sfp_rate_select_o => sfp_rate_select_o,
sfp_tx_fault_i => sfp_tx_fault_i,
sfp_tx_disable_o => sfp_tx_disable_o,
sfp_los_i => sfp_los_i,
eeprom_sda_i => eeprom_sda_in,
eeprom_sda_o => eeprom_sda_out,
eeprom_scl_i => eeprom_scl_in,
eeprom_scl_o => eeprom_scl_out,
onewire_i => onewire_data,
onewire_oen_o => onewire_oe,
plldac_sclk_o => plldac_sclk_o,
plldac_din_o => plldac_din_o,
pll25dac_cs_n_o => pll25dac_cs_n_o,
pll20dac_cs_n_o => pll20dac_cs_n_o,
sfp_txp_o => sfp_txp_o,
sfp_txn_o => sfp_txn_o,
sfp_rxp_i => sfp_rxp_i,
sfp_rxn_i => sfp_rxn_i,
sfp_det_i => sfp_mod_def0_i,
sfp_sda_i => sfp_sda_in,
sfp_sda_o => sfp_sda_out,
sfp_scl_i => sfp_scl_in,
sfp_scl_o => sfp_scl_out,
sfp_rate_select_o => sfp_rate_select_o,
sfp_tx_fault_i => sfp_tx_fault_i,
sfp_tx_disable_o => sfp_tx_disable_o,
sfp_los_i => sfp_los_i,
eeprom_sda_i => eeprom_sda_in,
eeprom_sda_o => eeprom_sda_out,
eeprom_scl_i => eeprom_scl_in,
eeprom_scl_o => eeprom_scl_out,
onewire_i => onewire_data,
onewire_oen_o => onewire_oe,
-- Uart
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
-- SPI Flash
flash_sclk_o => flash_sclk_o,
flash_ncs_o => flash_ncs_o,
flash_mosi_o => flash_mosi_o,
flash_miso_i => flash_miso_i,
wb_slave_o => cnx_slave_out(c_WB_SLAVE_WRC),
wb_slave_i => cnx_slave_in(c_WB_SLAVE_WRC),
wrf_src_o => wrc_wrf_src_out,
wrf_src_i => wrc_wrf_src_in,
wrf_snk_o => wrc_wrf_snk_out,
wrf_snk_i => wrc_wrf_snk_in,
abscal_txts_o => wrc_abscal_txts_out,
abscal_rxts_o => wrc_abscal_rxts_out,
timestamps_o => wrc_timestamps_out,
timestamps_ack_i => wrc_timestamps_ack_in,
pps_ext_i => wrc_pps_in,
pps_p_o => wrc_pps_out,
pps_csync_o => wrc_pps_csync_out,
pps_valid_o => wrc_pps_valid_out,
pps_led_o => wrc_pps_led,
led_link_o => led_link_o,
led_act_o => led_act_o);
flash_sclk_o => flash_sclk_o,
flash_ncs_o => flash_ncs_o,
flash_mosi_o => flash_mosi_o,
flash_miso_i => flash_miso_i,
wb_slave_o => cnx_slave_out(c_WB_SLAVE_WRC),
wb_slave_i => cnx_slave_in(c_WB_SLAVE_WRC),
wrf_src_o => wrc_wrf_src_out,
wrf_src_i => wrc_wrf_src_in,
wrf_snk_o => wrc_wrf_snk_out,
wrf_snk_i => wrc_wrf_snk_in,
abscal_txts_o => wrc_abscal_txts_out,
abscal_rxts_o => wrc_abscal_rxts_out,
timestamps_o => wrc_timestamps_out,
timestamps_ack_i => wrc_timestamps_ack_in,
pps_ext_i => wrc_pps_in,
pps_p_o => wrc_pps_out,
pps_csync_o => wrc_pps_csync_out,
pps_valid_o => wrc_pps_valid_out,
pps_led_o => wrc_pps_led,
led_link_o => led_link_o,
led_act_o => led_act_o);
-- Logic to extend pps_csync_o (125 MHz) in order to be detected
-- in clk_sys (62.5 MHz) domain.
U_Extend_pps_csync : gc_extend_pulse
generic map (
g_width => 3)
port map (
clk_i => clk_ref_125m,
rst_n_i => rst_ref_125m_n,
pulse_i => wrc_pps_csync_out,
extended_o => wrc_pps_csync_out_ext_int);
sync_ffs_pps_csync : gc_sync_ffs
generic map (
g_width => 3)
port map (
clk_i => clk_ref_125m,
rst_n_i => rst_ref_125m_n,
pulse_i => wrc_pps_csync_out,
extended_o => wrc_pps_csync_out_ext_int);
sync_ffs_pps_csync : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
......@@ -529,15 +529,15 @@ begin -- architecture top
-- Logic to extend pps_valid_o (125 MHz) in order to be detected
-- in clk_sys (62.5 MHz) domain.
U_Extend_pps_valid : gc_extend_pulse
generic map (
g_width => 3)
port map (
clk_i => clk_ref_125m,
rst_n_i => rst_ref_125m_n,
pulse_i => wrc_pps_valid_out,
extended_o => wrc_pps_valid_out_ext_int);
sync_ffs_pps_valid : gc_sync_ffs
generic map (
g_width => 3)
port map (
clk_i => clk_ref_125m,
rst_n_i => rst_ref_125m_n,
pulse_i => wrc_pps_valid_out,
extended_o => wrc_pps_valid_out_ext_int);
sync_ffs_pps_valid : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
......@@ -561,8 +561,8 @@ begin -- architecture top
------------------------------------------------------------------------------
-- Digital I/O FMC Mezzanine connections
------------------------------------------------------------------------------
gen_dio_iobufs: for I in 0 to 4 generate
U_ibuf: IBUFDS
gen_dio_iobufs : for I in 0 to 4 generate
U_ibuf : IBUFDS
generic map (
DIFF_TERM => true)
port map (
......@@ -579,15 +579,15 @@ begin -- architecture top
-- Configure Digital I/Os 0 to 3 as outputs
dio_oe_n_o(2 downto 0) <= (others => '0');
-- Configure Digital I/Os 3 and 4 as inputs for external reference
dio_oe_n_o(3) <= '1'; -- for external 1-PPS
dio_oe_n_o(4) <= '1'; -- for external 10MHz clock
dio_oe_n_o(3) <= '1'; -- for external 1-PPS
dio_oe_n_o(4) <= '1'; -- for external 10MHz clock
-- All DIO connectors are not terminated
dio_term_en_o <= (others => '0');
-- EEPROM I2C tri-states
dio_sda_b <= '0' when (eeprom_sda_out = '0') else 'Z';
dio_sda_b <= '0' when (eeprom_sda_out = '0') else 'Z';
eeprom_sda_in <= dio_sda_b;
dio_scl_b <= '0' when (eeprom_scl_out = '0') else 'Z';
dio_scl_b <= '0' when (eeprom_scl_out = '0') else 'Z';
eeprom_scl_in <= dio_scl_b;
-- Div by 2 reference clock to LEMO connector
......@@ -598,7 +598,7 @@ begin -- architecture top
end if;
end process;
cmp_ibugds_extref: IBUFGDS
cmp_ibugds_extref : IBUFGDS
generic map (
DIFF_TERM => true)
port map (
......@@ -606,28 +606,28 @@ begin -- architecture top
I => dio_clk_p_i,
IB => dio_clk_n_i);
wrc_pps_in <= dio_in(3);
dio_out(0) <= wrc_pps_out;
dio_out(1) <= wrc_abscal_rxts_out;
dio_out(2) <= wrc_abscal_txts_out;
wrc_pps_in <= dio_in(3);
dio_out(0) <= wrc_pps_out;
dio_out(1) <= wrc_abscal_rxts_out;
dio_out(2) <= wrc_abscal_txts_out;
-- LEDs
U_Extend_PPS : gc_extend_pulse
generic map (
g_width => 10000000)
port map (
clk_i => clk_ref_125m,
rst_n_i => rst_ref_125m_n,
pulse_i => wrc_pps_led,
extended_o => dio_led_top_o);
generic map (
g_width => 10000000)
port map (
clk_i => clk_ref_125m,
rst_n_i => rst_ref_125m_n,
pulse_i => wrc_pps_led,
extended_o => dio_led_top_o);
dio_led_bot_o <= '0';
cmp_nic_wrapper : wr_nic_wrapper
generic map(
g_num_irqs => 1,
g_num_ports => 1
)
)
port map(
clk_sys_i => clk_sys_62m5,
resetn_i => rst_sys_62m5_n,
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment