wrspec: first draft of V2

323a9c76 · Maciej Lipinski · 4e0d9f47 · 323a9c76 · 323a9c76 · 323a9c76
Commit 323a9c76 authored Apr 29, 2011 by Maciej Lipinski
14 changed files
--- a/src/Makefile
+++ b/src/Makefile
@@ -7,6 +7,7 @@ wrspec.pdf : wrspec.tex figs
 	latex $^
 	dvips wrspec
 	ps2pdf wrspec.ps
+	cp wrspec.pdf ../

 figs:
 	$(MAKE) -C fig

--- a/src/deleted
+++ b/src/deleted
+where the parentDS with index 0 is used as
+parentDS defined in
+	the standard, the parentDS with index 1 and greater are used to store information about
+	backup sources of timing information, updated as defined by modified BMC, used by
+	platform-specific hardware support for topology redundancy. 
+
+
+==============================
+
+It can be noted that if $\Delta <<  \mu$, the above equation can be simplified:
+\begin{equation}
+\label{eq:aqasymmSympl}
+  \eqasymm = \Delta_{tx_m} + \Delta_{rx_s} - \frac{\Delta - \alpha \mu}{2 + \alpha}
+\end{equation}.
+
+=============================
+
+IEEE1588 standard allows its custamisation by the means of PTP profile which specifies set of
+required and prohibited options as well as ranges and defaults of configurations. WRPTP takes a
+full advantage of PTP profile defining WR TLVs, modification to Best Master Clock algorithm and
+default attribut values.
+
+=============================
+\begin{table}[ph!]
+\caption{WRPTP Data Sets fields}
+\centering
+\begin{tabular}{| c     |     p{2.0cm}  |    p{2.5cm}         | p{1.5cm} |            p{4cm}  
+                                                             |}        \hline   
+   
+\textbf{DS member}     	& \textbf{DS name}&\textbf{Values}& \textbf{D}ynamic or \textbf{S}tatic &
+\textbf{Description}                                                                             
+           \\  
+			&              &                         &       &                         
+                                                                                         \\ \hline
+portWrConfig   		& portDS       & NON\_WR,
+					 WR\_S\_ONLY,  
+					 WR\_M\_ONLY 
+					 WR\_M\_AND\_S		&S	& Determines predefined 
+									  function of WR port
+									  (static).\\ \hline
+portCalibrated 		& portDS       & TRUE, FALSE            &D        & Indicates whether fixed 
+									  delays of the given port
+									  are known.\\ \hline
+deltaTx       		& portDS       & 64 bit value           &D        & Port's $\Delta_{tx}$ 
+									  measured in picoseconds
+									  and multiplied by
+									  ${2^{16}}$.\\ \hline
+deltaRx     		& portDS       & 64 bit value           &D      & Port's $\Delta_{rx}$
+									  measured in picoseconds
+									  and multiplied by
+									  ${2^{16}}$.\\ \hline
+calPeriod   		& portDS       & 32 bit value           &S        & Calibration period in
+									  microseconds. \\ \hline
+calPattern   		& portDS       & 32 bit value           &S      & Medium specific 
+									  calibration pattern.
+									  \\ \hline
+calPatternLen  		& portDS       & 16 bit value           &S      & Number of bits of
+									  calPattern to be
+									  repeated.\\ \hline
+portWrMode		& portDS       & TRUE, FALSE            &D      & If TRUE, the port is 
+									  working in WR mode.      
+									  \\ \hline
+wrAlpha			& portDS       & 32 bit value           &S         & \textit{Medium 
+									  correlation parameter} as
+									  described in
+								      section~\ref{sec:singlefiber}.
+   
+									  \\ \hline
+parentPortWrConfig 	& portDS     	& NON\_WR,
+					 WR\_S\_ONLY,  
+					 WR\_M\_ONLY 
+					 WR\_M\_AND\_S          &D      & Determines predefined	
+									  function of the PTP	
+									  parent.\\ \hline
+parentPortDeltaTx      	& portDS	& 64 bit value           &D	& Parent's
+									  $\Delta_{tx}$ measured
+									  in picoseconds and
+									  multiplied by
+									  ${2^{16}}$. \\ \hline
+parentPortDeltaRx     	& portDS	& 64 bit value           &D	& Parent's 
+									  $\Delta_{rx}$ measured in
+									  picoseconds and multiplied
+									  by ${2^{16}}$. \\ \hline
+parentPortWrMode	& portDS	& TRUE, FALSE            &D      & If TRUE, the parent port
+									  is working in WR mode. 
+									  \\ \hline
+primarySlavePortNumber	& currentDS	& 16 bits value         &D      & If 0, no
+									  primary Slave is
+									  selected. 1, 2 ,...N-value
+									  of portNumber (clause
+									  7.5.2.3 PTP), selected as
+									  primary Slave.
+									  \\ \hline
+
+\end{tabular}
+\label{tab:wrDS}
+\end{table}
+
+
+=============================
+Hardware implementation of WR-Slave-enable port is much more complex then the implementation of
+WR-Master-enabled port, while the usual number of ports acting as slaves in a WR Boundary 
+Clock is foreseen to be two or one (out of around 18 total). Therefore, it is justified to introduce
+MasterOnly PTP state machine. Such solution enables to develop WR Boundary Clocks which implement 
+hardware support for Slave only on chose ports\footnote{This is the case of V2 of WR Switch. V3 
+WR Switch will enable all ports to act as Slaves}. A port running in MasterOnly mode can act only as
+a source of timing information (so-called downlink). The MasterOnly PTP state machine is presented
+in Figure~\ref{fig:ptpFSMmasterOnly}. 
+
+In case when SlaveOnly port is needed, the SlaveOnly PTP state machine defined in Figure~24 in PTP 
+standard is used (see Appendix~\ref{ptpFSM}, Figure~\ref{fig:ptpFSMslaveOnly}).
+
+\begin{figure}[ht!]
+  \centering
+  \includegraphics[width=0.85\textwidth]{fig/ptpFSMmasterOnly.ps}
+  \caption{MasterOnly PTP state machine.}
+  \label{fig:ptpFSMmasterOnly}
+\end{figure}
+
+=============================
+
+=============================
\ No newline at end of file
--- a/src/fig/SDA.ps
+++ b/src/fig/SDA.ps
--- a/src/fig/modifiedPtpFSM.ps
+++ b/src/fig/modifiedPtpFSM.ps
--- a/src/fig/ptpAndWrFSMs.ps
+++ b/src/fig/ptpAndWrFSMs.ps
--- a/src/fig/ptpFSM.ps
+++ b/src/fig/ptpFSM.ps
--- a/src/fig/ptpFSMmasterOnly.ps
+++ b/src/fig/ptpFSMmasterOnly.ps
--- a/src/fig/ptpFSMslaveOnly.ps
+++ b/src/fig/ptpFSMslaveOnly.ps
--- a/src/fig/src/PTP_FSM.cdr
+++ b/src/fig/src/PTP_FSM.cdr
--- a/src/fig/src/PTP_FSM_Master_Only.cdr
+++ b/src/fig/src/PTP_FSM_Master_Only.cdr
--- a/src/fig/src/SDA.cdr
+++ b/src/fig/src/SDA.cdr
--- a/src/fig/src/ptpFSMslaveOnly.cdr
+++ b/src/fig/src/ptpFSMslaveOnly.cdr
--- a/src/fig/src/ptpFsmAndWrFSM.cdr
+++ b/src/fig/src/ptpFsmAndWrFSM.cdr
--- a/src/wrspec.tex
+++ b/src/wrspec.tex