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White Rabbit Standardization
Commit bcbcb98d authored by Maciej Lipinski's avatar Maciej Lipinski
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wrspec.v2: last corrections

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src/fig/clocksHwSpec.ps
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src/fig/ptpAndWrFSMs.ps
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src/fig/wrFSM.ps
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src/fig/wrptpMSGs.ps
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src/from_tomeks_msc.tex
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% \def\us{\char`\_} \def\us{\char`\_}
\subsection{WR link model} \subsection{WR link model}
\label{s:link_model} \label{s:link_model}
Knowledge of the physical model of links connecting the clocks is a Knowledge of the physical model of the links connecting the clocks is a
prerequisite for achieving the required synchronization accuracy. The model prerequisite for achieving the required synchronization accuracy. The model
of a WR optical link is depicted in Figure~\ref{fig:link_model}. of a WR optical link is depicted in Figure~\ref{fig:link_model}.
\begin{figure}[ht!] \begin{figure}[ht!]
...@@ -55,14 +55,14 @@ and $T_{ref}$ is the period of Gigabit Ethernet 125 MHz reference clock (8 ns). ...@@ -55,14 +55,14 @@ and $T_{ref}$ is the period of Gigabit Ethernet 125 MHz reference clock (8 ns).
The goal of the presented model is to calculate the precise value of The goal of the presented model is to calculate the precise value of
master-to-slave offset $offset_{MS}$ by combining a coarse timestamp-based master-to-slave offset $offset_{MS}$ by combining a coarse timestamp-based
round-trip delay \ref{eq:meanPath} with precise phase measurement round-trip delay \eqref{eq:meanPath} with precise phase measurement
$phase_{MM}.$ Once the offset is computed, the WR slave can phase-shift its $phase_{MM}.$ Once the offset is computed, the WR slave can phase-shift its
recovered clock (deriving $phase_{S}$ from $offset_{MS}$) to match the phase recovered clock (deriving $phase_{S}$ from $offset_{MS}$) to match the phase
of the master clock, completing the synchronization. of the master clock, completing the synchronization.
\begin{figure}[ht!] \begin{figure}[ht!]
\centering \centering
\includegraphics[width=15cm]{fig/tomeksDrawings/sync_flow.eps} \includegraphics[width=15cm]{fig/tomeksDrawings/sync_flow.eps}
\caption{WR synchronization flow} \caption{WR synchronization flow (DMTD is explained in Appendix~\ref{s:dmtd})}
\label{fig:sync_flow} \label{fig:sync_flow}
\end{figure} \end{figure}
Determining the precise offset, however, is not a trivial task. Figure Determining the precise offset, however, is not a trivial task. Figure
...@@ -99,7 +99,7 @@ following sequence: ...@@ -99,7 +99,7 @@ following sequence:
\begin{enumerate} \begin{enumerate}
\item The master starts broadcasting \textit{ANNOUNCE} messages to look for \item The master starts broadcasting \textit{ANNOUNCE} messages to look for
a WR slave, a WR slave,
\item Eventually, the slave will respond with a \textit{SLAVE\us PRESENT} \item Eventually, the slave will respond with a \textit{SLAVE\_PRESENT}
message, indicating that it supports WR. If no response has been received message, indicating that it supports WR. If no response has been received
within a predefined time, the master assumes that the slave is not WR within a predefined time, the master assumes that the slave is not WR
compatible and aborts the synchronization process, compatible and aborts the synchronization process,
...@@ -132,18 +132,18 @@ data stream (see section 3.2.2 \cite{tomekMSC}). ...@@ -132,18 +132,18 @@ data stream (see section 3.2.2 \cite{tomekMSC}).
Let's first focus on the blocks marked blue in Let's first focus on the blocks marked blue in
Figure~\ref{fig:coarse_measurement}. Each time an SFD character is detected, Figure~\ref{fig:coarse_measurement}. Each time an SFD character is detected,
the PCS produces a timestamp trigger pulse which causes the timestaming unit the PCS produces a timestamp trigger pulse which causes the timestaming unit
to take a snapshot of the free running counter CNTR\us R with the D-type to take a snapshot of the free running counter CNTR\_R with the D-type
register DREG\us R. The counter is counting from 0 to 124999999 which (given register DREG\_R. The counter is counting from 0 to 124999999 which (given
the reference clock frequency of 125 MHz) gives a period of one full second. the reference clock frequency of 125 MHz) gives a period of one full second.
The counter CNTR\us R works synchronously to the reference clock (master side, The counter CNTR\_R works synchronously to the reference clock (master side,
signal 1 in Figure~\ref{fig:link_model}) or the compensated clock (slave side, signal 1 in Figure~\ref{fig:link_model}) or the compensated clock (slave side,
signal 5). Since RX trigger pulses come from different clock domains (2 or signal 5). Since RX trigger pulses come from different clock domains (2 or
4), they need to be synchronized to the reference clock with a chain of 4), they need to be synchronized to the reference clock with a chain of
D flip-flops (SYNC). Single-cycle long trigger pulses are widened by the D flip-flops (SYNC). Single-cycle long trigger pulses are widened by the
pulse extender before going to the synchronizer chain to ensure that no pulse extender before going to the synchronizer chain to ensure that no
pulses are missed due to the metastability of synchronizer flip-flops. The pulses are missed due to the metastability of synchronizer flip-flops. The
counter value is latched in register DREG\us R on the rising edge of the counter value is latched in register DREG\_R on the rising edge of the
synchronizer output. TX timestamp triggers, which are generated within the synchronizer output. TX timestamp triggers, which are generated within the
reference clock domain (clocks 1 or 5) also pass through a synchronizer reference clock domain (clocks 1 or 5) also pass through a synchronizer
chain to obtain identical trigger reaction latency. chain to obtain identical trigger reaction latency.
...@@ -167,8 +167,8 @@ One possible way of addressing this issue is to take RX timestamps on both ...@@ -167,8 +167,8 @@ One possible way of addressing this issue is to take RX timestamps on both
reference clock edges. The falling edge part of the TSU is marked pink in reference clock edges. The falling edge part of the TSU is marked pink in
\ref{fig:coarse_measurement}. It does not have an independent counter -- \ref{fig:coarse_measurement}. It does not have an independent counter --
instead, the current value of the rising edge counter is latched in register instead, the current value of the rising edge counter is latched in register
CNTR\us F on the falling edge of the reference clock, making the CNTR\us CNTR\_F on the falling edge of the reference clock, making the CNTR\us
F a copy of CNTR\us R delayed by a half of the clock period. This method F a copy of CNTR\_R delayed by a half of the clock period. This method
ensures that at least one of the timestamps is valid at any moment ensures that at least one of the timestamps is valid at any moment
(see Figure~\ref{fig:ts_dualedge}). The correct timestamp is chosen depending on the (see Figure~\ref{fig:ts_dualedge}). The correct timestamp is chosen depending on the
current phase shift between clocks (see section \ref{s:fine_delay}). current phase shift between clocks (see section \ref{s:fine_delay}).
...@@ -235,7 +235,7 @@ Analog DMTDs provide excellent resolution and linearity, at the cost of several ...@@ -235,7 +235,7 @@ Analog DMTDs provide excellent resolution and linearity, at the cost of several
external discrete components (mixers and filters), which can be troublesome, external discrete components (mixers and filters), which can be troublesome,
especially in multi-port applications such as the WR switch. Fortunately, the especially in multi-port applications such as the WR switch. Fortunately, the
analog mixing operation can be transformed into a digital sampling operation, analog mixing operation can be transformed into a digital sampling operation,
resulting in a digital DMTD detector, shown on fig. \ref{fig:digital_dmtd} resulting in a digital DMTD detector, shown on fig. \ref{fig:digital_dmtd}.
\begin{figure}[ht!] \begin{figure}[ht!]
\centering \centering
\includegraphics[width=12cm]{fig/tomeksDrawings/digital_dmtd.eps} \includegraphics[width=12cm]{fig/tomeksDrawings/digital_dmtd.eps}
...@@ -288,7 +288,7 @@ external components. ...@@ -288,7 +288,7 @@ external components.
\end{figure} \end{figure}
In practical DDMTD implementations, the output signals need to be additionally In practical DDMTD implementations, the output signals need to be additionally
conditioned as the input clock jitter can introduce glitches, as shown conditioned as the input clock jitter can introduce glitches, as shown
on fig. \ref{fig:dmtd_glitches}a. More details about the deglitching and on fig. \ref{fig:dmtd_glitches}. More details about the deglitching and
postprocessing algorithm can be found in section 4.3.5 of \cite{tomekMSC}. postprocessing algorithm can be found in section 4.3.5 of \cite{tomekMSC}.
\subsection{Fine delay measurement} \subsection{Fine delay measurement}
...@@ -355,8 +355,8 @@ and searching for a transition in the RX timestamp value. ...@@ -355,8 +355,8 @@ and searching for a transition in the RX timestamp value.
If the actual value of $phase_{MM}$ lies within a $\pm 25\% T_{ref}$ If the actual value of $phase_{MM}$ lies within a $\pm 25\% T_{ref}$
range from the transition point $\phi_{trans}$ (green zone in range from the transition point $\phi_{trans}$ (green zone in
\ref{fig:merging_example}), the algorithm will use $t_{4f}$ timestamp, \ref{fig:merging_example}), the algorithm will use the $t_{4f}$ timestamp,
otherwise $t_{4r}$ timestamp will be taken (red zone). Note that because otherwise the $t_{4r}$ timestamp will be taken (red zone). Note that because
$phase_{MM}$ is bounded to $\left[0, T_{ref}\right)$, the range checks must $phase_{MM}$ is bounded to $\left[0, T_{ref}\right)$, the range checks must
be aware of the jump in the phase between $T_{ref}$ and $0$. be aware of the jump in the phase between $T_{ref}$ and $0$.
...@@ -377,7 +377,7 @@ as the thick navy trace. ...@@ -377,7 +377,7 @@ as the thick navy trace.
\caption{Example of $t_{4p}$ timestamp enhancing.} \caption{Example of $t_{4p}$ timestamp enhancing.}
\label{fig:merging_example} \label{fig:merging_example}
\end{figure} \end{figure}
The enhancement operation for $t_{2}$ timestamp is done in a very The enhancement operation for the $t_{2}$ timestamp is done in a very
similar way by replacing $t_{4}$ with $t_{2}$ and $phase_{MM}$ with similar way by replacing $t_{4}$ with $t_{2}$ and $phase_{MM}$ with
$phase_{S}$. Note that changing the slave's phase shift $phase_{S}$ will $phase_{S}$. Note that changing the slave's phase shift $phase_{S}$ will
result in a change of the values of both $t_{2p}$ and $t_{4p}$ (see table result in a change of the values of both $t_{2p}$ and $t_{4p}$ (see table
...@@ -495,7 +495,7 @@ where $B_{i}$ and $C_{i}$ are material-specific coefficients. ...@@ -495,7 +495,7 @@ where $B_{i}$ and $C_{i}$ are material-specific coefficients.
For a standard G.652 telecom fiber, the refractive indexes are respectively: For a standard G.652 telecom fiber, the refractive indexes are respectively:
$n_{1550} = 1.467$ and $n_{1310} = 1.466$. In order to simplify the asymmetry $n_{1550} = 1.467$ and $n_{1310} = 1.466$. In order to simplify the asymmetry
calculations in the hardware, the WR specification defines calculations in the hardware, the WR specification defines
a custom fiber asymmetry coefficient \ref{eq:fiber_alpha1} expressing the a custom fiber asymmetry coefficient \eqref{eq:fiber_alpha1} expressing the
ratio between the M-S and S-M fiber propagation delays: ratio between the M-S and S-M fiber propagation delays:
\begin{equation} \begin{equation}
...@@ -584,7 +584,7 @@ PHYs whose maximum ($\delta_{PHY(M/S)_{max}}$) and minimum ($\delta_{PHY(M/S)_{m ...@@ -584,7 +584,7 @@ PHYs whose maximum ($\delta_{PHY(M/S)_{max}}$) and minimum ($\delta_{PHY(M/S)_{m
\label{eq:fixedDelayVariation} \label{eq:fixedDelayVariation}
\delta_{\{TX, RX\}\_PHY(M/S)_{variable}} \in \langle 0 :\delta_{PHY(M/S)_{max}} - \delta_{PHY(M/S)_{min}} \rangle \delta_{\{TX, RX\}\_PHY(M/S)_{variable}} \in \langle 0 :\delta_{PHY(M/S)_{max}} - \delta_{PHY(M/S)_{min}} \rangle
\end{equation} \end{equation}
e.g. below 10 bit times in case of Gigabit Ethernet. e.g. below 10 bit times in the case of Gigabit Ethernet.
Therefore, a fixed delay can be expressed as a sum of a constant value Therefore, a fixed delay can be expressed as a sum of a constant value
($\delta_{\{TX, RX\}\_PHY(M/S)_{min}}$) and a variable part ($\delta_{\{TX, RX\}\_PHY(M/S)_{variable}}$) which needs to be measured: ($\delta_{\{TX, RX\}\_PHY(M/S)_{min}}$) and a variable part ($\delta_{\{TX, RX\}\_PHY(M/S)_{variable}}$) which needs to be measured:
\begin{equation} \begin{equation}
...@@ -673,10 +673,10 @@ corr_{phase} = offset_{MS} - [offset_{MS}] ...@@ -673,10 +673,10 @@ corr_{phase} = offset_{MS} - [offset_{MS}]
\label{eq:corr_phase} \label{eq:corr_phase}
\end{equation} \end{equation}
\end{enumerate} \end{enumerate}
\emph{Voilà!} Now the slave's clock and PPS signals are synchronized to the \emph{Voil\`{a}!} Now the slave's clock and PPS signals are synchronized to the
master with sub-nanosecond accuracy. Since the offset can vary with operating master with sub-nanosecond accuracy. Since the offset can vary with operating
conditions, it is measured at regular intervals and the difference between conditions, it is measured at regular intervals and the difference between
subsequent measurements is added to slave's phase shift to compensate for subsequent measurements is added to the slave's phase shift to compensate for
phase drift: phase drift:
\begin{equation} \begin{equation}
corr_{phase} = offset_{MS} - offset_{MS\us previous} corr_{phase} = offset_{MS} - offset_{MS\us previous}
......
src/wrspec.tex
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