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Resource Evaluation of WR switch HDL for Ultrascale Plus
Commit 0c089ba4 authored by Maciej Lipinski's avatar Maciej Lipinski Committed by Marek Gumiński
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[PSU] simulation changes to follow the clockClass and debug RAM dump changes

parent 2aa262df
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Showing with 94 additions and 62 deletions
sim/regs/psu_regs.v
View file @ 0c089ba4
`define ADDR_PSU_PCR 5'h0
`define PSU_PCR_PSU_ENA_OFFSET 0
`define PSU_PCR_PSU_ENA 32'h00000001
`define PSU_PCR_PSU_CLR_TX_MSG_OFFSET 1
`define PSU_PCR_PSU_CLR_TX_MSG 32'h00000002
`define PSU_PCR_INJ_PRIO_OFFSET 8
`define PSU_PCR_INJ_PRIO 32'h00000700
`define PSU_PCR_HOLDOVER_CLK_CLASS_OFFSET 16
`define PSU_PCR_HOLDOVER_CLK_CLASS 32'hffff0000
`define ADDR_PSU_PTCR 5'h4
`define PSU_PTCR_SEQID_DUP_NDROP_OFFSET 0
`define PSU_PTCR_SEQID_DUP_NDROP 32'h00000001
`define PSU_PCR_HOLDOVER_CLK_CLASS 32'h00ff0000
`define ADDR_PSU_PSR 5'h4
`define PSU_PSR_HOLDOVER_ON_OFFSET 0
`define PSU_PSR_HOLDOVER_ON 32'h00000001
`define PSU_PSR_HD_MSG_RX_OFFSET 1
`define PSU_PSR_HD_MSG_RX 32'h00000002
`define PSU_PSR_HD_ON_SPLL_OFFSET 2
`define PSU_PSR_HD_ON_SPLL 32'h00000004
`define PSU_PSR_ACTIVE_REF_SPLL_OFFSET 8
`define PSU_PSR_ACTIVE_REF_SPLL 32'hffffff00
`define ADDR_PSU_PTCR 5'h8
`define PSU_PTCR_SEQID_DUP_DROP_OFFSET 0
`define PSU_PTCR_SEQID_DUP_DROP 32'h00000001
`define PSU_PTCR_SEQID_WRG_DROP_OFFSET 1
`define PSU_PTCR_SEQID_WRG_DROP 32'h00000002
`define PSU_PTCR_CLKCL_WRG_DROP_OFFSET 2
`define PSU_PTCR_CLKCL_WRG_DROP 32'h00000004
`define PSU_PTCR_PRTID_WRG_DROP_OFFSET 3
`define PSU_PTCR_PRTID_WRG_DROP 32'h00000008
`define ADDR_PSU_PRCR 5'h8
`define ADDR_PSU_PRCR 5'hc
`define PSU_PRCR_SEQID_DUP_DET_OFFSET 0
`define PSU_PRCR_SEQID_DUP_DET 32'h00000001
`define PSU_PRCR_SEQID_WRG_DET_OFFSET 1
`define PSU_PRCR_SEQID_WRG_DET 32'h00000002
`define PSU_PRCR_PRTID_WRG_DET_OFFSET 2
`define PSU_PRCR_PRTID_WRG_DET 32'h00000004
`define ADDR_PSU_RXPM 5'hc
`define ADDR_PSU_RXPM 5'h10
`define PSU_RXPM_PORT_MASK_OFFSET 0
`define PSU_RXPM_PORT_MASK 32'hffffffff
`define ADDR_PSU_TXPM 5'h10
`define ADDR_PSU_TXPM 5'h14
`define PSU_TXPM_PORT_MASK_OFFSET 0
`define PSU_TXPM_PORT_MASK 32'hffffffff
`define ADDR_PSU_PTD 5'h14
`define ADDR_PSU_PTD 5'h18
`define PSU_PTD_DBG_HOLDOVER_ON_OFFSET 0
`define PSU_PTD_DBG_HOLDOVER_ON 32'h00000001
`define PSU_PTD_TX_RAM_RD_ENA_OFFSET 1
`define PSU_PTD_TX_RAM_RD_ENA 32'h00000002
`define PSU_PTD_TX_RAM_DAT_VALID_OFFSET 1
`define PSU_PTD_TX_RAM_DAT_VALID 32'h00000002
`define PSU_PTD_TX_RAM_RD_ADR_OFFSET 4
`define PSU_PTD_TX_RAM_RD_ADR 32'h00003ff0
`define PSU_PTD_TX_RAM_RD_DAT_OFFSET 14
......
sim/simdrv_psu.svh
View file @ 0c089ba4
......@@ -17,7 +17,7 @@ class CSimDrv_PSU;
m_base = base;
endfunction // new
task init(bit[2:0] inj_prio, bit[15:0] holdover_clk_class, bit ignore_rx_port_id,
task init(bit[2:0] inj_prio, bit[7:0] holdover_clk_class, bit ignore_rx_port_id,
bit[31:0] rx_mask, bit[31:0] tx_mask );
m_acc.write(m_base + `ADDR_PSU_PCR,
......@@ -66,19 +66,36 @@ class CSimDrv_PSU;
endtask;
task dbg_dump_tx_ram();
uint64_t i;
int i=0;
int word_addr=0;
int bank=0;
uint64_t tmp;
uint64_t dat;
for(i=0;i<1024;i++)
while(i<550)
begin
m_acc.write(m_base + `ADDR_PSU_PTD,
`PSU_PTD_TX_RAM_RD_ENA |
(i << `PSU_PTD_TX_RAM_RD_ADR_OFFSET) & `PSU_PTD_TX_RAM_RD_ADR);
m_acc.read(m_base + `ADDR_PSU_PTD, tmp, 4);
dat = (tmp & `PSU_PTD_TX_RAM_RD_DAT) >> `PSU_PTD_TX_RAM_RD_DAT_OFFSET;
if((dat >> 17) & 'h1) $display("%2d: 0x4%x",i, dat);
if(tmp & `PSU_PTD_TX_RAM_DAT_VALID) //is the data valid, otherwise retry
begin
dat = (tmp & `PSU_PTD_TX_RAM_RD_DAT) >> `PSU_PTD_TX_RAM_RD_DAT_OFFSET;
if(i==0) $display("[PSU-dump] === Bank 1 === \n" );
if(i==256) $display("[PSU-dump] === Bank 2 === \n" );
if(i==512) $display("[PSU-dump] == perport === \n" );
if(i <335) $display("addr = %2d bank=%d word=%2d : 0x4%x",i, bank,word_addr, 'hFFFFF & dat);
else $display("addr = %2d port=%d word=%2d : 0x4%x",i, bank,word_addr, 'hFFFFF & dat);
i++;
if (i== 80) bank++;
else if(i==335) bank=0;
else if(i >355 && i%word_addr==0) bank++;
if(i>335 && i%word_addr==0) word_addr=0;
else word_addr++;
if(i== 80) begin i = 256; word_addr=0; bank++; end
if(i==335) begin i = 512; word_addr=0; bank=0; end
end
end
m_acc.write(m_base + `ADDR_PSU_PTD, 'h0000);
endtask;
endclass // CSimDrv_PSU
......
testbench/scb_top/main.sv
View file @ 0c089ba4
......@@ -286,22 +286,22 @@ module main;
'h00, //32 correctionField
'h00, //33 logMessageInterval
//// PTP Announce
'h00, // originalTimestamp 1
'h00, // originalTimestamp 2
'h00, // originalTimestamp 3
'h00, // originalTimestamp 4
'h00, // originalTimestamp 5
'h00, // originalTimestamp 6
'h00, // originalTimestamp 7
'h00, // originalTimestamp 8
'h00, // originalTimestamp 9
'h00, // originalTimestamp 10
'h00, // currentUtcOffset 1
'h00, // currentUtcOffset 2
'h00, // reserved
'h00, // grandmasterPriorit1
'h07, // gandmasterClockQuality 1 -> clockClass ?
'h00, // gandmasterClockQuality 2 -> clockAccuracy
'h00, //34 originalTimestamp 1
'h00, //35 originalTimestamp 2
'h00, //36 originalTimestamp 3
'h00, //37 originalTimestamp 4
'h00, //38 originalTimestamp 5
'h00, //39 originalTimestamp 6
'h00, //40 originalTimestamp 7
'h00, //41 originalTimestamp 8
'h00, //42 originalTimestamp 9
'h00, //43 originalTimestamp 10
'h00, //44 currentUtcOffset 1
'h00, //45 currentUtcOffset 2
'h00, //46 reserved
'h00, //47 grandmasterPriorit1
'h07, //48 gandmasterClockQuality 1 -> clockClass ?
'h00, //49 gandmasterClockQuality 2 -> clockAccuracy
'h00, // gandmasterClockQuality 3 -> offsetScaledLogVariance;
'h00 // gandmasterClockQuality 4 -> offsetScaledLogVariance;
};
......@@ -357,9 +357,9 @@ module main;
int g_simple_allocator_unicast_check = 0;
integer g_send_announce_from_NIC = 0;
reg [g_max_ports-1:0] announceTxVector = 18'b111111111111111111;
reg [g_max_ports-1:0] announceTxVector = 18'b000000000000000000;
reg [31:0] psu_tx_mask = 18'b000000000000001111;
reg [31:0] psu_rx_mask = 18'b000000000000001000;
reg [31:0] psu_rx_mask = 18'b100000000000000000;
reg [15:0] psu_hldvr_clk_class= 7;
reg [ 2:0] psu_inj_prio = 0;
bit ignore_rx_port_id = 0;
......@@ -2936,19 +2936,23 @@ module main;
initial begin
// portUnderTest = 18'b100000000000001100;
// portUnderTest = 18'b100000000000001000;
portUnderTest = 18'b000000000000000000;
announceTxVector = 18'b000000000000000100;
announceTxVector = 18'b001000000100000100;
psu_tx_mask = 18'b001000000000001111;
g_psu_test = 1;
// tx ,rx ,opt
trans_paths[2] = '{2 ,0 , 8};
trans_paths[3] = '{3 ,0 , 8 };
// trans_paths[11] = '{11 ,6 , 0 };
trans_paths[17] = '{17 ,0 , 8 };
repeat_number = 10;
repeat_number = 15;
tries_number = 1;
g_enable_pck_gaps = 1;
g_min_pck_gap = 500;
g_max_pck_gap = 520;
g_min_pck_gap = 1000;
g_max_pck_gap = 1200;
g_force_payload_size = 0; //size per option
......@@ -2961,8 +2965,8 @@ module main;
for(int i=0;i<ANNOUNCE_templ.size();i++)
ptpAnnounce.payload[i] = ANNOUNCE_templ[i];
g_send_announce_from_NIC = 10; // ten times to all ports
g_psu_test =1;
g_send_announce_from_NIC = 4; // ten times to all ports
g_psu_test = 0;
end
//*/
//////////////////////////////////////////////////////////////////////////////////////////////
......@@ -3164,8 +3168,9 @@ module main;
for(int i=0;i<ANNOUNCE_templ.size();i++)
pkt.payload[i] = ANNOUNCE_templ[i];
pkt.payload[28] = srcPort;
pkt.payload[30] = i;
pkt.payload[29] = srcPort;
pkt.payload[31] = i;
pkt.payload[48] = 5+i%3;
end
if(opt == 444)
pkt.src[4] = dmac_dist++;
......@@ -4680,28 +4685,27 @@ module main;
begin
if(g_send_announce_from_NIC > 0)
begin
automatic int an_i = 0;
automatic int an_j = 0;
ptpAnnounce.tx_wr_port = 0;
wait_cycles(100);
for (int an_i =0;an_i<g_send_announce_from_NIC;an_i++)
for (an_i =0;an_i<g_send_announce_from_NIC;an_i++)
begin
for(int an_j = 0;an_j<g_num_ports;an_j++)
for(an_j = 0;an_j<g_num_ports;an_j++)
begin
automatic int an_jj=an_j;
if(announceTxVector[an_jj])
if(announceTxVector[an_j])
begin
wait_cycles(100);
ptpAnnounce.tx_wr_port = an_jj; // port to send
ptpAnnounce.payload[28]= 'h00 ; // seqID 1
ptpAnnounce.payload[29]= an_jj % 'hFF; // seqID 2
ptpAnnounce.payload[30]= 'h00; // seqID 1
ptpAnnounce.payload[31]= an_i % 'hFF; // seqID 2
ptpAnnounce.tx_wr_port = an_j; // port to send
ptpAnnounce.payload[28]= 'h00 ; // Port number
ptpAnnounce.payload[29]= an_j % 'hFF; // Port number
ptpAnnounce.payload[30]= 'h00; // seqID 1
ptpAnnounce.payload[31]= an_i % 'hFF; // seqID 2
$display("NIC: tx-ing PTP announce: port = %2d | ID= %2d", an_j,an_i);
// while(nic.tx_irq_enabled) wait_cycles(100);
ports[18].send.send(ptpAnnounce); //nic
wait_cycles(800);
end
else
wait_cycles(20);
end
end
......@@ -4711,15 +4715,15 @@ module main;
fork // testing PSU
begin
if(g_psu_test > 0)
// if(g_psu_test > 0)
begin
wait_cycles(100);
psu.enable(1);
wait_cycles(1300);
wait_cycles(600);
psu.dbg_holdover(1);
wait_cycles(1300);
wait_cycles(1700);
psu.dbg_holdover(0);
wait_cycles(1300);
wait_cycles(10000);
psu.dbg_dump_tx_ram();
end
end
......
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