Skip to content

R
Resource Evaluation of WR switch HDL for Ultrascale Plus
Commit 187fda19 authored by Marek Gumiński's avatar Marek Gumiński
Browse files
Options

Fixed NIC in a way that doesn't break endpoint

parent a95b339d
Hide whitespace changes
Inline Side-by-side
Showing with 7 additions and 7 deletions
ip_cores/wr-cores-local/modules/wr_nic/nic_elastic_buffer.vhd
View file @ 187fda19
......@@ -54,7 +54,7 @@ entity nic_elastic_buffer is
snk_i : in t_wrf_sink_in;
snk_o : out t_wrf_sink_out;
fab_o : out t_ep_internal_fabric;
fab_o : out t_ep_internal_fabric64;
dreq_i : in std_logic
);
......@@ -90,8 +90,8 @@ architecture rtl of nic_elastic_buffer is
signal cyc_d0 : std_logic;
signal fifo_in : t_ep_internal_fabric;
signal fifo_out : t_ep_internal_fabric;
signal fifo_in : t_ep_internal_fabric64;
signal fifo_out : t_ep_internal_fabric64;
signal snk_out : t_wrf_sink_out;
signal stall_int : std_logic;
......
ip_cores/wr-cores-local/modules/wr_nic/nic_rx_fsm.vhd
View file @ 187fda19
......@@ -119,7 +119,7 @@ architecture behavioral of NIC_RX_FSM is
rst_n_i : in std_logic;
snk_i : in t_wrf_sink_in;
snk_o : out t_wrf_sink_out;
fab_o : out t_ep_internal_fabric;
fab_o : out t_ep_internal_fabric64;
dreq_i : in std_logic);
end component;
......@@ -163,7 +163,7 @@ architecture behavioral of NIC_RX_FSM is
signal increase_addr : std_logic;
signal fab_in : t_ep_internal_fabric;
signal fab_in : t_ep_internal_fabric64;
signal fab_dreq : std_logic;
signal bw_src_out : t_wrf_source_out;
......@@ -394,10 +394,10 @@ begin
-- CPU is big-endian
if(rx_rdreg_toggle = '0') then
-- 1st word
rx_buf_data(31 downto 16) <= fab_in.data;
rx_buf_data(31 downto 16) <= fab_in.data(31 downto 16);
else
-- 2nd word
rx_buf_data(15 downto 0) <= fab_in.data;
rx_buf_data(15 downto 0) <= fab_in.data(15 downto 0);
end if;
else
-- CPU is little endian
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment