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Resource Evaluation of WR switch HDL for Ultrascale Plus
Commit 21de71de authored by Marek Gumiński's avatar Marek Gumiński
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Instantiated 10GB transceivers 

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parent c0b7deb8
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ip_cores/wr-cores-local/modules/wr_endpoint/endpoint_pkg.vhd
View file @ 21de71de
......@@ -441,7 +441,7 @@ package body endpoint_pkg is
return integer is
begin
if (pcs_16) then
return 16;
return 64;
else
return 8;
end if;
......@@ -451,7 +451,7 @@ package body endpoint_pkg is
return integer is
begin
if (pcs_16) then
return 2;
return 8;
else
return 1;
end if;
......
top/bare_top/scb_top_bare.vhd
View file @ 21de71de
......@@ -792,8 +792,8 @@ begin
phy_loopen_o => phys_o(i).loopen,
phy_rdy_i => phys_i(i).rdy,
phy_ref_clk_i => phys_i(i).ref_clk,
phy_tx_data_o => ep_dbg_data_array(i), -- phys_o(i).tx_data, --
phy_tx_k_o => ep_dbg_k_array(i), -- phys_o(i).tx_k, --
phy_tx_data_o => phys_o(i).tx_data, --
phy_tx_k_o => phys_o(i).tx_k, --
phy_tx_disparity_i => phys_i(i).tx_disparity,
phy_tx_enc_err_i => phys_i(i).tx_enc_err,
phy_rx_data_i => phys_i(i).rx_data,
......
top/bare_top/wrsw_top_pkg.vhd
View file @ 21de71de
......@@ -49,17 +49,17 @@ package wrsw_top_pkg is
loopen : std_logic;
enable : std_logic;
syncen : std_logic;
tx_data : std_logic_vector(15 downto 0);
tx_k : std_logic_vector(1 downto 0);
tx_data : std_logic_vector(63 downto 0);
tx_k : std_logic_vector(7 downto 0);
end record;
type t_phyif_input is record
ref_clk : std_logic;
tx_disparity : std_logic;
tx_enc_err : std_logic;
rx_data : std_logic_vector(15 downto 0);
rx_data : std_logic_vector(63 downto 0);
rx_clk : std_logic;
rx_k : std_logic_vector(1 downto 0);
rx_k : std_logic_vector(7 downto 0);
rx_enc_err : std_logic;
rx_bitslide : std_logic_vector(4 downto 0);
rdy : std_logic;
......
top/scb_18ports/scb_top_synthesis.vhd
View file @ 21de71de
......@@ -258,7 +258,7 @@ architecture Behavioral of scb_top_synthesis is
signal clk_aux : std_logic;
signal clk_gtx_ibuf : std_logic_vector(5-1 downto 0);
signal clk_gtx : std_logic_vector(c_NUM_PHYS-1 downto 0);
signal clk_gtx : std_logic_vector(5-1 downto 0);
signal cpu_nwait_int : std_logic;
......@@ -556,24 +556,20 @@ begin
-- GTX PHYs
-------------------------------------------------------------------------------
clk_gtx(3 downto 0) <= (others => clk_gtx_ibuf(0));
clk_gtx(7 downto 4) <= (others => clk_gtx_ibuf(1));
clk_gtx(11 downto 8) <= (others => clk_gtx_ibuf(2));
clk_gtx(15 downto 12) <= (others => clk_gtx_ibuf(3));
clk_gtx(17 downto 16) <= (others => clk_gtx_ibuf(4));
clk_gtx <= clk_gtx_ibuf;
phy_block: block
signal to_phys_tx_data : STD_LOGIC_VECTOR(c_NUM_PHYS*16-1 DOWNTO 0);
signal to_phys_tx_data : STD_LOGIC_VECTOR(c_NUM_PHYS*64-1 DOWNTO 0);
signal to_phys_tx_k : STD_LOGIC_VECTOR(c_NUM_PHYS*8-1 DOWNTO 0);
signal to_phys_rst : STD_LOGIC;
signal from_phys_rx_data : STD_LOGIC_VECTOR(c_NUM_PHYS*16-1 DOWNTO 0);
signal from_phys_rx_data : STD_LOGIC_VECTOR(c_NUM_PHYS*64-1 DOWNTO 0);
signal from_phys_rx_k : STD_LOGIC_VECTOR(c_NUM_PHYS*16-1 DOWNTO 0);
signal from_phys_disp_err : STD_LOGIC_VECTOR(c_NUM_PHYS*16-1 DOWNTO 0);
signal from_phys_rx_comma : STD_LOGIC_VECTOR(c_NUM_PHYS*8-1 DOWNTO 0);
signal from_phys_enc_err : STD_LOGIC_VECTOR(c_NUM_PHYS*8-1 DOWNTO 0);
signal c25m_to_phys_rst : STD_LOGIC;
signal from_phys_tx_enc_err_common : STD_LOGIC;
......@@ -616,17 +612,15 @@ begin
--change from long vectors to records
concatenate_gen : for i in 0 to c_NUM_PHYS-1 generate
to_phys_tx_data(16*(i+1)-1 downto 16*i)
to_phys_tx_data(64*(i+1)-1 downto 64*i)
<= to_phys(i).tx_data;
--not sure if it shouldn't be swapped
to_phys_tx_k(8*i) <= to_phys(i).tx_k(0);
to_phys_tx_k(8*i+1) <= to_phys(i).tx_k(1);
to_phys_tx_k(8*(i+1)-1 downto 8*i+2) <= (others=>'0');
to_phys_tx_k(8*(i+1)-1 downto 8*i) <= to_phys(i).tx_k;
from_phys(i).rx_clk <= rxusrclk2(i);
from_phys(i).rx_data <= from_phys_rx_data(16*(i+1)-1 downto 16*i);
from_phys(i).rx_data <= from_phys_rx_data(64*(i+1)-1 downto 64*i);
-- actually only bits 0 and 1 out out 16 assigned to each channels are used
from_phys(i).tx_disparity <= or_reduce( from_phys_disp_err(16*(i+1)-1 downto 16*i ) );
......@@ -635,7 +629,7 @@ begin
from_phys(i).tx_enc_err <= from_phys_tx_enc_err_common;
-- actually only bits 0 and 1 out out 16 assigned to each channels are used
from_phys(i).rx_k <= from_phys_rx_comma(8*(i+1)-7 downto 8*i );
from_phys(i).rx_k <= from_phys_rx_comma(8*(i+1)-1 downto 8*i );
-- actually only bits 0 and 1 out out 16 assigned to each channels are used
from_phys(i).rx_enc_err <= or_reduce( from_phys_enc_err(8*(i+1)-1 downto 8*i ) );
......@@ -693,9 +687,8 @@ begin
end generate;
phys: entity work.gtwizard_ultrascale_1
port map(
gtwiz_userclk_tx_reset_in(0) => c25m_to_phys_rst,
phys: entity work.transceivers_10gb
port map(
gtwiz_userclk_tx_active_in(0) => '1',
gtwiz_userclk_rx_active_in(0) => '1',
gtwiz_buffbypass_tx_reset_in => (others => c25m_to_phys_rst),
......@@ -707,31 +700,30 @@ phys: entity work.gtwizard_ultrascale_1
gtwiz_buffbypass_rx_start_user_in => (others => '0'),
gtwiz_buffbypass_rx_done_out => open,
gtwiz_buffbypass_rx_error_out => open,
gtwiz_reset_clk_freerun_in => (others => clk_25mhz),
gtwiz_reset_all_in => (others => c25m_to_phys_rst),
gtwiz_reset_tx_pll_and_datapath_in => (others => '0'),
gtwiz_reset_tx_datapath_in => (others => '0'),
gtwiz_reset_rx_pll_and_datapath_in => (others => '0'),
gtwiz_reset_rx_datapath_in => (others => '0'),
gtwiz_reset_rx_cdr_stable_out => open,
gtwiz_reset_tx_done_out => open,
gtwiz_reset_rx_done_out => open,
gtwiz_userdata_tx_in => to_phys_tx_data,
gtwiz_userdata_rx_out => from_phys_rx_data,
drpclk_in => (others => clk_25mhz ),
gtwiz_reset_clk_freerun_in => (others => clk_25mhz),
gtwiz_reset_all_in => (others => c25m_to_phys_rst),
gtwiz_reset_tx_pll_and_datapath_in => (others => '0'),
gtwiz_reset_tx_datapath_in => (others => '0'),
gtwiz_reset_rx_pll_and_datapath_in => (others => '0'),
gtwiz_reset_rx_datapath_in => (others => '0'),
gtwiz_reset_rx_cdr_stable_out => open,
gtwiz_reset_tx_done_out => open,
gtwiz_reset_rx_done_out => open,
gtwiz_userdata_tx_in => to_phys_tx_data,
gtwiz_userdata_rx_out => from_phys_rx_data,
gtrefclk00_in => clk_gtx,
qpll0outclk_out => open,
qpll0outrefclk_out => open,
gthrxn_in => gtx_rxn_i,
gthrxp_in => gtx_rxp_i,
gtrefclk0_in => clk_gtx,
rx8b10ben_in => (others => '1'),
rxusrclk_in => rxusrclk2,
rxusrclk2_in => rxusrclk2,
tx8b10ben_in => (others => '1'),
-- Set High (on TXCTRL1) to work with TXCTRL0 to force running disparity negative or positive when encoding TXDATA.
-- Set Low to use normal running disparity.
......@@ -741,7 +733,6 @@ phys: entity work.gtwizard_ultrascale_1
txctrl2_in => to_phys_tx_k,
txusrclk_in => txusrclk2,
txusrclk2_in => txusrclk2,
gthtxn_out => gtx_txn_o,
gthtxp_out => gtx_txp_o,
gtpowergood_out => open,
......
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