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Resource Evaluation of WR switch HDL for Ultrascale Plus
Commit 2bbec1ac authored by Marek Gumiński's avatar Marek Gumiński
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Removed async groups. 

Seems like the clock names has changed and these commands caused critical warnings.
I'm not implementing the design for now so it doesn't matter.
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top/scb_18ports/scb_top_synthesis.xdc
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...@@ -13,127 +13,6 @@ create_clock -period 8.000 -name clk_gtx_4 -waveform {0.000 4.000} [get_ports {g ...@@ -13,127 +13,6 @@ create_clock -period 8.000 -name clk_gtx_4 -waveform {0.000 4.000} [get_ports {g
set_clock_groups -asynchronous -group phy_block.phys/inst/gen_gtwizard_gthe4_top.gtwizard_ultrascale_1_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[4].gtwizard_ultrascale_v1_7_2_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_2_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O
set_clock_groups -asynchronous -group phy_block.phys/inst/gen_gtwizard_gthe4_top.gtwizard_ultrascale_1_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[5].gtwizard_ultrascale_v1_7_2_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_2_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O
set_clock_groups -asynchronous -group phy_block.phys/inst/gen_gtwizard_gthe4_top.gtwizard_ultrascale_1_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[6].gtwizard_ultrascale_v1_7_2_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_2_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O
set_clock_groups -asynchronous -group phy_block.phys/inst/gen_gtwizard_gthe4_top.gtwizard_ultrascale_1_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[7].gtwizard_ultrascale_v1_7_2_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_2_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O
set_clock_groups -asynchronous -group phy_block.phys/inst/gen_gtwizard_gthe4_top.gtwizard_ultrascale_1_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[8].gtwizard_ultrascale_v1_7_2_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_2_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O
set_clock_groups -asynchronous -group phy_block.phys/inst/gen_gtwizard_gthe4_top.gtwizard_ultrascale_1_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[9].gtwizard_ultrascale_v1_7_2_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_2_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O
set_clock_groups -asynchronous -group phy_block.phys/inst/gen_gtwizard_gthe4_top.gtwizard_ultrascale_1_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[10].gtwizard_ultrascale_v1_7_2_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_2_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O
set_clock_groups -asynchronous -group phy_block.phys/inst/gen_gtwizard_gthe4_top.gtwizard_ultrascale_1_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[11].gtwizard_ultrascale_v1_7_2_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_2_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O
set_clock_groups -asynchronous -group phy_block.phys/inst/gen_gtwizard_gthe4_top.gtwizard_ultrascale_1_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[12].gtwizard_ultrascale_v1_7_2_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_2_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O
set_clock_groups -asynchronous -group phy_block.phys/inst/gen_gtwizard_gthe4_top.gtwizard_ultrascale_1_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[13].gtwizard_ultrascale_v1_7_2_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_2_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O
set_clock_groups -asynchronous -group phy_block.phys/inst/gen_gtwizard_gthe4_top.gtwizard_ultrascale_1_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[14].gtwizard_ultrascale_v1_7_2_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_2_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O
set_clock_groups -asynchronous -group phy_block.phys/inst/gen_gtwizard_gthe4_top.gtwizard_ultrascale_1_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[15].gtwizard_ultrascale_v1_7_2_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_2_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O
set_clock_groups -asynchronous -group phy_block.phys/inst/gen_gtwizard_gthe4_top.gtwizard_ultrascale_1_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[16].gtwizard_ultrascale_v1_7_2_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_2_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O
set_clock_groups -asynchronous -group phy_block.phys/inst/gen_gtwizard_gthe4_top.gtwizard_ultrascale_1_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[17].gtwizard_ultrascale_v1_7_2_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_2_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O
set_clock_groups -asynchronous -group clk_boot
set_clock_groups -asynchronous -group clk_dmtd
set_clock_groups -asynchronous -group clk_ref
set_clock_groups -asynchronous -group clk_gtx_0
set_clock_groups -asynchronous -group clk_gtx_1
set_clock_groups -asynchronous -group clk_gtx_2
set_clock_groups -asynchronous -group clk_gtx_3
set_clock_groups -asynchronous -group clk_gtx_4
set_clock_groups -asynchronous -group gtrefclkmonitor_out[0]
set_clock_groups -asynchronous -group rxoutclk_out[0]
set_clock_groups -asynchronous -group GTHE4_CHANNEL_RXOUTCLKPCS[0]
set_clock_groups -asynchronous -group txoutclk_out[0]
set_clock_groups -asynchronous -group txoutclkpcs_out[0]
set_clock_groups -asynchronous -group gtrefclkmonitor_out[1]
set_clock_groups -asynchronous -group rxoutclk_out[1]
set_clock_groups -asynchronous -group GTHE4_CHANNEL_RXOUTCLKPCS[1]
set_clock_groups -asynchronous -group txoutclk_out[1]
set_clock_groups -asynchronous -group txoutclkpcs_out[1]
set_clock_groups -asynchronous -group gtrefclkmonitor_out[2]
set_clock_groups -asynchronous -group rxoutclk_out[2]
set_clock_groups -asynchronous -group GTHE4_CHANNEL_RXOUTCLKPCS[2]
set_clock_groups -asynchronous -group txoutclk_out[2]
set_clock_groups -asynchronous -group txoutclkpcs_out[2]
set_clock_groups -asynchronous -group gtrefclkmonitor_out[3]
set_clock_groups -asynchronous -group rxoutclk_out[3]
set_clock_groups -asynchronous -group GTHE4_CHANNEL_RXOUTCLKPCS[3]
set_clock_groups -asynchronous -group txoutclk_out[3]
set_clock_groups -asynchronous -group txoutclkpcs_out[3]
set_clock_groups -asynchronous -group gtrefclkmonitor_out[0]_1
set_clock_groups -asynchronous -group rxoutclk_out[0]_1
set_clock_groups -asynchronous -group GTHE4_CHANNEL_RXOUTCLKPCS[0]_1
set_clock_groups -asynchronous -group txoutclk_out[0]_1
set_clock_groups -asynchronous -group txoutclkpcs_out[0]_1
set_clock_groups -asynchronous -group gtrefclkmonitor_out[1]_1
set_clock_groups -asynchronous -group rxoutclk_out[1]_1
set_clock_groups -asynchronous -group GTHE4_CHANNEL_RXOUTCLKPCS[1]_1
set_clock_groups -asynchronous -group txoutclk_out[1]_1
set_clock_groups -asynchronous -group txoutclkpcs_out[1]_1
set_clock_groups -asynchronous -group gtrefclkmonitor_out[2]_1
set_clock_groups -asynchronous -group rxoutclk_out[2]_1
set_clock_groups -asynchronous -group GTHE4_CHANNEL_RXOUTCLKPCS[2]_1
set_clock_groups -asynchronous -group txoutclk_out[2]_1
set_clock_groups -asynchronous -group txoutclkpcs_out[2]_1
set_clock_groups -asynchronous -group gtrefclkmonitor_out[3]_1
set_clock_groups -asynchronous -group rxoutclk_out[3]_1
set_clock_groups -asynchronous -group GTHE4_CHANNEL_RXOUTCLKPCS[3]_1
set_clock_groups -asynchronous -group txoutclk_out[3]_1
set_clock_groups -asynchronous -group txoutclkpcs_out[3]_1
set_clock_groups -asynchronous -group gtrefclkmonitor_out[0]_2
set_clock_groups -asynchronous -group rxoutclk_out[0]_2
set_clock_groups -asynchronous -group GTHE4_CHANNEL_RXOUTCLKPCS[0]_2
set_clock_groups -asynchronous -group txoutclk_out[0]_2
set_clock_groups -asynchronous -group txoutclkpcs_out[0]_2
set_clock_groups -asynchronous -group gtrefclkmonitor_out[1]_2
set_clock_groups -asynchronous -group rxoutclk_out[1]_2
set_clock_groups -asynchronous -group GTHE4_CHANNEL_RXOUTCLKPCS[1]_2
set_clock_groups -asynchronous -group txoutclk_out[1]_2
set_clock_groups -asynchronous -group txoutclkpcs_out[1]_2
set_clock_groups -asynchronous -group gtrefclkmonitor_out[2]_2
set_clock_groups -asynchronous -group rxoutclk_out[2]_2
set_clock_groups -asynchronous -group GTHE4_CHANNEL_RXOUTCLKPCS[2]_2
set_clock_groups -asynchronous -group txoutclk_out[2]_2
set_clock_groups -asynchronous -group txoutclkpcs_out[2]_2
set_clock_groups -asynchronous -group gtrefclkmonitor_out[3]_2
set_clock_groups -asynchronous -group rxoutclk_out[3]_2
set_clock_groups -asynchronous -group GTHE4_CHANNEL_RXOUTCLKPCS[3]_2
set_clock_groups -asynchronous -group txoutclk_out[3]_2
set_clock_groups -asynchronous -group txoutclkpcs_out[3]_2
set_clock_groups -asynchronous -group gtrefclkmonitor_out[0]_3
set_clock_groups -asynchronous -group rxoutclk_out[0]_3
set_clock_groups -asynchronous -group GTHE4_CHANNEL_RXOUTCLKPCS[0]_3
set_clock_groups -asynchronous -group txoutclk_out[0]_3
set_clock_groups -asynchronous -group txoutclkpcs_out[0]_3
set_clock_groups -asynchronous -group gtrefclkmonitor_out[1]_3
set_clock_groups -asynchronous -group rxoutclk_out[1]_3
set_clock_groups -asynchronous -group GTHE4_CHANNEL_RXOUTCLKPCS[1]_3
set_clock_groups -asynchronous -group txoutclk_out[1]_3
set_clock_groups -asynchronous -group txoutclkpcs_out[1]_3
set_clock_groups -asynchronous -group gtrefclkmonitor_out[2]_3
set_clock_groups -asynchronous -group rxoutclk_out[2]_3
set_clock_groups -asynchronous -group GTHE4_CHANNEL_RXOUTCLKPCS[2]_3
set_clock_groups -asynchronous -group txoutclk_out[2]_3
set_clock_groups -asynchronous -group txoutclkpcs_out[2]_3
set_clock_groups -asynchronous -group gtrefclkmonitor_out[3]_3
set_clock_groups -asynchronous -group rxoutclk_out[3]_3
set_clock_groups -asynchronous -group GTHE4_CHANNEL_RXOUTCLKPCS[3]_3
set_clock_groups -asynchronous -group txoutclk_out[3]_3
set_clock_groups -asynchronous -group txoutclkpcs_out[3]_3
set_clock_groups -asynchronous -group gtrefclkmonitor_out[0]_4
set_clock_groups -asynchronous -group rxoutclk_out[0]_4
set_clock_groups -asynchronous -group GTHE4_CHANNEL_RXOUTCLKPCS[0]_4
set_clock_groups -asynchronous -group txoutclk_out[0]_4
set_clock_groups -asynchronous -group txoutclkpcs_out[0]_4
set_clock_groups -asynchronous -group gtrefclkmonitor_out[1]_4
set_clock_groups -asynchronous -group rxoutclk_out[1]_4
set_clock_groups -asynchronous -group GTHE4_CHANNEL_RXOUTCLKPCS[1]_4
set_clock_groups -asynchronous -group txoutclk_out[1]_4
set_clock_groups -asynchronous -group txoutclkpcs_out[1]_4
set_clock_groups -asynchronous -group clk_sys_startup
set_clock_groups -asynchronous -group clkout0
set_clock_groups -asynchronous -group clk_fb
set_clock_groups -asynchronous -group clk_500
set_clock_groups -asynchronous -group clk_fb_1
set_clock_groups -asynchronous -group clk_500_1
set_property PACKAGE_PIN D10 [get_ports {cpu_addr_i[0]}] set_property PACKAGE_PIN D10 [get_ports {cpu_addr_i[0]}]
set_property PACKAGE_PIN F12 [get_ports {cpu_addr_i[1]}] set_property PACKAGE_PIN F12 [get_ports {cpu_addr_i[1]}]
set_property PACKAGE_PIN E12 [get_ports {cpu_addr_i[2]}] set_property PACKAGE_PIN E12 [get_ports {cpu_addr_i[2]}]
......
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